arch/mips/ddb5xxx/ddb5477/int-handler.S

   1 /*
   2  * Copyright 2001 MontaVista Software Inc.
   3  * Author: jsun@mvista.com or jsun@junsun.net
   4  *
   5  * First-level interrupt dispatcher for ddb5477
   6  *
   7  * This program is free software; you can redistribute  it and/or modify it
   8  * under  the terms of  the GNU General  Public License as published by the
   9  * Free Software Foundation;  either version 2 of the  License, or (at your
  10  * option) any later version.
  11  */
  12 #include <asm/asm.h>
  13 #include <asm/mipsregs.h>
  14 #include <asm/addrspace.h>
  15 #include <asm/regdef.h>
  16 #include <asm/stackframe.h>
  17 #include <asm/ddb5xxx/ddb5477.h>
  18
  19 /*
  20  * first level interrupt dispatcher for ocelot board -
  21  * We check for the timer first, then check PCI ints A and D.
  22  * Then check for serial IRQ and fall through.
  23  */
  24         .align  5
  25         NESTED(ddb5477_handle_int, PT_SIZE, sp)
  26         SAVE_ALL
  27         CLI
  28         .set    at
  29         .set    noreorder
  30         mfc0    t0, CP0_CAUSE
  31         mfc0    t2, CP0_STATUS
  32
  33         and     t0, t2
  34
  35         andi    t1, t0, STATUSF_IP7     /* cpu timer */
  36         bnez    t1, ll_cputimer_irq
  37         andi    t1, t0, (STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP5 | STATUSF_IP6 )
  38         bnez    t1, ll_vrc5477_irq
  39         andi    t1, t0, STATUSF_IP0     /* software int 0 */
  40         bnez    t1, ll_cpu_ip0
  41         andi    t1, t0, STATUSF_IP1     /* software int 1 */
  42         bnez    t1, ll_cpu_ip1
  43         nop
  44         .set    reorder
  45
  46         /* wrong alarm or masked ... */
  47         j       spurious_interrupt
  48         nop
  49         END(ddb5477_handle_int)
  50
  51         .align  5
  52
  53 ll_vrc5477_irq:
  54         move    a0, sp
  55         jal     vrc5477_irq_dispatch
  56         j       ret_from_irq
  57
  58 ll_cputimer_irq:
  59         li      a0, CPU_IRQ_BASE + 7
  60         move    a1, sp
  61         jal     do_IRQ
  62         j       ret_from_irq
  63
  64
  65 ll_cpu_ip0:
  66         li      a0, CPU_IRQ_BASE + 0
  67         move    a1, sp
  68         jal     do_IRQ
  69         j       ret_from_irq
  70
  71 ll_cpu_ip1:
  72         li      a0, CPU_IRQ_BASE + 1
  73         move    a1, sp
  74         jal     do_IRQ
  75         j       ret_from_irq