arch/mips/include/asm/cpu-features.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2003, 2004 Ralf Baechle
   7  * Copyright (C) 2004  Maciej W. Rozycki
   8  */
   9 #ifndef __ASM_CPU_FEATURES_H
  10 #define __ASM_CPU_FEATURES_H
  11
  12 #include <asm/cpu.h>
  13 #include <asm/cpu-info.h>
  14 #include <cpu-feature-overrides.h>
  15
  16 /*
  17  * SMP assumption: Options of CPU 0 are a superset of all processors.
  18  * This is true for all known MIPS systems.
  19  */
  20 #ifndef cpu_has_tlb
  21 #define cpu_has_tlb             (cpu_data[0].options & MIPS_CPU_TLB)
  22 #endif
  23 #ifndef cpu_has_tlbinv
  24 #define cpu_has_tlbinv          (cpu_data[0].options & MIPS_CPU_TLBINV)
  25 #endif
  26 #ifndef cpu_has_segments
  27 #define cpu_has_segments        (cpu_data[0].options & MIPS_CPU_SEGMENTS)
  28 #endif
  29 #ifndef cpu_has_eva
  30 #define cpu_has_eva             (cpu_data[0].options & MIPS_CPU_EVA)
  31 #endif
  32 #ifndef cpu_has_htw
  33 #define cpu_has_htw             (cpu_data[0].options & MIPS_CPU_HTW)
  34 #endif
  35 #ifndef cpu_has_rixiex
  36 #define cpu_has_rixiex          (cpu_data[0].options & MIPS_CPU_RIXIEX)
  37 #endif
  38 #ifndef cpu_has_maar
  39 #define cpu_has_maar            (cpu_data[0].options & MIPS_CPU_MAAR)
  40 #endif
  41 #ifndef cpu_has_rw_llb
  42 #define cpu_has_rw_llb          (cpu_data[0].options & MIPS_CPU_RW_LLB)
  43 #endif
  44
  45 /*
  46  * For the moment we don't consider R6000 and R8000 so we can assume that
  47  * anything that doesn't support R4000-style exceptions and interrupts is
  48  * R3000-like.  Users should still treat these two macro definitions as
  49  * opaque.
  50  */
  51 #ifndef cpu_has_3kex
  52 #define cpu_has_3kex            (!cpu_has_4kex)
  53 #endif
  54 #ifndef cpu_has_4kex
  55 #define cpu_has_4kex            (cpu_data[0].options & MIPS_CPU_4KEX)
  56 #endif
  57 #ifndef cpu_has_3k_cache
  58 #define cpu_has_3k_cache        (cpu_data[0].options & MIPS_CPU_3K_CACHE)
  59 #endif
  60 #define cpu_has_6k_cache        0
  61 #define cpu_has_8k_cache        0
  62 #ifndef cpu_has_4k_cache
  63 #define cpu_has_4k_cache        (cpu_data[0].options & MIPS_CPU_4K_CACHE)
  64 #endif
  65 #ifndef cpu_has_tx39_cache
  66 #define cpu_has_tx39_cache      (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
  67 #endif
  68 #ifndef cpu_has_octeon_cache
  69 #define cpu_has_octeon_cache    0
  70 #endif
  71 /* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work.  */
  72 #ifndef cpu_has_fpu
  73 #define cpu_has_fpu             (current_cpu_data.options & MIPS_CPU_FPU)
  74 #define raw_cpu_has_fpu         (raw_current_cpu_data.options & MIPS_CPU_FPU)
  75 #else
  76 #define raw_cpu_has_fpu         cpu_has_fpu
  77 #endif
  78 #ifndef cpu_has_32fpr
  79 #define cpu_has_32fpr           (cpu_data[0].options & MIPS_CPU_32FPR)
  80 #endif
  81 #ifndef cpu_has_counter
  82 #define cpu_has_counter         (cpu_data[0].options & MIPS_CPU_COUNTER)
  83 #endif
  84 #ifndef cpu_has_watch
  85 #define cpu_has_watch           (cpu_data[0].options & MIPS_CPU_WATCH)
  86 #endif
  87 #ifndef cpu_has_divec
  88 #define cpu_has_divec           (cpu_data[0].options & MIPS_CPU_DIVEC)
  89 #endif
  90 #ifndef cpu_has_vce
  91 #define cpu_has_vce             (cpu_data[0].options & MIPS_CPU_VCE)
  92 #endif
  93 #ifndef cpu_has_cache_cdex_p
  94 #define cpu_has_cache_cdex_p    (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
  95 #endif
  96 #ifndef cpu_has_cache_cdex_s
  97 #define cpu_has_cache_cdex_s    (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
  98 #endif
  99 #ifndef cpu_has_prefetch
 100 #define cpu_has_prefetch        (cpu_data[0].options & MIPS_CPU_PREFETCH)
 101 #endif
 102 #ifndef cpu_has_mcheck
 103 #define cpu_has_mcheck          (cpu_data[0].options & MIPS_CPU_MCHECK)
 104 #endif
 105 #ifndef cpu_has_ejtag
 106 #define cpu_has_ejtag           (cpu_data[0].options & MIPS_CPU_EJTAG)
 107 #endif
 108 #ifndef cpu_has_llsc
 109 #define cpu_has_llsc            (cpu_data[0].options & MIPS_CPU_LLSC)
 110 #endif
 111 #ifndef kernel_uses_llsc
 112 #define kernel_uses_llsc        cpu_has_llsc
 113 #endif
 114 #ifndef cpu_has_mips16
 115 #define cpu_has_mips16          (cpu_data[0].ases & MIPS_ASE_MIPS16)
 116 #endif
 117 #ifndef cpu_has_mdmx
 118 #define cpu_has_mdmx            (cpu_data[0].ases & MIPS_ASE_MDMX)
 119 #endif
 120 #ifndef cpu_has_mips3d
 121 #define cpu_has_mips3d          (cpu_data[0].ases & MIPS_ASE_MIPS3D)
 122 #endif
 123 #ifndef cpu_has_smartmips
 124 #define cpu_has_smartmips       (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
 125 #endif
 126
 127 #ifndef cpu_has_rixi
 128 # ifdef CONFIG_64BIT
 129 # define cpu_has_rixi           (cpu_data[0].options & MIPS_CPU_RIXI)
 130 # else /* CONFIG_32BIT */
 131 # define cpu_has_rixi           ((cpu_data[0].options & MIPS_CPU_RIXI) && !cpu_has_64bits)
 132 # endif
 133 #endif
 134
 135 #ifndef cpu_has_mmips
 136 # ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
 137 #  define cpu_has_mmips         (cpu_data[0].options & MIPS_CPU_MICROMIPS)
 138 # else
 139 #  define cpu_has_mmips         0
 140 # endif
 141 #endif
 142
 143 #ifndef cpu_has_xpa
 144 #define cpu_has_xpa             (cpu_data[0].options & MIPS_CPU_XPA)
 145 #endif
 146 #ifndef cpu_has_vtag_icache
 147 #define cpu_has_vtag_icache     (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
 148 #endif
 149 #ifndef cpu_has_dc_aliases
 150 #define cpu_has_dc_aliases      (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
 151 #endif
 152 #ifndef cpu_has_ic_fills_f_dc
 153 #define cpu_has_ic_fills_f_dc   (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
 154 #endif
 155 #ifndef cpu_has_pindexed_dcache
 156 #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
 157 #endif
 158 #ifndef cpu_has_local_ebase
 159 #define cpu_has_local_ebase     1
 160 #endif
 161
 162 /*
 163  * I-Cache snoops remote store.  This only matters on SMP.  Some multiprocessors
 164  * such as the R10000 have I-Caches that snoop local stores; the embedded ones
 165  * don't.  For maintaining I-cache coherency this means we need to flush the
 166  * D-cache all the way back to whever the I-cache does refills from, so the
 167  * I-cache has a chance to see the new data at all.  Then we have to flush the
 168  * I-cache also.
 169  * Note we may have been rescheduled and may no longer be running on the CPU
 170  * that did the store so we can't optimize this into only doing the flush on
 171  * the local CPU.
 172  */
 173 #ifndef cpu_icache_snoops_remote_store
 174 #ifdef CONFIG_SMP
 175 #define cpu_icache_snoops_remote_store  (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
 176 #else
 177 #define cpu_icache_snoops_remote_store  1
 178 #endif
 179 #endif
 180
 181 #ifndef cpu_has_mips_1
 182 # define cpu_has_mips_1         (!cpu_has_mips_r6)
 183 #endif
 184 #ifndef cpu_has_mips_2
 185 # define cpu_has_mips_2         (cpu_data[0].isa_level & MIPS_CPU_ISA_II)
 186 #endif
 187 #ifndef cpu_has_mips_3
 188 # define cpu_has_mips_3         (cpu_data[0].isa_level & MIPS_CPU_ISA_III)
 189 #endif
 190 #ifndef cpu_has_mips_4
 191 # define cpu_has_mips_4         (cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
 192 #endif
 193 #ifndef cpu_has_mips_5
 194 # define cpu_has_mips_5         (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
 195 #endif
 196 #ifndef cpu_has_mips32r1
 197 # define cpu_has_mips32r1       (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
 198 #endif
 199 #ifndef cpu_has_mips32r2
 200 # define cpu_has_mips32r2       (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
 201 #endif
 202 #ifndef cpu_has_mips32r6
 203 # define cpu_has_mips32r6       (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6)
 204 #endif
 205 #ifndef cpu_has_mips64r1
 206 # define cpu_has_mips64r1       (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
 207 #endif
 208 #ifndef cpu_has_mips64r2
 209 # define cpu_has_mips64r2       (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
 210 #endif
 211 #ifndef cpu_has_mips64r6
 212 # define cpu_has_mips64r6       (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R6)
 213 #endif
 214
 215 /*
 216  * Shortcuts ...
 217  */
 218 #define cpu_has_mips_2_3_4_5    (cpu_has_mips_2 | cpu_has_mips_3_4_5)
 219 #define cpu_has_mips_3_4_5      (cpu_has_mips_3 | cpu_has_mips_4_5)
 220 #define cpu_has_mips_4_5        (cpu_has_mips_4 | cpu_has_mips_5)
 221
 222 #define cpu_has_mips_2_3_4_5_r  (cpu_has_mips_2 | cpu_has_mips_3_4_5_r)
 223 #define cpu_has_mips_3_4_5_r    (cpu_has_mips_3 | cpu_has_mips_4_5_r)
 224 #define cpu_has_mips_4_5_r      (cpu_has_mips_4 | cpu_has_mips_5_r)
 225 #define cpu_has_mips_5_r        (cpu_has_mips_5 | cpu_has_mips_r)
 226
 227 #define cpu_has_mips_3_4_5_64_r2_r6                                     \
 228                                 (cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6)
 229 #define cpu_has_mips_4_5_64_r2_r6                                       \
 230                                 (cpu_has_mips_4_5 | cpu_has_mips64r1 |  \
 231                                  cpu_has_mips_r2 | cpu_has_mips_r6)
 232
 233 #define cpu_has_mips32  (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6)
 234 #define cpu_has_mips64  (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6)
 235 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
 236 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
 237 #define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6)
 238 #define cpu_has_mips_r  (cpu_has_mips32r1 | cpu_has_mips32r2 | \
 239                          cpu_has_mips32r6 | cpu_has_mips64r1 | \
 240                          cpu_has_mips64r2 | cpu_has_mips64r6)
 241
 242 /* MIPSR2 and MIPSR6 have a lot of similarities */
 243 #define cpu_has_mips_r2_r6      (cpu_has_mips_r2 | cpu_has_mips_r6)
 244
 245 /*
 246  * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
 247  *
 248  * Returns non-zero value if the current processor implementation requires
 249  * an IHB instruction to deal with an instruction hazard as per MIPS R2
 250  * architecture specification, zero otherwise.
 251  */
 252 #ifndef cpu_has_mips_r2_exec_hazard
 253 #define cpu_has_mips_r2_exec_hazard                                     \
 254 ({                                                                      \
 255         int __res;                                                      \
 256                                                                         \
 257         switch (current_cpu_type()) {                                   \
 258         case CPU_M14KC:                                                 \
 259         case CPU_74K:                                                   \
 260         case CPU_1074K:                                                 \
 261         case CPU_PROAPTIV:                                              \
 262         case CPU_P5600:                                                 \
 263         case CPU_M5150:                                                 \
 264         case CPU_QEMU_GENERIC:                                          \
 265         case CPU_CAVIUM_OCTEON:                                         \
 266         case CPU_CAVIUM_OCTEON_PLUS:                                    \
 267         case CPU_CAVIUM_OCTEON2:                                        \
 268         case CPU_CAVIUM_OCTEON3:                                        \
 269                 __res = 0;                                              \
 270                 break;                                                  \
 271                                                                         \
 272         default:                                                        \
 273                 __res = 1;                                              \
 274         }                                                               \
 275                                                                         \
 276         __res;                                                          \
 277 })
 278 #endif
 279
 280 /*
 281  * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
 282  * pre-MIPS32/MIPS64 processors have CLO, CLZ.  The IDT RC64574 is 64-bit and
 283  * has CLO and CLZ but not DCLO nor DCLZ.  For 64-bit kernels
 284  * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
 285  */
 286 #ifndef cpu_has_clo_clz
 287 #define cpu_has_clo_clz cpu_has_mips_r
 288 #endif
 289
 290 /*
 291  * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH.
 292  * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD.
 293  * This indicates the availability of WSBH and in case of 64 bit CPUs also
 294  * DSBH and DSHD.
 295  */
 296 #ifndef cpu_has_wsbh
 297 #define cpu_has_wsbh            cpu_has_mips_r2
 298 #endif
 299
 300 #ifndef cpu_has_dsp
 301 #define cpu_has_dsp             (cpu_data[0].ases & MIPS_ASE_DSP)
 302 #endif
 303
 304 #ifndef cpu_has_dsp2
 305 #define cpu_has_dsp2            (cpu_data[0].ases & MIPS_ASE_DSP2P)
 306 #endif
 307
 308 #ifndef cpu_has_mipsmt
 309 #define cpu_has_mipsmt          (cpu_data[0].ases & MIPS_ASE_MIPSMT)
 310 #endif
 311
 312 #ifndef cpu_has_userlocal
 313 #define cpu_has_userlocal       (cpu_data[0].options & MIPS_CPU_ULRI)
 314 #endif
 315
 316 #ifdef CONFIG_32BIT
 317 # ifndef cpu_has_nofpuex
 318 # define cpu_has_nofpuex        (cpu_data[0].options & MIPS_CPU_NOFPUEX)
 319 # endif
 320 # ifndef cpu_has_64bits
 321 # define cpu_has_64bits         (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
 322 # endif
 323 # ifndef cpu_has_64bit_zero_reg
 324 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
 325 # endif
 326 # ifndef cpu_has_64bit_gp_regs
 327 # define cpu_has_64bit_gp_regs          0
 328 # endif
 329 # ifndef cpu_has_64bit_addresses
 330 # define cpu_has_64bit_addresses        0
 331 # endif
 332 # ifndef cpu_vmbits
 333 # define cpu_vmbits 31
 334 # endif
 335 #endif
 336
 337 #ifdef CONFIG_64BIT
 338 # ifndef cpu_has_nofpuex
 339 # define cpu_has_nofpuex                0
 340 # endif
 341 # ifndef cpu_has_64bits
 342 # define cpu_has_64bits                 1
 343 # endif
 344 # ifndef cpu_has_64bit_zero_reg
 345 # define cpu_has_64bit_zero_reg         1
 346 # endif
 347 # ifndef cpu_has_64bit_gp_regs
 348 # define cpu_has_64bit_gp_regs          1
 349 # endif
 350 # ifndef cpu_has_64bit_addresses
 351 # define cpu_has_64bit_addresses        1
 352 # endif
 353 # ifndef cpu_vmbits
 354 # define cpu_vmbits cpu_data[0].vmbits
 355 # define __NEED_VMBITS_PROBE
 356 # endif
 357 #endif
 358
 359 #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
 360 # define cpu_has_vint           (cpu_data[0].options & MIPS_CPU_VINT)
 361 #elif !defined(cpu_has_vint)
 362 # define cpu_has_vint                   0
 363 #endif
 364
 365 #if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
 366 # define cpu_has_veic           (cpu_data[0].options & MIPS_CPU_VEIC)
 367 #elif !defined(cpu_has_veic)
 368 # define cpu_has_veic                   0
 369 #endif
 370
 371 #ifndef cpu_has_inclusive_pcaches
 372 #define cpu_has_inclusive_pcaches       (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
 373 #endif
 374
 375 #ifndef cpu_dcache_line_size
 376 #define cpu_dcache_line_size()  cpu_data[0].dcache.linesz
 377 #endif
 378 #ifndef cpu_icache_line_size
 379 #define cpu_icache_line_size()  cpu_data[0].icache.linesz
 380 #endif
 381 #ifndef cpu_scache_line_size
 382 #define cpu_scache_line_size()  cpu_data[0].scache.linesz
 383 #endif
 384
 385 #ifndef cpu_hwrena_impl_bits
 386 #define cpu_hwrena_impl_bits            0
 387 #endif
 388
 389 #ifndef cpu_has_perf_cntr_intr_bit
 390 #define cpu_has_perf_cntr_intr_bit      (cpu_data[0].options & MIPS_CPU_PCI)
 391 #endif
 392
 393 #ifndef cpu_has_vz
 394 #define cpu_has_vz              (cpu_data[0].ases & MIPS_ASE_VZ)
 395 #endif
 396
 397 #if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa)
 398 # define cpu_has_msa            (cpu_data[0].ases & MIPS_ASE_MSA)
 399 #elif !defined(cpu_has_msa)
 400 # define cpu_has_msa            0
 401 #endif
 402
 403 #ifndef cpu_has_fre
 404 # define cpu_has_fre            (cpu_data[0].options & MIPS_CPU_FRE)
 405 #endif
 406
 407 #ifndef cpu_has_cdmm
 408 # define cpu_has_cdmm           (cpu_data[0].options & MIPS_CPU_CDMM)
 409 #endif
 410
 411 #endif /* __ASM_CPU_FEATURES_H */