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2 * Copyright (C) 2002 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
13 #include <linux/sched.h>
14 #include <linux/sched/task_stack.h>
15 #include <linux/thread_info.h>
16 #include <linux/bitops.h>
18 #include <asm/mipsregs.h>
20 #include <asm/cpu-features.h>
21 #include <asm/fpu_emulator.h>
22 #include <asm/hazards.h>
23 #include <asm/processor.h>
24 #include <asm/current.h>
27 #ifdef CONFIG_MIPS_MT_FPAFF
28 #include <asm/mips_mt.h>
34 extern void _init_fpu(unsigned int);
35 extern void _save_fp(struct task_struct
*);
36 extern void _restore_fp(struct task_struct
*);
39 * This enum specifies a mode in which we want the FPU to operate, for cores
40 * which implement the Status.FR bit. Note that the bottom bit of the value
41 * purposefully matches the desired value of the Status.FR bit.
44 FPU_32BIT
= 0, /* FR = 0 */
45 FPU_64BIT
, /* FR = 1, FRE = 0 */
47 FPU_HYBRID
, /* FR = 1, FRE = 1 */
49 #define FPU_FR_MASK 0x1
52 #define __disable_fpu() \
54 clear_c0_status(ST0_CU1); \
55 disable_fpu_hazard(); \
58 static inline int __enable_fpu(enum fpu_mode mode
)
64 /* just enable the FPU in its current mode */
65 set_c0_status(ST0_CU1
);
74 set_c0_config5(MIPS_CONF5_FRE
);
78 #if !(defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) \
79 || defined(CONFIG_64BIT))
80 /* we only have a 32-bit FPU */
87 clear_c0_config5(MIPS_CONF5_FRE
);
90 /* set CU1 & change FR appropriately */
91 fr
= (int)mode
& FPU_FR_MASK
;
92 change_c0_status(ST0_CU1
| ST0_FR
, ST0_CU1
| (fr
? ST0_FR
: 0));
95 /* check FR has the desired value */
96 if (!!(read_c0_status() & ST0_FR
) == !!fr
)
99 /* unsupported FR value */
110 #define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU)
112 static inline int __is_fpu_owner(void)
114 return test_thread_flag(TIF_USEDFPU
);
117 static inline int is_fpu_owner(void)
119 return cpu_has_fpu
&& __is_fpu_owner();
122 static inline int __own_fpu(void)
127 if (test_thread_flag(TIF_HYBRID_FPREGS
))
130 mode
= !test_thread_flag(TIF_32BIT_FPREGS
);
132 ret
= __enable_fpu(mode
);
136 KSTK_STATUS(current
) |= ST0_CU1
;
137 if (mode
== FPU_64BIT
|| mode
== FPU_HYBRID
)
138 KSTK_STATUS(current
) |= ST0_FR
;
139 else /* mode == FPU_32BIT */
140 KSTK_STATUS(current
) &= ~ST0_FR
;
142 set_thread_flag(TIF_USEDFPU
);
146 static inline int own_fpu_inatomic(int restore
)
150 if (cpu_has_fpu
&& !__is_fpu_owner()) {
153 _restore_fp(current
);
158 static inline int own_fpu(int restore
)
163 ret
= own_fpu_inatomic(restore
);
168 static inline void lose_fpu_inatomic(int save
, struct task_struct
*tsk
)
170 if (is_msa_enabled()) {
173 tsk
->thread
.fpu
.fcr31
=
174 read_32bit_cp1_register(CP1_STATUS
);
177 clear_tsk_thread_flag(tsk
, TIF_USEDMSA
);
179 } else if (is_fpu_owner()) {
184 /* FPU should not have been left enabled with no owner */
185 WARN(read_c0_status() & ST0_CU1
,
186 "Orphaned FPU left enabled");
188 KSTK_STATUS(tsk
) &= ~ST0_CU1
;
189 clear_tsk_thread_flag(tsk
, TIF_USEDFPU
);
192 static inline void lose_fpu(int save
)
195 lose_fpu_inatomic(save
, current
);
199 static inline int init_fpu(void)
201 unsigned int fcr31
= current
->thread
.fpu
.fcr31
;
205 unsigned int config5
;
218 * Ensure FRE is clear whilst running _init_fpu, since
219 * single precision FP instructions are used. If FRE
220 * was set then we'll just end up initialising all 32
223 config5
= clear_c0_config5(MIPS_CONF5_FRE
);
229 write_c0_config5(config5
);
232 fpu_emulator_init_fpu();
237 static inline void save_fp(struct task_struct
*tsk
)
243 static inline void restore_fp(struct task_struct
*tsk
)
249 static inline union fpureg
*get_fpu_regs(struct task_struct
*tsk
)
251 if (tsk
== current
) {
258 return tsk
->thread
.fpu
.fpr
;
261 #endif /* _ASM_FPU_H */