arch/mips/include/asm/fpu.h

   1 /*
   2  * Copyright (C) 2002 MontaVista Software Inc.
   3  * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation;  either version 2 of the  License, or (at your
   8  * option) any later version.
   9  */
  10 #ifndef _ASM_FPU_H
  11 #define _ASM_FPU_H
  12
  13 #include <linux/sched.h>
  14 #include <linux/sched/task_stack.h>
  15 #include <linux/thread_info.h>
  16 #include <linux/bitops.h>
  17
  18 #include <asm/mipsregs.h>
  19 #include <asm/cpu.h>
  20 #include <asm/cpu-features.h>
  21 #include <asm/fpu_emulator.h>
  22 #include <asm/hazards.h>
  23 #include <asm/processor.h>
  24 #include <asm/current.h>
  25 #include <asm/msa.h>
  26
  27 #ifdef CONFIG_MIPS_MT_FPAFF
  28 #include <asm/mips_mt.h>
  29 #endif
  30
  31 struct sigcontext;
  32 struct sigcontext32;
  33
  34 extern void _init_fpu(unsigned int);
  35 extern void _save_fp(struct task_struct *);
  36 extern void _restore_fp(struct task_struct *);
  37
  38 /*
  39  * This enum specifies a mode in which we want the FPU to operate, for cores
  40  * which implement the Status.FR bit. Note that the bottom bit of the value
  41  * purposefully matches the desired value of the Status.FR bit.
  42  */
  43 enum fpu_mode {
  44         FPU_32BIT = 0,          /* FR = 0 */
  45         FPU_64BIT,              /* FR = 1, FRE = 0 */
  46         FPU_AS_IS,
  47         FPU_HYBRID,             /* FR = 1, FRE = 1 */
  48
  49 #define FPU_FR_MASK             0x1
  50 };
  51
  52 #define __disable_fpu()                                                 \
  53 do {                                                                    \
  54         clear_c0_status(ST0_CU1);                                       \
  55         disable_fpu_hazard();                                           \
  56 } while (0)
  57
  58 static inline int __enable_fpu(enum fpu_mode mode)
  59 {
  60         int fr;
  61
  62         switch (mode) {
  63         case FPU_AS_IS:
  64                 /* just enable the FPU in its current mode */
  65                 set_c0_status(ST0_CU1);
  66                 enable_fpu_hazard();
  67                 return 0;
  68
  69         case FPU_HYBRID:
  70                 if (!cpu_has_fre)
  71                         return SIGFPE;
  72
  73                 /* set FRE */
  74                 set_c0_config5(MIPS_CONF5_FRE);
  75                 goto fr_common;
  76
  77         case FPU_64BIT:
  78 #if !(defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) \
  79       || defined(CONFIG_64BIT))
  80                 /* we only have a 32-bit FPU */
  81                 return SIGFPE;
  82 #endif
  83                 /* fall through */
  84         case FPU_32BIT:
  85                 if (cpu_has_fre) {
  86                         /* clear FRE */
  87                         clear_c0_config5(MIPS_CONF5_FRE);
  88                 }
  89 fr_common:
  90                 /* set CU1 & change FR appropriately */
  91                 fr = (int)mode & FPU_FR_MASK;
  92                 change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0));
  93                 enable_fpu_hazard();
  94
  95                 /* check FR has the desired value */
  96                 if (!!(read_c0_status() & ST0_FR) == !!fr)
  97                         return 0;
  98
  99                 /* unsupported FR value */
 100                 __disable_fpu();
 101                 return SIGFPE;
 102
 103         default:
 104                 BUG();
 105         }
 106
 107         return SIGFPE;
 108 }
 109
 110 #define clear_fpu_owner()       clear_thread_flag(TIF_USEDFPU)
 111
 112 static inline int __is_fpu_owner(void)
 113 {
 114         return test_thread_flag(TIF_USEDFPU);
 115 }
 116
 117 static inline int is_fpu_owner(void)
 118 {
 119         return cpu_has_fpu && __is_fpu_owner();
 120 }
 121
 122 static inline int __own_fpu(void)
 123 {
 124         enum fpu_mode mode;
 125         int ret;
 126
 127         if (test_thread_flag(TIF_HYBRID_FPREGS))
 128                 mode = FPU_HYBRID;
 129         else
 130                 mode = !test_thread_flag(TIF_32BIT_FPREGS);
 131
 132         ret = __enable_fpu(mode);
 133         if (ret)
 134                 return ret;
 135
 136         KSTK_STATUS(current) |= ST0_CU1;
 137         if (mode == FPU_64BIT || mode == FPU_HYBRID)
 138                 KSTK_STATUS(current) |= ST0_FR;
 139         else /* mode == FPU_32BIT */
 140                 KSTK_STATUS(current) &= ~ST0_FR;
 141
 142         set_thread_flag(TIF_USEDFPU);
 143         return 0;
 144 }
 145
 146 static inline int own_fpu_inatomic(int restore)
 147 {
 148         int ret = 0;
 149
 150         if (cpu_has_fpu && !__is_fpu_owner()) {
 151                 ret = __own_fpu();
 152                 if (restore && !ret)
 153                         _restore_fp(current);
 154         }
 155         return ret;
 156 }
 157
 158 static inline int own_fpu(int restore)
 159 {
 160         int ret;
 161
 162         preempt_disable();
 163         ret = own_fpu_inatomic(restore);
 164         preempt_enable();
 165         return ret;
 166 }
 167
 168 static inline void lose_fpu_inatomic(int save, struct task_struct *tsk)
 169 {
 170         if (is_msa_enabled()) {
 171                 if (save) {
 172                         save_msa(tsk);
 173                         tsk->thread.fpu.fcr31 =
 174                                         read_32bit_cp1_register(CP1_STATUS);
 175                 }
 176                 disable_msa();
 177                 clear_tsk_thread_flag(tsk, TIF_USEDMSA);
 178                 __disable_fpu();
 179         } else if (is_fpu_owner()) {
 180                 if (save)
 181                         _save_fp(tsk);
 182                 __disable_fpu();
 183         } else {
 184                 /* FPU should not have been left enabled with no owner */
 185                 WARN(read_c0_status() & ST0_CU1,
 186                      "Orphaned FPU left enabled");
 187         }
 188         KSTK_STATUS(tsk) &= ~ST0_CU1;
 189         clear_tsk_thread_flag(tsk, TIF_USEDFPU);
 190 }
 191
 192 static inline void lose_fpu(int save)
 193 {
 194         preempt_disable();
 195         lose_fpu_inatomic(save, current);
 196         preempt_enable();
 197 }
 198
 199 static inline int init_fpu(void)
 200 {
 201         unsigned int fcr31 = current->thread.fpu.fcr31;
 202         int ret = 0;
 203
 204         if (cpu_has_fpu) {
 205                 unsigned int config5;
 206
 207                 ret = __own_fpu();
 208                 if (ret)
 209                         return ret;
 210
 211                 if (!cpu_has_fre) {
 212                         _init_fpu(fcr31);
 213
 214                         return 0;
 215                 }
 216
 217                 /*
 218                  * Ensure FRE is clear whilst running _init_fpu, since
 219                  * single precision FP instructions are used. If FRE
 220                  * was set then we'll just end up initialising all 32
 221                  * 64b registers.
 222                  */
 223                 config5 = clear_c0_config5(MIPS_CONF5_FRE);
 224                 enable_fpu_hazard();
 225
 226                 _init_fpu(fcr31);
 227
 228                 /* Restore FRE */
 229                 write_c0_config5(config5);
 230                 enable_fpu_hazard();
 231         } else
 232                 fpu_emulator_init_fpu();
 233
 234         return ret;
 235 }
 236
 237 static inline void save_fp(struct task_struct *tsk)
 238 {
 239         if (cpu_has_fpu)
 240                 _save_fp(tsk);
 241 }
 242
 243 static inline void restore_fp(struct task_struct *tsk)
 244 {
 245         if (cpu_has_fpu)
 246                 _restore_fp(tsk);
 247 }
 248
 249 static inline union fpureg *get_fpu_regs(struct task_struct *tsk)
 250 {
 251         if (tsk == current) {
 252                 preempt_disable();
 253                 if (is_fpu_owner())
 254                         _save_fp(current);
 255                 preempt_enable();
 256         }
 257
 258         return tsk->thread.fpu.fpr;
 259 }
 260
 261 #endif /* _ASM_FPU_H */