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2 * Copyright (C) 2002 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
13 #include <linux/sched.h>
14 #include <linux/thread_info.h>
15 #include <linux/bitops.h>
17 #include <asm/mipsregs.h>
19 #include <asm/cpu-features.h>
20 #include <asm/fpu_emulator.h>
21 #include <asm/hazards.h>
22 #include <asm/processor.h>
23 #include <asm/current.h>
26 #ifdef CONFIG_MIPS_MT_FPAFF
27 #include <asm/mips_mt.h>
33 extern void _init_fpu(void);
34 extern void _save_fp(struct task_struct
*);
35 extern void _restore_fp(struct task_struct
*);
38 * This enum specifies a mode in which we want the FPU to operate, for cores
39 * which implement the Status.FR bit. Note that the bottom bit of the value
40 * purposefully matches the desired value of the Status.FR bit.
43 FPU_32BIT
= 0, /* FR = 0 */
44 FPU_64BIT
, /* FR = 1, FRE = 0 */
46 FPU_HYBRID
, /* FR = 1, FRE = 1 */
48 #define FPU_FR_MASK 0x1
51 static inline int __enable_fpu(enum fpu_mode mode
)
57 /* just enable the FPU in its current mode */
58 set_c0_status(ST0_CU1
);
67 set_c0_config5(MIPS_CONF5_FRE
);
71 #if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_64BIT))
72 /* we only have a 32-bit FPU */
79 clear_c0_config5(MIPS_CONF5_FRE
);
82 /* set CU1 & change FR appropriately */
83 fr
= (int)mode
& FPU_FR_MASK
;
84 change_c0_status(ST0_CU1
| ST0_FR
, ST0_CU1
| (fr
? ST0_FR
: 0));
87 /* check FR has the desired value */
88 return (!!(read_c0_status() & ST0_FR
) == !!fr
) ? 0 : SIGFPE
;
97 #define __disable_fpu() \
99 clear_c0_status(ST0_CU1); \
100 disable_fpu_hazard(); \
103 #define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU)
105 static inline int __is_fpu_owner(void)
107 return test_thread_flag(TIF_USEDFPU
);
110 static inline int is_fpu_owner(void)
112 return cpu_has_fpu
&& __is_fpu_owner();
115 static inline int __own_fpu(void)
120 if (test_thread_flag(TIF_HYBRID_FPREGS
))
123 mode
= !test_thread_flag(TIF_32BIT_FPREGS
);
125 ret
= __enable_fpu(mode
);
129 KSTK_STATUS(current
) |= ST0_CU1
;
130 if (mode
== FPU_64BIT
|| mode
== FPU_HYBRID
)
131 KSTK_STATUS(current
) |= ST0_FR
;
132 else /* mode == FPU_32BIT */
133 KSTK_STATUS(current
) &= ~ST0_FR
;
135 set_thread_flag(TIF_USEDFPU
);
139 static inline int own_fpu_inatomic(int restore
)
143 if (cpu_has_fpu
&& !__is_fpu_owner()) {
146 _restore_fp(current
);
151 static inline int own_fpu(int restore
)
156 ret
= own_fpu_inatomic(restore
);
161 static inline void lose_fpu(int save
)
164 if (is_msa_enabled()) {
167 current
->thread
.fpu
.fcr31
=
168 read_32bit_cp1_register(CP1_STATUS
);
171 clear_thread_flag(TIF_USEDMSA
);
172 } else if (is_fpu_owner()) {
177 KSTK_STATUS(current
) &= ~ST0_CU1
;
178 clear_thread_flag(TIF_USEDFPU
);
182 static inline int init_fpu(void)
187 unsigned int config5
;
200 * Ensure FRE is clear whilst running _init_fpu, since
201 * single precision FP instructions are used. If FRE
202 * was set then we'll just end up initialising all 32
205 config5
= clear_c0_config5(MIPS_CONF5_FRE
);
211 write_c0_config5(config5
);
214 fpu_emulator_init_fpu();
219 static inline void save_fp(struct task_struct
*tsk
)
225 static inline void restore_fp(struct task_struct
*tsk
)
231 static inline union fpureg
*get_fpu_regs(struct task_struct
*tsk
)
233 if (tsk
== current
) {
240 return tsk
->thread
.fpu
.fpr
;
243 #endif /* _ASM_FPU_H */