arch/mips/include/asm/mach-powertv/asic_regs.h

   1 /*
   2  * Copyright (C) 2009  Cisco Systems, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  17  */
  18
  19 #ifndef __ASM_MACH_POWERTV_ASIC_H_
  20 #define __ASM_MACH_POWERTV_ASIC_H_
  21 #include <linux/io.h>
  22
  23 /* ASIC types */
  24 enum asic_type {
  25         ASIC_UNKNOWN,
  26         ASIC_ZEUS,
  27         ASIC_CALLIOPE,
  28         ASIC_CRONUS,
  29         ASIC_CRONUSLITE,
  30         ASICS
  31 };
  32
  33 /* hardcoded values read from Chip Version registers */
  34 #define CRONUS_10       0x0B4C1C20
  35 #define CRONUS_11       0x0B4C1C21
  36 #define CRONUSLITE_10   0x0B4C1C40
  37
  38 #define NAND_FLASH_BASE 0x03000000
  39 #define ZEUS_IO_BASE    0x09000000
  40 #define CALLIOPE_IO_BASE        0x08000000
  41 #define CRONUS_IO_BASE  0x09000000
  42 #define ASIC_IO_SIZE    0x01000000
  43
  44 /* Definitions for backward compatibility */
  45 #define UART1_INTSTAT   uart1_intstat
  46 #define UART1_INTEN     uart1_inten
  47 #define UART1_CONFIG1   uart1_config1
  48 #define UART1_CONFIG2   uart1_config2
  49 #define UART1_DIVISORHI uart1_divisorhi
  50 #define UART1_DIVISORLO uart1_divisorlo
  51 #define UART1_DATA      uart1_data
  52 #define UART1_STATUS    uart1_status
  53
  54 /* ASIC register enumeration */
  55 struct register_map {
  56         u32 eic_slow0_strt_add;
  57         u32 eic_cfg_bits;
  58         u32 eic_ready_status;
  59
  60         u32 chipver3;
  61         u32 chipver2;
  62         u32 chipver1;
  63         u32 chipver0;
  64
  65         u32 uart1_intstat;
  66         u32 uart1_inten;
  67         u32 uart1_config1;
  68         u32 uart1_config2;
  69         u32 uart1_divisorhi;
  70         u32 uart1_divisorlo;
  71         u32 uart1_data;
  72         u32 uart1_status;
  73
  74         u32 int_stat_3;
  75         u32 int_stat_2;
  76         u32 int_stat_1;
  77         u32 int_stat_0;
  78         u32 int_config;
  79         u32 int_int_scan;
  80         u32 ien_int_3;
  81         u32 ien_int_2;
  82         u32 ien_int_1;
  83         u32 ien_int_0;
  84         u32 int_level_3_3;
  85         u32 int_level_3_2;
  86         u32 int_level_3_1;
  87         u32 int_level_3_0;
  88         u32 int_level_2_3;
  89         u32 int_level_2_2;
  90         u32 int_level_2_1;
  91         u32 int_level_2_0;
  92         u32 int_level_1_3;
  93         u32 int_level_1_2;
  94         u32 int_level_1_1;
  95         u32 int_level_1_0;
  96         u32 int_level_0_3;
  97         u32 int_level_0_2;
  98         u32 int_level_0_1;
  99         u32 int_level_0_0;
 100         u32 int_docsis_en;
 101
 102         u32 mips_pll_setup;
 103         u32 usb_fs;
 104         u32 test_bus;
 105         u32 crt_spare;
 106         u32 usb2_ohci_int_mask;
 107         u32 usb2_strap;
 108         u32 ehci_hcapbase;
 109         u32 ohci_hc_revision;
 110         u32 bcm1_bs_lmi_steer;
 111         u32 usb2_control;
 112         u32 usb2_stbus_obc;
 113         u32 usb2_stbus_mess_size;
 114         u32 usb2_stbus_chunk_size;
 115
 116         u32 pcie_regs;
 117         u32 tim_ch;
 118         u32 tim_cl;
 119         u32 gpio_dout;
 120         u32 gpio_din;
 121         u32 gpio_dir;
 122         u32 watchdog;
 123         u32 front_panel;
 124
 125         u32 register_maps;
 126 };
 127
 128 extern enum asic_type asic;
 129 extern const struct register_map *register_map;
 130 extern unsigned long asic_phy_base;     /* Physical address of ASIC */
 131 extern unsigned long asic_base;         /* Virtual address of ASIC */
 132
 133 /*
 134  * Macros to interface to registers through their ioremapped address
 135  * asic_reg_offset      Returns the offset of a given register from the start
 136  *                      of the ASIC address space
 137  * asic_reg_phys_addr   Returns the physical address of the given register
 138  * asic_reg_addr        Returns the iomapped virtual address of the given
 139  *                      register.
 140  */
 141 #define asic_reg_offset(x)      (register_map->x)
 142 #define asic_reg_phys_addr(x)   (asic_phy_base + asic_reg_offset(x))
 143 #define asic_reg_addr(x) \
 144         ((unsigned int *) (asic_base + asic_reg_offset(x)))
 145
 146 /*
 147  * The asic_reg macro is gone. It should be replaced by either asic_read or
 148  * asic_write, as appropriate.
 149  */
 150
 151 #define asic_read(x)            readl(asic_reg_addr(x))
 152 #define asic_write(v, x)        writel(v, asic_reg_addr(x))
 153
 154 extern void asic_irq_init(void);
 155 #endif