arch/mips/include/asm/mach-ralink/ralink_regs.h

   1 /*
   2  *  Ralink SoC register definitions
   3  *
   4  *  Copyright (C) 2013 John Crispin <john@phrozen.org>
   5  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
   6  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms of the GNU General Public License version 2 as published
  10  *  by the Free Software Foundation.
  11  */
  12
  13 #ifndef _RALINK_REGS_H_
  14 #define _RALINK_REGS_H_
  15
  16 #include <linux/io.h>
  17
  18 enum ralink_soc_type {
  19         RALINK_UNKNOWN = 0,
  20         RT2880_SOC,
  21         RT3883_SOC,
  22         RT305X_SOC_RT3050,
  23         RT305X_SOC_RT3052,
  24         RT305X_SOC_RT3350,
  25         RT305X_SOC_RT3352,
  26         RT305X_SOC_RT5350,
  27         MT762X_SOC_MT7620A,
  28         MT762X_SOC_MT7620N,
  29         MT762X_SOC_MT7621AT,
  30         MT762X_SOC_MT7628AN,
  31         MT762X_SOC_MT7688,
  32 };
  33 extern enum ralink_soc_type ralink_soc;
  34
  35 extern __iomem void *rt_sysc_membase;
  36 extern __iomem void *rt_memc_membase;
  37
  38 static inline void rt_sysc_w32(u32 val, unsigned reg)
  39 {
  40         __raw_writel(val, rt_sysc_membase + reg);
  41 }
  42
  43 static inline u32 rt_sysc_r32(unsigned reg)
  44 {
  45         return __raw_readl(rt_sysc_membase + reg);
  46 }
  47
  48 static inline void rt_sysc_m32(u32 clr, u32 set, unsigned reg)
  49 {
  50         u32 val = rt_sysc_r32(reg) & ~clr;
  51
  52         __raw_writel(val | set, rt_sysc_membase + reg);
  53 }
  54
  55 static inline void rt_memc_w32(u32 val, unsigned reg)
  56 {
  57         __raw_writel(val, rt_memc_membase + reg);
  58 }
  59
  60 static inline u32 rt_memc_r32(unsigned reg)
  61 {
  62         return __raw_readl(rt_memc_membase + reg);
  63 }
  64
  65 #endif /* _RALINK_REGS_H_ */