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git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - arch/mips/include/asm/mipsregs.h
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
13 #ifndef _ASM_MIPSREGS_H
14 #define _ASM_MIPSREGS_H
16 #include <linux/linkage.h>
17 #include <linux/types.h>
18 #include <asm/hazards.h>
22 * The following macros are especially useful for __asm__
29 #define STR(x) __STR(x)
39 #define _ULCAST_ (unsigned long)
40 #define _U64CAST_ (u64)
44 * Coprocessor 0 register names
48 #define CP0_ENTRYLO0 $2
49 #define CP0_ENTRYLO1 $3
51 #define CP0_CONTEXT $4
52 #define CP0_PAGEMASK $5
53 #define CP0_SEGCTL0 $5, 2
54 #define CP0_SEGCTL1 $5, 3
55 #define CP0_SEGCTL2 $5, 4
59 #define CP0_BADVADDR $8
60 #define CP0_BADINSTR $8, 1
62 #define CP0_ENTRYHI $10
63 #define CP0_GUESTCTL1 $10, 4
64 #define CP0_GUESTCTL2 $10, 5
65 #define CP0_GUESTCTL3 $10, 6
66 #define CP0_COMPARE $11
67 #define CP0_GUESTCTL0EXT $11, 4
68 #define CP0_STATUS $12
69 #define CP0_GUESTCTL0 $12, 6
70 #define CP0_GTOFFSET $12, 7
74 #define CP0_EBASE $15, 1
75 #define CP0_CMGCRBASE $15, 3
76 #define CP0_CONFIG $16
77 #define CP0_CONFIG3 $16, 3
78 #define CP0_CONFIG5 $16, 5
79 #define CP0_LLADDR $17
80 #define CP0_WATCHLO $18
81 #define CP0_WATCHHI $19
82 #define CP0_XCONTEXT $20
83 #define CP0_FRAMEMASK $21
84 #define CP0_DIAGNOSTIC $22
87 #define CP0_PERFORMANCE $25
89 #define CP0_CACHEERR $27
92 #define CP0_ERROREPC $30
93 #define CP0_DESAVE $31
96 * R4640/R4650 cp0 register names. These registers are listed
97 * here only for completeness; without MMU these CPUs are not useable
98 * by Linux. A future ELKS port might take make Linux run on them
102 #define CP0_IBOUND $1
104 #define CP0_DBOUND $3
106 #define CP0_IWATCH $18
107 #define CP0_DWATCH $19
110 * Coprocessor 0 Set 1 register names
112 #define CP0_S1_DERRADDR0 $26
113 #define CP0_S1_DERRADDR1 $27
114 #define CP0_S1_INTCONTROL $20
117 * Coprocessor 0 Set 2 register names
119 #define CP0_S2_SRSCTL $12 /* MIPSR2 */
122 * Coprocessor 0 Set 3 register names
124 #define CP0_S3_SRSMAP $12 /* MIPSR2 */
129 #define CP0_TX39_CACHE $7
132 /* Generic EntryLo bit definitions */
133 #define ENTRYLO_G (_ULCAST_(1) << 0)
134 #define ENTRYLO_V (_ULCAST_(1) << 1)
135 #define ENTRYLO_D (_ULCAST_(1) << 2)
136 #define ENTRYLO_C_SHIFT 3
137 #define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
139 /* R3000 EntryLo bit definitions */
140 #define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
141 #define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
142 #define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
143 #define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
145 /* MIPS32/64 EntryLo bit definitions */
146 #define MIPS_ENTRYLO_PFN_SHIFT 6
147 #define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
148 #define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
151 * Values for PageMask register
153 #ifdef CONFIG_CPU_VR41XX
155 /* Why doesn't stupidity hurt ... */
157 #define PM_1K 0x00000000
158 #define PM_4K 0x00001800
159 #define PM_16K 0x00007800
160 #define PM_64K 0x0001f800
161 #define PM_256K 0x0007f800
165 #define PM_4K 0x00000000
166 #define PM_8K 0x00002000
167 #define PM_16K 0x00006000
168 #define PM_32K 0x0000e000
169 #define PM_64K 0x0001e000
170 #define PM_128K 0x0003e000
171 #define PM_256K 0x0007e000
172 #define PM_512K 0x000fe000
173 #define PM_1M 0x001fe000
174 #define PM_2M 0x003fe000
175 #define PM_4M 0x007fe000
176 #define PM_8M 0x00ffe000
177 #define PM_16M 0x01ffe000
178 #define PM_32M 0x03ffe000
179 #define PM_64M 0x07ffe000
180 #define PM_256M 0x1fffe000
181 #define PM_1G 0x7fffe000
186 * Default page size for a given kernel configuration
188 #ifdef CONFIG_PAGE_SIZE_4KB
189 #define PM_DEFAULT_MASK PM_4K
190 #elif defined(CONFIG_PAGE_SIZE_8KB)
191 #define PM_DEFAULT_MASK PM_8K
192 #elif defined(CONFIG_PAGE_SIZE_16KB)
193 #define PM_DEFAULT_MASK PM_16K
194 #elif defined(CONFIG_PAGE_SIZE_32KB)
195 #define PM_DEFAULT_MASK PM_32K
196 #elif defined(CONFIG_PAGE_SIZE_64KB)
197 #define PM_DEFAULT_MASK PM_64K
199 #error Bad page size configuration!
203 * Default huge tlb size for a given kernel configuration
205 #ifdef CONFIG_PAGE_SIZE_4KB
206 #define PM_HUGE_MASK PM_1M
207 #elif defined(CONFIG_PAGE_SIZE_8KB)
208 #define PM_HUGE_MASK PM_4M
209 #elif defined(CONFIG_PAGE_SIZE_16KB)
210 #define PM_HUGE_MASK PM_16M
211 #elif defined(CONFIG_PAGE_SIZE_32KB)
212 #define PM_HUGE_MASK PM_64M
213 #elif defined(CONFIG_PAGE_SIZE_64KB)
214 #define PM_HUGE_MASK PM_256M
215 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
216 #error Bad page size configuration for hugetlbfs!
220 * Wired register bits
222 #define MIPSR6_WIRED_LIMIT_SHIFT 16
223 #define MIPSR6_WIRED_LIMIT (_ULCAST_(0xffff) << MIPSR6_WIRED_LIMIT_SHIFT)
224 #define MIPSR6_WIRED_WIRED_SHIFT 0
225 #define MIPSR6_WIRED_WIRED (_ULCAST_(0xffff) << MIPSR6_WIRED_WIRED_SHIFT)
228 * Values used for computation of new tlb entries
243 #define PG_RIE (_ULCAST_(1) << 31)
244 #define PG_XIE (_ULCAST_(1) << 30)
245 #define PG_ELPA (_ULCAST_(1) << 29)
246 #define PG_ESP (_ULCAST_(1) << 28)
247 #define PG_IEC (_ULCAST_(1) << 27)
249 /* MIPS32/64 EntryHI bit definitions */
250 #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
251 #define MIPS_ENTRYHI_ASIDX (_ULCAST_(0x3) << 8)
252 #define MIPS_ENTRYHI_ASID (_ULCAST_(0xff) << 0)
255 * R4x00 interrupt enable / cause bits
257 #define IE_SW0 (_ULCAST_(1) << 8)
258 #define IE_SW1 (_ULCAST_(1) << 9)
259 #define IE_IRQ0 (_ULCAST_(1) << 10)
260 #define IE_IRQ1 (_ULCAST_(1) << 11)
261 #define IE_IRQ2 (_ULCAST_(1) << 12)
262 #define IE_IRQ3 (_ULCAST_(1) << 13)
263 #define IE_IRQ4 (_ULCAST_(1) << 14)
264 #define IE_IRQ5 (_ULCAST_(1) << 15)
267 * R4x00 interrupt cause bits
269 #define C_SW0 (_ULCAST_(1) << 8)
270 #define C_SW1 (_ULCAST_(1) << 9)
271 #define C_IRQ0 (_ULCAST_(1) << 10)
272 #define C_IRQ1 (_ULCAST_(1) << 11)
273 #define C_IRQ2 (_ULCAST_(1) << 12)
274 #define C_IRQ3 (_ULCAST_(1) << 13)
275 #define C_IRQ4 (_ULCAST_(1) << 14)
276 #define C_IRQ5 (_ULCAST_(1) << 15)
279 * Bitfields in the R4xx0 cp0 status register
281 #define ST0_IE 0x00000001
282 #define ST0_EXL 0x00000002
283 #define ST0_ERL 0x00000004
284 #define ST0_KSU 0x00000018
285 # define KSU_USER 0x00000010
286 # define KSU_SUPERVISOR 0x00000008
287 # define KSU_KERNEL 0x00000000
288 #define ST0_UX 0x00000020
289 #define ST0_SX 0x00000040
290 #define ST0_KX 0x00000080
291 #define ST0_DE 0x00010000
292 #define ST0_CE 0x00020000
295 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
296 * cacheops in userspace. This bit exists only on RM7000 and RM9000
299 #define ST0_CO 0x08000000
302 * Bitfields in the R[23]000 cp0 status register.
304 #define ST0_IEC 0x00000001
305 #define ST0_KUC 0x00000002
306 #define ST0_IEP 0x00000004
307 #define ST0_KUP 0x00000008
308 #define ST0_IEO 0x00000010
309 #define ST0_KUO 0x00000020
310 /* bits 6 & 7 are reserved on R[23]000 */
311 #define ST0_ISC 0x00010000
312 #define ST0_SWC 0x00020000
313 #define ST0_CM 0x00080000
316 * Bits specific to the R4640/R4650
318 #define ST0_UM (_ULCAST_(1) << 4)
319 #define ST0_IL (_ULCAST_(1) << 23)
320 #define ST0_DL (_ULCAST_(1) << 24)
323 * Enable the MIPS MDMX and DSP ASEs
325 #define ST0_MX 0x01000000
328 * Status register bits available in all MIPS CPUs.
330 #define ST0_IM 0x0000ff00
331 #define STATUSB_IP0 8
332 #define STATUSF_IP0 (_ULCAST_(1) << 8)
333 #define STATUSB_IP1 9
334 #define STATUSF_IP1 (_ULCAST_(1) << 9)
335 #define STATUSB_IP2 10
336 #define STATUSF_IP2 (_ULCAST_(1) << 10)
337 #define STATUSB_IP3 11
338 #define STATUSF_IP3 (_ULCAST_(1) << 11)
339 #define STATUSB_IP4 12
340 #define STATUSF_IP4 (_ULCAST_(1) << 12)
341 #define STATUSB_IP5 13
342 #define STATUSF_IP5 (_ULCAST_(1) << 13)
343 #define STATUSB_IP6 14
344 #define STATUSF_IP6 (_ULCAST_(1) << 14)
345 #define STATUSB_IP7 15
346 #define STATUSF_IP7 (_ULCAST_(1) << 15)
347 #define STATUSB_IP8 0
348 #define STATUSF_IP8 (_ULCAST_(1) << 0)
349 #define STATUSB_IP9 1
350 #define STATUSF_IP9 (_ULCAST_(1) << 1)
351 #define STATUSB_IP10 2
352 #define STATUSF_IP10 (_ULCAST_(1) << 2)
353 #define STATUSB_IP11 3
354 #define STATUSF_IP11 (_ULCAST_(1) << 3)
355 #define STATUSB_IP12 4
356 #define STATUSF_IP12 (_ULCAST_(1) << 4)
357 #define STATUSB_IP13 5
358 #define STATUSF_IP13 (_ULCAST_(1) << 5)
359 #define STATUSB_IP14 6
360 #define STATUSF_IP14 (_ULCAST_(1) << 6)
361 #define STATUSB_IP15 7
362 #define STATUSF_IP15 (_ULCAST_(1) << 7)
363 #define ST0_CH 0x00040000
364 #define ST0_NMI 0x00080000
365 #define ST0_SR 0x00100000
366 #define ST0_TS 0x00200000
367 #define ST0_BEV 0x00400000
368 #define ST0_RE 0x02000000
369 #define ST0_FR 0x04000000
370 #define ST0_CU 0xf0000000
371 #define ST0_CU0 0x10000000
372 #define ST0_CU1 0x20000000
373 #define ST0_CU2 0x40000000
374 #define ST0_CU3 0x80000000
375 #define ST0_XX 0x80000000 /* MIPS IV naming */
378 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
380 #define INTCTLB_IPFDC 23
381 #define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
382 #define INTCTLB_IPPCI 26
383 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
384 #define INTCTLB_IPTI 29
385 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
388 * Bitfields and bit numbers in the coprocessor 0 cause register.
390 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
392 #define CAUSEB_EXCCODE 2
393 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
395 #define CAUSEF_IP (_ULCAST_(255) << 8)
397 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
399 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
400 #define CAUSEB_IP2 10
401 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
402 #define CAUSEB_IP3 11
403 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
404 #define CAUSEB_IP4 12
405 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
406 #define CAUSEB_IP5 13
407 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
408 #define CAUSEB_IP6 14
409 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
410 #define CAUSEB_IP7 15
411 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
412 #define CAUSEB_FDCI 21
413 #define CAUSEF_FDCI (_ULCAST_(1) << 21)
415 #define CAUSEF_WP (_ULCAST_(1) << 22)
417 #define CAUSEF_IV (_ULCAST_(1) << 23)
418 #define CAUSEB_PCI 26
419 #define CAUSEF_PCI (_ULCAST_(1) << 26)
421 #define CAUSEF_DC (_ULCAST_(1) << 27)
423 #define CAUSEF_CE (_ULCAST_(3) << 28)
425 #define CAUSEF_TI (_ULCAST_(1) << 30)
427 #define CAUSEF_BD (_ULCAST_(1) << 31)
430 * Cause.ExcCode trap codes.
432 #define EXCCODE_INT 0 /* Interrupt pending */
433 #define EXCCODE_MOD 1 /* TLB modified fault */
434 #define EXCCODE_TLBL 2 /* TLB miss on load or ifetch */
435 #define EXCCODE_TLBS 3 /* TLB miss on a store */
436 #define EXCCODE_ADEL 4 /* Address error on a load or ifetch */
437 #define EXCCODE_ADES 5 /* Address error on a store */
438 #define EXCCODE_IBE 6 /* Bus error on an ifetch */
439 #define EXCCODE_DBE 7 /* Bus error on a load or store */
440 #define EXCCODE_SYS 8 /* System call */
441 #define EXCCODE_BP 9 /* Breakpoint */
442 #define EXCCODE_RI 10 /* Reserved instruction exception */
443 #define EXCCODE_CPU 11 /* Coprocessor unusable */
444 #define EXCCODE_OV 12 /* Arithmetic overflow */
445 #define EXCCODE_TR 13 /* Trap instruction */
446 #define EXCCODE_MSAFPE 14 /* MSA floating point exception */
447 #define EXCCODE_FPE 15 /* Floating point exception */
448 #define EXCCODE_TLBRI 19 /* TLB Read-Inhibit exception */
449 #define EXCCODE_TLBXI 20 /* TLB Execution-Inhibit exception */
450 #define EXCCODE_MSADIS 21 /* MSA disabled exception */
451 #define EXCCODE_MDMX 22 /* MDMX unusable exception */
452 #define EXCCODE_WATCH 23 /* Watch address reference */
453 #define EXCCODE_MCHECK 24 /* Machine check */
454 #define EXCCODE_THREAD 25 /* Thread exceptions (MT) */
455 #define EXCCODE_DSPDIS 26 /* DSP disabled exception */
456 #define EXCCODE_GE 27 /* Virtualized guest exception (VZ) */
458 /* Implementation specific trap codes used by MIPS cores */
459 #define MIPS_EXCCODE_TLBPAR 16 /* TLB parity error exception */
462 * Bits in the coprocessor 0 config register.
465 #define CONF_CM_CACHABLE_NO_WA 0
466 #define CONF_CM_CACHABLE_WA 1
467 #define CONF_CM_UNCACHED 2
468 #define CONF_CM_CACHABLE_NONCOHERENT 3
469 #define CONF_CM_CACHABLE_CE 4
470 #define CONF_CM_CACHABLE_COW 5
471 #define CONF_CM_CACHABLE_CUW 6
472 #define CONF_CM_CACHABLE_ACCELERATED 7
473 #define CONF_CM_CMASK 7
474 #define CONF_BE (_ULCAST_(1) << 15)
476 /* Bits common to various processors. */
477 #define CONF_CU (_ULCAST_(1) << 3)
478 #define CONF_DB (_ULCAST_(1) << 4)
479 #define CONF_IB (_ULCAST_(1) << 5)
480 #define CONF_DC (_ULCAST_(7) << 6)
481 #define CONF_IC (_ULCAST_(7) << 9)
482 #define CONF_EB (_ULCAST_(1) << 13)
483 #define CONF_EM (_ULCAST_(1) << 14)
484 #define CONF_SM (_ULCAST_(1) << 16)
485 #define CONF_SC (_ULCAST_(1) << 17)
486 #define CONF_EW (_ULCAST_(3) << 18)
487 #define CONF_EP (_ULCAST_(15)<< 24)
488 #define CONF_EC (_ULCAST_(7) << 28)
489 #define CONF_CM (_ULCAST_(1) << 31)
491 /* Bits specific to the R4xx0. */
492 #define R4K_CONF_SW (_ULCAST_(1) << 20)
493 #define R4K_CONF_SS (_ULCAST_(1) << 21)
494 #define R4K_CONF_SB (_ULCAST_(3) << 22)
496 /* Bits specific to the R5000. */
497 #define R5K_CONF_SE (_ULCAST_(1) << 12)
498 #define R5K_CONF_SS (_ULCAST_(3) << 20)
500 /* Bits specific to the RM7000. */
501 #define RM7K_CONF_SE (_ULCAST_(1) << 3)
502 #define RM7K_CONF_TE (_ULCAST_(1) << 12)
503 #define RM7K_CONF_CLK (_ULCAST_(1) << 16)
504 #define RM7K_CONF_TC (_ULCAST_(1) << 17)
505 #define RM7K_CONF_SI (_ULCAST_(3) << 20)
506 #define RM7K_CONF_SC (_ULCAST_(1) << 31)
508 /* Bits specific to the R10000. */
509 #define R10K_CONF_DN (_ULCAST_(3) << 3)
510 #define R10K_CONF_CT (_ULCAST_(1) << 5)
511 #define R10K_CONF_PE (_ULCAST_(1) << 6)
512 #define R10K_CONF_PM (_ULCAST_(3) << 7)
513 #define R10K_CONF_EC (_ULCAST_(15)<< 9)
514 #define R10K_CONF_SB (_ULCAST_(1) << 13)
515 #define R10K_CONF_SK (_ULCAST_(1) << 14)
516 #define R10K_CONF_SS (_ULCAST_(7) << 16)
517 #define R10K_CONF_SC (_ULCAST_(7) << 19)
518 #define R10K_CONF_DC (_ULCAST_(7) << 26)
519 #define R10K_CONF_IC (_ULCAST_(7) << 29)
521 /* Bits specific to the VR41xx. */
522 #define VR41_CONF_CS (_ULCAST_(1) << 12)
523 #define VR41_CONF_P4K (_ULCAST_(1) << 13)
524 #define VR41_CONF_BP (_ULCAST_(1) << 16)
525 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
526 #define VR41_CONF_AD (_ULCAST_(1) << 23)
528 /* Bits specific to the R30xx. */
529 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
530 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
531 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
532 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
533 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
534 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
535 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
536 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
537 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
539 /* Bits specific to the TX49. */
540 #define TX49_CONF_DC (_ULCAST_(1) << 16)
541 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
542 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
543 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
545 /* Bits specific to the MIPS32/64 PRA. */
546 #define MIPS_CONF_VI (_ULCAST_(1) << 3)
547 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
548 #define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7)
549 #define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
550 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
551 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
552 #define MIPS_CONF_M (_ULCAST_(1) << 31)
555 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
557 #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
558 #define MIPS_CONF1_EP (_ULCAST_(1) << 1)
559 #define MIPS_CONF1_CA (_ULCAST_(1) << 2)
560 #define MIPS_CONF1_WR (_ULCAST_(1) << 3)
561 #define MIPS_CONF1_PC (_ULCAST_(1) << 4)
562 #define MIPS_CONF1_MD (_ULCAST_(1) << 5)
563 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
564 #define MIPS_CONF1_DA_SHF 7
565 #define MIPS_CONF1_DA_SZ 3
566 #define MIPS_CONF1_DA (_ULCAST_(7) << 7)
567 #define MIPS_CONF1_DL_SHF 10
568 #define MIPS_CONF1_DL_SZ 3
569 #define MIPS_CONF1_DL (_ULCAST_(7) << 10)
570 #define MIPS_CONF1_DS_SHF 13
571 #define MIPS_CONF1_DS_SZ 3
572 #define MIPS_CONF1_DS (_ULCAST_(7) << 13)
573 #define MIPS_CONF1_IA_SHF 16
574 #define MIPS_CONF1_IA_SZ 3
575 #define MIPS_CONF1_IA (_ULCAST_(7) << 16)
576 #define MIPS_CONF1_IL_SHF 19
577 #define MIPS_CONF1_IL_SZ 3
578 #define MIPS_CONF1_IL (_ULCAST_(7) << 19)
579 #define MIPS_CONF1_IS_SHF 22
580 #define MIPS_CONF1_IS_SZ 3
581 #define MIPS_CONF1_IS (_ULCAST_(7) << 22)
582 #define MIPS_CONF1_TLBS_SHIFT (25)
583 #define MIPS_CONF1_TLBS_SIZE (6)
584 #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
586 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
587 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
588 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
589 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
590 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
591 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
592 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
593 #define MIPS_CONF2_TU (_ULCAST_(7) << 28)
595 #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
596 #define MIPS_CONF3_SM (_ULCAST_(1) << 1)
597 #define MIPS_CONF3_MT (_ULCAST_(1) << 2)
598 #define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
599 #define MIPS_CONF3_SP (_ULCAST_(1) << 4)
600 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
601 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
602 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
603 #define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
604 #define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
605 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
606 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
607 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
608 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
609 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
610 #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
611 #define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
612 #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
613 #define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
614 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
615 #define MIPS_CONF3_PW (_ULCAST_(1) << 24)
616 #define MIPS_CONF3_SC (_ULCAST_(1) << 25)
617 #define MIPS_CONF3_BI (_ULCAST_(1) << 26)
618 #define MIPS_CONF3_BP (_ULCAST_(1) << 27)
619 #define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
620 #define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
621 #define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
623 #define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
624 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
625 #define MIPS_CONF4_FTLBSETS_SHIFT (0)
626 #define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
627 #define MIPS_CONF4_FTLBWAYS_SHIFT (4)
628 #define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
629 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
630 /* bits 10:8 in FTLB-only configurations */
631 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
632 /* bits 12:8 in VTLB-FTLB only configurations */
633 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
634 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
635 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
636 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
637 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
638 #define MIPS_CONF4_KSCREXIST_SHIFT (16)
639 #define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
640 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
641 #define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
642 #define MIPS_CONF4_AE (_ULCAST_(1) << 28)
643 #define MIPS_CONF4_IE (_ULCAST_(3) << 29)
644 #define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
646 #define MIPS_CONF5_NF (_ULCAST_(1) << 0)
647 #define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
648 #define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
649 #define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
650 #define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
651 #define MIPS_CONF5_VP (_ULCAST_(1) << 7)
652 #define MIPS_CONF5_SBRI (_ULCAST_(1) << 6)
653 #define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
654 #define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
655 #define MIPS_CONF5_CA2 (_ULCAST_(1) << 14)
656 #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
657 #define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
658 #define MIPS_CONF5_CV (_ULCAST_(1) << 29)
659 #define MIPS_CONF5_K (_ULCAST_(1) << 30)
661 #define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
662 /* proAptiv FTLB on/off bit */
663 #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
664 /* Loongson-3 FTLB on/off bit */
665 #define MIPS_CONF6_FTLBDIS (_ULCAST_(1) << 22)
666 /* FTLB probability bits */
667 #define MIPS_CONF6_FTLBP_SHIFT (16)
669 #define MIPS_CONF7_WII (_ULCAST_(1) << 31)
671 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
673 #define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
674 #define MIPS_CONF7_AR (_ULCAST_(1) << 16)
676 /* WatchLo* register definitions */
677 #define MIPS_WATCHLO_IRW (_ULCAST_(0x7) << 0)
679 /* WatchHi* register definitions */
680 #define MIPS_WATCHHI_M (_ULCAST_(1) << 31)
681 #define MIPS_WATCHHI_G (_ULCAST_(1) << 30)
682 #define MIPS_WATCHHI_WM (_ULCAST_(0x3) << 28)
683 #define MIPS_WATCHHI_WM_R_RVA (_ULCAST_(0) << 28)
684 #define MIPS_WATCHHI_WM_R_GPA (_ULCAST_(1) << 28)
685 #define MIPS_WATCHHI_WM_G_GVA (_ULCAST_(2) << 28)
686 #define MIPS_WATCHHI_EAS (_ULCAST_(0x3) << 24)
687 #define MIPS_WATCHHI_ASID (_ULCAST_(0xff) << 16)
688 #define MIPS_WATCHHI_MASK (_ULCAST_(0x1ff) << 3)
689 #define MIPS_WATCHHI_I (_ULCAST_(1) << 2)
690 #define MIPS_WATCHHI_R (_ULCAST_(1) << 1)
691 #define MIPS_WATCHHI_W (_ULCAST_(1) << 0)
692 #define MIPS_WATCHHI_IRW (_ULCAST_(0x7) << 0)
694 /* PerfCnt control register definitions */
695 #define MIPS_PERFCTRL_EXL (_ULCAST_(1) << 0)
696 #define MIPS_PERFCTRL_K (_ULCAST_(1) << 1)
697 #define MIPS_PERFCTRL_S (_ULCAST_(1) << 2)
698 #define MIPS_PERFCTRL_U (_ULCAST_(1) << 3)
699 #define MIPS_PERFCTRL_IE (_ULCAST_(1) << 4)
700 #define MIPS_PERFCTRL_EVENT_S 5
701 #define MIPS_PERFCTRL_EVENT (_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
702 #define MIPS_PERFCTRL_PCTD (_ULCAST_(1) << 15)
703 #define MIPS_PERFCTRL_EC (_ULCAST_(0x3) << 23)
704 #define MIPS_PERFCTRL_EC_R (_ULCAST_(0) << 23)
705 #define MIPS_PERFCTRL_EC_RI (_ULCAST_(1) << 23)
706 #define MIPS_PERFCTRL_EC_G (_ULCAST_(2) << 23)
707 #define MIPS_PERFCTRL_EC_GRI (_ULCAST_(3) << 23)
708 #define MIPS_PERFCTRL_W (_ULCAST_(1) << 30)
709 #define MIPS_PERFCTRL_M (_ULCAST_(1) << 31)
711 /* PerfCnt control register MT extensions used by MIPS cores */
712 #define MIPS_PERFCTRL_VPEID_S 16
713 #define MIPS_PERFCTRL_VPEID (_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
714 #define MIPS_PERFCTRL_TCID_S 22
715 #define MIPS_PERFCTRL_TCID (_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
716 #define MIPS_PERFCTRL_MT_EN (_ULCAST_(0x3) << 20)
717 #define MIPS_PERFCTRL_MT_EN_ALL (_ULCAST_(0) << 20)
718 #define MIPS_PERFCTRL_MT_EN_VPE (_ULCAST_(1) << 20)
719 #define MIPS_PERFCTRL_MT_EN_TC (_ULCAST_(2) << 20)
721 /* PerfCnt control register MT extensions used by BMIPS5000 */
722 #define BRCM_PERFCTRL_TC (_ULCAST_(1) << 30)
724 /* PerfCnt control register MT extensions used by Netlogic XLR */
725 #define XLR_PERFCTRL_ALLTHREADS (_ULCAST_(1) << 13)
727 /* MAAR bit definitions */
728 #define MIPS_MAAR_VH (_U64CAST_(1) << 63)
729 #define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
730 #define MIPS_MAAR_ADDR_SHIFT 12
731 #define MIPS_MAAR_S (_ULCAST_(1) << 1)
732 #define MIPS_MAAR_VL (_ULCAST_(1) << 0)
734 /* MAARI bit definitions */
735 #define MIPS_MAARI_INDEX (_ULCAST_(0x3f) << 0)
737 /* EBase bit definitions */
738 #define MIPS_EBASE_CPUNUM_SHIFT 0
739 #define MIPS_EBASE_CPUNUM (_ULCAST_(0x3ff) << 0)
740 #define MIPS_EBASE_WG_SHIFT 11
741 #define MIPS_EBASE_WG (_ULCAST_(1) << 11)
742 #define MIPS_EBASE_BASE_SHIFT 12
743 #define MIPS_EBASE_BASE (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
745 /* CMGCRBase bit definitions */
746 #define MIPS_CMGCRB_BASE 11
747 #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
749 /* LLAddr bit definitions */
750 #define MIPS_LLADDR_LLB_SHIFT 0
751 #define MIPS_LLADDR_LLB (_ULCAST_(1) << MIPS_LLADDR_LLB_SHIFT)
754 * Bits in the MIPS32 Memory Segmentation registers.
756 #define MIPS_SEGCFG_PA_SHIFT 9
757 #define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
758 #define MIPS_SEGCFG_AM_SHIFT 4
759 #define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
760 #define MIPS_SEGCFG_EU_SHIFT 3
761 #define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
762 #define MIPS_SEGCFG_C_SHIFT 0
763 #define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
765 #define MIPS_SEGCFG_UUSK _ULCAST_(7)
766 #define MIPS_SEGCFG_USK _ULCAST_(5)
767 #define MIPS_SEGCFG_MUSUK _ULCAST_(4)
768 #define MIPS_SEGCFG_MUSK _ULCAST_(3)
769 #define MIPS_SEGCFG_MSK _ULCAST_(2)
770 #define MIPS_SEGCFG_MK _ULCAST_(1)
771 #define MIPS_SEGCFG_UK _ULCAST_(0)
773 #define MIPS_PWFIELD_GDI_SHIFT 24
774 #define MIPS_PWFIELD_GDI_MASK 0x3f000000
775 #define MIPS_PWFIELD_UDI_SHIFT 18
776 #define MIPS_PWFIELD_UDI_MASK 0x00fc0000
777 #define MIPS_PWFIELD_MDI_SHIFT 12
778 #define MIPS_PWFIELD_MDI_MASK 0x0003f000
779 #define MIPS_PWFIELD_PTI_SHIFT 6
780 #define MIPS_PWFIELD_PTI_MASK 0x00000fc0
781 #define MIPS_PWFIELD_PTEI_SHIFT 0
782 #define MIPS_PWFIELD_PTEI_MASK 0x0000003f
784 #define MIPS_PWSIZE_PS_SHIFT 30
785 #define MIPS_PWSIZE_PS_MASK 0x40000000
786 #define MIPS_PWSIZE_GDW_SHIFT 24
787 #define MIPS_PWSIZE_GDW_MASK 0x3f000000
788 #define MIPS_PWSIZE_UDW_SHIFT 18
789 #define MIPS_PWSIZE_UDW_MASK 0x00fc0000
790 #define MIPS_PWSIZE_MDW_SHIFT 12
791 #define MIPS_PWSIZE_MDW_MASK 0x0003f000
792 #define MIPS_PWSIZE_PTW_SHIFT 6
793 #define MIPS_PWSIZE_PTW_MASK 0x00000fc0
794 #define MIPS_PWSIZE_PTEW_SHIFT 0
795 #define MIPS_PWSIZE_PTEW_MASK 0x0000003f
797 #define MIPS_PWCTL_PWEN_SHIFT 31
798 #define MIPS_PWCTL_PWEN_MASK 0x80000000
799 #define MIPS_PWCTL_XK_SHIFT 28
800 #define MIPS_PWCTL_XK_MASK 0x10000000
801 #define MIPS_PWCTL_XS_SHIFT 27
802 #define MIPS_PWCTL_XS_MASK 0x08000000
803 #define MIPS_PWCTL_XU_SHIFT 26
804 #define MIPS_PWCTL_XU_MASK 0x04000000
805 #define MIPS_PWCTL_DPH_SHIFT 7
806 #define MIPS_PWCTL_DPH_MASK 0x00000080
807 #define MIPS_PWCTL_HUGEPG_SHIFT 6
808 #define MIPS_PWCTL_HUGEPG_MASK 0x00000060
809 #define MIPS_PWCTL_PSN_SHIFT 0
810 #define MIPS_PWCTL_PSN_MASK 0x0000003f
812 /* GuestCtl0 fields */
813 #define MIPS_GCTL0_GM_SHIFT 31
814 #define MIPS_GCTL0_GM (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
815 #define MIPS_GCTL0_RI_SHIFT 30
816 #define MIPS_GCTL0_RI (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
817 #define MIPS_GCTL0_MC_SHIFT 29
818 #define MIPS_GCTL0_MC (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
819 #define MIPS_GCTL0_CP0_SHIFT 28
820 #define MIPS_GCTL0_CP0 (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
821 #define MIPS_GCTL0_AT_SHIFT 26
822 #define MIPS_GCTL0_AT (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
823 #define MIPS_GCTL0_GT_SHIFT 25
824 #define MIPS_GCTL0_GT (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
825 #define MIPS_GCTL0_CG_SHIFT 24
826 #define MIPS_GCTL0_CG (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
827 #define MIPS_GCTL0_CF_SHIFT 23
828 #define MIPS_GCTL0_CF (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
829 #define MIPS_GCTL0_G1_SHIFT 22
830 #define MIPS_GCTL0_G1 (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
831 #define MIPS_GCTL0_G0E_SHIFT 19
832 #define MIPS_GCTL0_G0E (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
833 #define MIPS_GCTL0_PT_SHIFT 18
834 #define MIPS_GCTL0_PT (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
835 #define MIPS_GCTL0_RAD_SHIFT 9
836 #define MIPS_GCTL0_RAD (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
837 #define MIPS_GCTL0_DRG_SHIFT 8
838 #define MIPS_GCTL0_DRG (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
839 #define MIPS_GCTL0_G2_SHIFT 7
840 #define MIPS_GCTL0_G2 (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
841 #define MIPS_GCTL0_GEXC_SHIFT 2
842 #define MIPS_GCTL0_GEXC (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
843 #define MIPS_GCTL0_SFC2_SHIFT 1
844 #define MIPS_GCTL0_SFC2 (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
845 #define MIPS_GCTL0_SFC1_SHIFT 0
846 #define MIPS_GCTL0_SFC1 (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
848 /* GuestCtl0.AT Guest address translation control */
849 #define MIPS_GCTL0_AT_ROOT 1 /* Guest MMU under Root control */
850 #define MIPS_GCTL0_AT_GUEST 3 /* Guest MMU under Guest control */
852 /* GuestCtl0.GExcCode Hypervisor exception cause codes */
853 #define MIPS_GCTL0_GEXC_GPSI 0 /* Guest Privileged Sensitive Instruction */
854 #define MIPS_GCTL0_GEXC_GSFC 1 /* Guest Software Field Change */
855 #define MIPS_GCTL0_GEXC_HC 2 /* Hypercall */
856 #define MIPS_GCTL0_GEXC_GRR 3 /* Guest Reserved Instruction Redirect */
857 #define MIPS_GCTL0_GEXC_GVA 8 /* Guest Virtual Address available */
858 #define MIPS_GCTL0_GEXC_GHFC 9 /* Guest Hardware Field Change */
859 #define MIPS_GCTL0_GEXC_GPA 10 /* Guest Physical Address available */
861 /* GuestCtl0Ext fields */
862 #define MIPS_GCTL0EXT_RPW_SHIFT 8
863 #define MIPS_GCTL0EXT_RPW (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
864 #define MIPS_GCTL0EXT_NCC_SHIFT 6
865 #define MIPS_GCTL0EXT_NCC (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
866 #define MIPS_GCTL0EXT_CGI_SHIFT 4
867 #define MIPS_GCTL0EXT_CGI (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
868 #define MIPS_GCTL0EXT_FCD_SHIFT 3
869 #define MIPS_GCTL0EXT_FCD (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
870 #define MIPS_GCTL0EXT_OG_SHIFT 2
871 #define MIPS_GCTL0EXT_OG (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
872 #define MIPS_GCTL0EXT_BG_SHIFT 1
873 #define MIPS_GCTL0EXT_BG (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
874 #define MIPS_GCTL0EXT_MG_SHIFT 0
875 #define MIPS_GCTL0EXT_MG (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
877 /* GuestCtl0Ext.RPW Root page walk configuration */
878 #define MIPS_GCTL0EXT_RPW_BOTH 0 /* Root PW for GPA->RPA and RVA->RPA */
879 #define MIPS_GCTL0EXT_RPW_GPA 2 /* Root PW for GPA->RPA */
880 #define MIPS_GCTL0EXT_RPW_RVA 3 /* Root PW for RVA->RPA */
882 /* GuestCtl0Ext.NCC Nested cache coherency attributes */
883 #define MIPS_GCTL0EXT_NCC_IND 0 /* Guest CCA independent of Root CCA */
884 #define MIPS_GCTL0EXT_NCC_MOD 1 /* Guest CCA modified by Root CCA */
886 /* GuestCtl1 fields */
887 #define MIPS_GCTL1_ID_SHIFT 0
888 #define MIPS_GCTL1_ID_WIDTH 8
889 #define MIPS_GCTL1_ID (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
890 #define MIPS_GCTL1_RID_SHIFT 16
891 #define MIPS_GCTL1_RID_WIDTH 8
892 #define MIPS_GCTL1_RID (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
893 #define MIPS_GCTL1_EID_SHIFT 24
894 #define MIPS_GCTL1_EID_WIDTH 8
895 #define MIPS_GCTL1_EID (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
897 /* GuestID reserved for root context */
898 #define MIPS_GCTL1_ROOT_GUESTID 0
900 /* CDMMBase register bit definitions */
901 #define MIPS_CDMMBASE_SIZE_SHIFT 0
902 #define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
903 #define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
904 #define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
905 #define MIPS_CDMMBASE_ADDR_SHIFT 11
906 #define MIPS_CDMMBASE_ADDR_START 15
908 /* RDHWR register numbers */
909 #define MIPS_HWR_CPUNUM 0 /* CPU number */
910 #define MIPS_HWR_SYNCISTEP 1 /* SYNCI step size */
911 #define MIPS_HWR_CC 2 /* Cycle counter */
912 #define MIPS_HWR_CCRES 3 /* Cycle counter resolution */
913 #define MIPS_HWR_ULR 29 /* UserLocal */
914 #define MIPS_HWR_IMPL1 30 /* Implementation dependent */
915 #define MIPS_HWR_IMPL2 31 /* Implementation dependent */
917 /* Bits in HWREna register */
918 #define MIPS_HWRENA_CPUNUM (_ULCAST_(1) << MIPS_HWR_CPUNUM)
919 #define MIPS_HWRENA_SYNCISTEP (_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
920 #define MIPS_HWRENA_CC (_ULCAST_(1) << MIPS_HWR_CC)
921 #define MIPS_HWRENA_CCRES (_ULCAST_(1) << MIPS_HWR_CCRES)
922 #define MIPS_HWRENA_ULR (_ULCAST_(1) << MIPS_HWR_ULR)
923 #define MIPS_HWRENA_IMPL1 (_ULCAST_(1) << MIPS_HWR_IMPL1)
924 #define MIPS_HWRENA_IMPL2 (_ULCAST_(1) << MIPS_HWR_IMPL2)
927 * Bitfields in the TX39 family CP0 Configuration Register 3
929 #define TX39_CONF_ICS_SHIFT 19
930 #define TX39_CONF_ICS_MASK 0x00380000
931 #define TX39_CONF_ICS_1KB 0x00000000
932 #define TX39_CONF_ICS_2KB 0x00080000
933 #define TX39_CONF_ICS_4KB 0x00100000
934 #define TX39_CONF_ICS_8KB 0x00180000
935 #define TX39_CONF_ICS_16KB 0x00200000
937 #define TX39_CONF_DCS_SHIFT 16
938 #define TX39_CONF_DCS_MASK 0x00070000
939 #define TX39_CONF_DCS_1KB 0x00000000
940 #define TX39_CONF_DCS_2KB 0x00010000
941 #define TX39_CONF_DCS_4KB 0x00020000
942 #define TX39_CONF_DCS_8KB 0x00030000
943 #define TX39_CONF_DCS_16KB 0x00040000
945 #define TX39_CONF_CWFON 0x00004000
946 #define TX39_CONF_WBON 0x00002000
947 #define TX39_CONF_RF_SHIFT 10
948 #define TX39_CONF_RF_MASK 0x00000c00
949 #define TX39_CONF_DOZE 0x00000200
950 #define TX39_CONF_HALT 0x00000100
951 #define TX39_CONF_LOCK 0x00000080
952 #define TX39_CONF_ICE 0x00000020
953 #define TX39_CONF_DCE 0x00000010
954 #define TX39_CONF_IRSIZE_SHIFT 2
955 #define TX39_CONF_IRSIZE_MASK 0x0000000c
956 #define TX39_CONF_DRSIZE_SHIFT 0
957 #define TX39_CONF_DRSIZE_MASK 0x00000003
960 * Interesting Bits in the R10K CP0 Branch Diagnostic Register
962 /* Disable Branch Target Address Cache */
963 #define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
964 /* Enable Branch Prediction Global History */
965 #define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
966 /* Disable Branch Return Cache */
967 #define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
970 #define LOONGSON_DIAG_ITLB (_ULCAST_(1) << 2)
972 #define LOONGSON_DIAG_DTLB (_ULCAST_(1) << 3)
974 #define LOONGSON_DIAG_VTLB (_ULCAST_(1) << 12)
976 #define LOONGSON_DIAG_FTLB (_ULCAST_(1) << 13)
978 /* CvmCtl register field definitions */
979 #define CVMCTL_IPPCI_SHIFT 7
980 #define CVMCTL_IPPCI (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT)
981 #define CVMCTL_IPTI_SHIFT 4
982 #define CVMCTL_IPTI (_U64CAST_(0x7) << CVMCTL_IPTI_SHIFT)
984 /* CvmMemCtl2 register field definitions */
985 #define CVMMEMCTL2_INHIBITTS (_U64CAST_(1) << 17)
987 /* CvmVMConfig register field definitions */
988 #define CVMVMCONF_DGHT (_U64CAST_(1) << 60)
989 #define CVMVMCONF_MMUSIZEM1_S 12
990 #define CVMVMCONF_MMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_MMUSIZEM1_S)
991 #define CVMVMCONF_RMMUSIZEM1_S 0
992 #define CVMVMCONF_RMMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_RMMUSIZEM1_S)
995 * Coprocessor 1 (FPU) register names
997 #define CP1_REVISION $0
1000 #define CP1_FCCR $25
1001 #define CP1_FEXR $26
1002 #define CP1_FENR $28
1003 #define CP1_STATUS $31
1007 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
1009 #define MIPS_FPIR_S (_ULCAST_(1) << 16)
1010 #define MIPS_FPIR_D (_ULCAST_(1) << 17)
1011 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
1012 #define MIPS_FPIR_3D (_ULCAST_(1) << 19)
1013 #define MIPS_FPIR_W (_ULCAST_(1) << 20)
1014 #define MIPS_FPIR_L (_ULCAST_(1) << 21)
1015 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
1016 #define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
1017 #define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
1018 #define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
1021 * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
1023 #define MIPS_FCCR_CONDX_S 0
1024 #define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
1025 #define MIPS_FCCR_COND0_S 0
1026 #define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
1027 #define MIPS_FCCR_COND1_S 1
1028 #define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
1029 #define MIPS_FCCR_COND2_S 2
1030 #define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
1031 #define MIPS_FCCR_COND3_S 3
1032 #define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
1033 #define MIPS_FCCR_COND4_S 4
1034 #define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
1035 #define MIPS_FCCR_COND5_S 5
1036 #define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
1037 #define MIPS_FCCR_COND6_S 6
1038 #define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
1039 #define MIPS_FCCR_COND7_S 7
1040 #define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
1043 * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
1045 #define MIPS_FENR_FS_S 2
1046 #define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
1049 * FPU Status Register Values
1051 #define FPU_CSR_COND_S 23 /* $fcc0 */
1052 #define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
1054 #define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
1055 #define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
1057 #define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
1058 #define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
1059 #define FPU_CSR_COND1_S 25 /* $fcc1 */
1060 #define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
1061 #define FPU_CSR_COND2_S 26 /* $fcc2 */
1062 #define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
1063 #define FPU_CSR_COND3_S 27 /* $fcc3 */
1064 #define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
1065 #define FPU_CSR_COND4_S 28 /* $fcc4 */
1066 #define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
1067 #define FPU_CSR_COND5_S 29 /* $fcc5 */
1068 #define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
1069 #define FPU_CSR_COND6_S 30 /* $fcc6 */
1070 #define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
1071 #define FPU_CSR_COND7_S 31 /* $fcc7 */
1072 #define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
1075 * Bits 22:20 of the FPU Status Register will be read as 0,
1076 * and should be written as zero.
1078 #define FPU_CSR_RSVD (_ULCAST_(7) << 20)
1080 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
1081 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
1084 * X the exception cause indicator
1085 * E the exception enable
1086 * S the sticky/flag bit
1088 #define FPU_CSR_ALL_X 0x0003f000
1089 #define FPU_CSR_UNI_X 0x00020000
1090 #define FPU_CSR_INV_X 0x00010000
1091 #define FPU_CSR_DIV_X 0x00008000
1092 #define FPU_CSR_OVF_X 0x00004000
1093 #define FPU_CSR_UDF_X 0x00002000
1094 #define FPU_CSR_INE_X 0x00001000
1096 #define FPU_CSR_ALL_E 0x00000f80
1097 #define FPU_CSR_INV_E 0x00000800
1098 #define FPU_CSR_DIV_E 0x00000400
1099 #define FPU_CSR_OVF_E 0x00000200
1100 #define FPU_CSR_UDF_E 0x00000100
1101 #define FPU_CSR_INE_E 0x00000080
1103 #define FPU_CSR_ALL_S 0x0000007c
1104 #define FPU_CSR_INV_S 0x00000040
1105 #define FPU_CSR_DIV_S 0x00000020
1106 #define FPU_CSR_OVF_S 0x00000010
1107 #define FPU_CSR_UDF_S 0x00000008
1108 #define FPU_CSR_INE_S 0x00000004
1110 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
1111 #define FPU_CSR_RM 0x00000003
1112 #define FPU_CSR_RN 0x0 /* nearest */
1113 #define FPU_CSR_RZ 0x1 /* towards zero */
1114 #define FPU_CSR_RU 0x2 /* towards +Infinity */
1115 #define FPU_CSR_RD 0x3 /* towards -Infinity */
1118 #ifndef __ASSEMBLY__
1121 * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
1123 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1124 defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1125 #define get_isa16_mode(x) ((x) & 0x1)
1126 #define msk_isa16_mode(x) ((x) & ~0x1)
1127 #define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
1129 #define get_isa16_mode(x) 0
1130 #define msk_isa16_mode(x) (x)
1131 #define set_isa16_mode(x) do { } while(0)
1135 * microMIPS instructions can be 16-bit or 32-bit in length. This
1136 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1138 static inline int mm_insn_16bit(u16 insn
)
1140 u16 opcode
= (insn
>> 10) & 0x7;
1142 return (opcode
>= 1 && opcode
<= 3) ? 1 : 0;
1146 * Helper macros for generating raw instruction encodings in inline asm.
1148 #ifdef CONFIG_CPU_MICROMIPS
1149 #define _ASM_INSN16_IF_MM(_enc) \
1151 ".hword (" #_enc ")\n\t"
1152 #define _ASM_INSN32_IF_MM(_enc) \
1154 ".hword ((" #_enc ") >> 16)\n\t" \
1155 ".hword ((" #_enc ") & 0xffff)\n\t"
1157 #define _ASM_INSN_IF_MIPS(_enc) \
1159 ".word (" #_enc ")\n\t"
1162 #ifndef _ASM_INSN16_IF_MM
1163 #define _ASM_INSN16_IF_MM(_enc)
1165 #ifndef _ASM_INSN32_IF_MM
1166 #define _ASM_INSN32_IF_MM(_enc)
1168 #ifndef _ASM_INSN_IF_MIPS
1169 #define _ASM_INSN_IF_MIPS(_enc)
1173 * TLB Invalidate Flush
1175 static inline void tlbinvf(void)
1177 __asm__
__volatile__(
1179 ".set noreorder\n\t"
1181 _ASM_INSN_IF_MIPS(0x42000004)
1182 _ASM_INSN32_IF_MM(0x0000537c)
1188 * Functions to access the R10000 performance counters. These are basically
1189 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1190 * performance counter number encoded into bits 1 ... 5 of the instruction.
1191 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1192 * disassembler these will look like an access to sel 0 or 1.
1194 #define read_r10k_perf_cntr(counter) \
1196 unsigned int __res; \
1197 __asm__ __volatile__( \
1205 #define write_r10k_perf_cntr(counter,val) \
1207 __asm__ __volatile__( \
1210 : "r" (val), "i" (counter)); \
1213 #define read_r10k_perf_event(counter) \
1215 unsigned int __res; \
1216 __asm__ __volatile__( \
1224 #define write_r10k_perf_cntl(counter,val) \
1226 __asm__ __volatile__( \
1229 : "r" (val), "i" (counter)); \
1234 * Macros to access the system control coprocessor
1237 #define __read_32bit_c0_register(source, sel) \
1238 ({ unsigned int __res; \
1240 __asm__ __volatile__( \
1241 "mfc0\t%0, " #source "\n\t" \
1244 __asm__ __volatile__( \
1245 ".set\tmips32\n\t" \
1246 "mfc0\t%0, " #source ", " #sel "\n\t" \
1252 #define __read_64bit_c0_register(source, sel) \
1253 ({ unsigned long long __res; \
1254 if (sizeof(unsigned long) == 4) \
1255 __res = __read_64bit_c0_split(source, sel); \
1256 else if (sel == 0) \
1257 __asm__ __volatile__( \
1259 "dmfc0\t%0, " #source "\n\t" \
1263 __asm__ __volatile__( \
1264 ".set\tmips64\n\t" \
1265 "dmfc0\t%0, " #source ", " #sel "\n\t" \
1271 #define __write_32bit_c0_register(register, sel, value) \
1274 __asm__ __volatile__( \
1275 "mtc0\t%z0, " #register "\n\t" \
1276 : : "Jr" ((unsigned int)(value))); \
1278 __asm__ __volatile__( \
1279 ".set\tmips32\n\t" \
1280 "mtc0\t%z0, " #register ", " #sel "\n\t" \
1282 : : "Jr" ((unsigned int)(value))); \
1285 #define __write_64bit_c0_register(register, sel, value) \
1287 if (sizeof(unsigned long) == 4) \
1288 __write_64bit_c0_split(register, sel, value); \
1289 else if (sel == 0) \
1290 __asm__ __volatile__( \
1292 "dmtc0\t%z0, " #register "\n\t" \
1294 : : "Jr" (value)); \
1296 __asm__ __volatile__( \
1297 ".set\tmips64\n\t" \
1298 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
1300 : : "Jr" (value)); \
1303 #define __read_ulong_c0_register(reg, sel) \
1304 ((sizeof(unsigned long) == 4) ? \
1305 (unsigned long) __read_32bit_c0_register(reg, sel) : \
1306 (unsigned long) __read_64bit_c0_register(reg, sel))
1308 #define __write_ulong_c0_register(reg, sel, val) \
1310 if (sizeof(unsigned long) == 4) \
1311 __write_32bit_c0_register(reg, sel, val); \
1313 __write_64bit_c0_register(reg, sel, val); \
1317 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1319 #define __read_32bit_c0_ctrl_register(source) \
1320 ({ unsigned int __res; \
1321 __asm__ __volatile__( \
1322 "cfc0\t%0, " #source "\n\t" \
1327 #define __write_32bit_c0_ctrl_register(register, value) \
1329 __asm__ __volatile__( \
1330 "ctc0\t%z0, " #register "\n\t" \
1331 : : "Jr" ((unsigned int)(value))); \
1335 * These versions are only needed for systems with more than 38 bits of
1336 * physical address space running the 32-bit kernel. That's none atm :-)
1338 #define __read_64bit_c0_split(source, sel) \
1340 unsigned long long __val; \
1341 unsigned long __flags; \
1343 local_irq_save(__flags); \
1345 __asm__ __volatile__( \
1346 ".set\tmips64\n\t" \
1347 "dmfc0\t%M0, " #source "\n\t" \
1348 "dsll\t%L0, %M0, 32\n\t" \
1349 "dsra\t%M0, %M0, 32\n\t" \
1350 "dsra\t%L0, %L0, 32\n\t" \
1354 __asm__ __volatile__( \
1355 ".set\tmips64\n\t" \
1356 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
1357 "dsll\t%L0, %M0, 32\n\t" \
1358 "dsra\t%M0, %M0, 32\n\t" \
1359 "dsra\t%L0, %L0, 32\n\t" \
1362 local_irq_restore(__flags); \
1367 #define __write_64bit_c0_split(source, sel, val) \
1369 unsigned long __flags; \
1371 local_irq_save(__flags); \
1373 __asm__ __volatile__( \
1374 ".set\tmips64\n\t" \
1375 "dsll\t%L0, %L0, 32\n\t" \
1376 "dsrl\t%L0, %L0, 32\n\t" \
1377 "dsll\t%M0, %M0, 32\n\t" \
1378 "or\t%L0, %L0, %M0\n\t" \
1379 "dmtc0\t%L0, " #source "\n\t" \
1383 __asm__ __volatile__( \
1384 ".set\tmips64\n\t" \
1385 "dsll\t%L0, %L0, 32\n\t" \
1386 "dsrl\t%L0, %L0, 32\n\t" \
1387 "dsll\t%M0, %M0, 32\n\t" \
1388 "or\t%L0, %L0, %M0\n\t" \
1389 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1392 local_irq_restore(__flags); \
1395 #define __readx_32bit_c0_register(source) \
1397 unsigned int __res; \
1399 __asm__ __volatile__( \
1402 " .set mips32r2 \n" \
1403 " # mfhc0 $1, %1 \n" \
1404 _ASM_INSN_IF_MIPS(0x40410000 | ((%1 & 0x1f) << 11)) \
1405 _ASM_INSN32_IF_MM(0x002000f4 | ((%1 & 0x1f) << 16)) \
1413 #define __writex_32bit_c0_register(register, value) \
1415 __asm__ __volatile__( \
1418 " .set mips32r2 \n" \
1420 " # mthc0 $1, %1 \n" \
1421 _ASM_INSN_IF_MIPS(0x40c10000 | ((%1 & 0x1f) << 11)) \
1422 _ASM_INSN32_IF_MM(0x002002f4 | ((%1 & 0x1f) << 16)) \
1425 : "r" (value), "i" (register)); \
1428 #define read_c0_index() __read_32bit_c0_register($0, 0)
1429 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
1431 #define read_c0_random() __read_32bit_c0_register($1, 0)
1432 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
1434 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
1435 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1437 #define readx_c0_entrylo0() __readx_32bit_c0_register(2)
1438 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1440 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
1441 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1443 #define readx_c0_entrylo1() __readx_32bit_c0_register(3)
1444 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1446 #define read_c0_conf() __read_32bit_c0_register($3, 0)
1447 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1449 #define read_c0_context() __read_ulong_c0_register($4, 0)
1450 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
1452 #define read_c0_contextconfig() __read_32bit_c0_register($4, 1)
1453 #define write_c0_contextconfig(val) __write_32bit_c0_register($4, 1, val)
1455 #define read_c0_userlocal() __read_ulong_c0_register($4, 2)
1456 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1458 #define read_c0_xcontextconfig() __read_ulong_c0_register($4, 3)
1459 #define write_c0_xcontextconfig(val) __write_ulong_c0_register($4, 3, val)
1461 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
1462 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
1464 #define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
1465 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1467 #define read_c0_wired() __read_32bit_c0_register($6, 0)
1468 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
1470 #define read_c0_info() __read_32bit_c0_register($7, 0)
1472 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
1473 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
1475 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
1476 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
1478 #define read_c0_badinstr() __read_32bit_c0_register($8, 1)
1479 #define read_c0_badinstrp() __read_32bit_c0_register($8, 2)
1481 #define read_c0_count() __read_32bit_c0_register($9, 0)
1482 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
1484 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
1485 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
1487 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
1488 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
1490 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
1491 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
1493 #define read_c0_guestctl1() __read_32bit_c0_register($10, 4)
1494 #define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
1496 #define read_c0_guestctl2() __read_32bit_c0_register($10, 5)
1497 #define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
1499 #define read_c0_guestctl3() __read_32bit_c0_register($10, 6)
1500 #define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
1502 #define read_c0_compare() __read_32bit_c0_register($11, 0)
1503 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
1505 #define read_c0_guestctl0ext() __read_32bit_c0_register($11, 4)
1506 #define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1508 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
1509 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
1511 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
1512 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
1514 #define read_c0_status() __read_32bit_c0_register($12, 0)
1516 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1518 #define read_c0_guestctl0() __read_32bit_c0_register($12, 6)
1519 #define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
1521 #define read_c0_gtoffset() __read_32bit_c0_register($12, 7)
1522 #define write_c0_gtoffset(val) __write_32bit_c0_register($12, 7, val)
1524 #define read_c0_cause() __read_32bit_c0_register($13, 0)
1525 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
1527 #define read_c0_epc() __read_ulong_c0_register($14, 0)
1528 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
1530 #define read_c0_prid() __read_32bit_c0_register($15, 0)
1532 #define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3)
1534 #define read_c0_config() __read_32bit_c0_register($16, 0)
1535 #define read_c0_config1() __read_32bit_c0_register($16, 1)
1536 #define read_c0_config2() __read_32bit_c0_register($16, 2)
1537 #define read_c0_config3() __read_32bit_c0_register($16, 3)
1538 #define read_c0_config4() __read_32bit_c0_register($16, 4)
1539 #define read_c0_config5() __read_32bit_c0_register($16, 5)
1540 #define read_c0_config6() __read_32bit_c0_register($16, 6)
1541 #define read_c0_config7() __read_32bit_c0_register($16, 7)
1542 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
1543 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
1544 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
1545 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
1546 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
1547 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
1548 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
1549 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
1551 #define read_c0_lladdr() __read_ulong_c0_register($17, 0)
1552 #define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
1553 #define read_c0_maar() __read_ulong_c0_register($17, 1)
1554 #define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
1555 #define read_c0_maari() __read_32bit_c0_register($17, 2)
1556 #define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
1559 * The WatchLo register. There may be up to 8 of them.
1561 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1562 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
1563 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
1564 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
1565 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
1566 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
1567 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
1568 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
1569 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1570 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
1571 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
1572 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
1573 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
1574 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
1575 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
1576 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
1579 * The WatchHi register. There may be up to 8 of them.
1581 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
1582 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
1583 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
1584 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
1585 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
1586 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
1587 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
1588 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
1590 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
1591 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
1592 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
1593 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
1594 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
1595 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
1596 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
1597 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
1599 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
1600 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
1602 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
1603 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1605 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
1606 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1608 #define read_c0_diag() __read_32bit_c0_register($22, 0)
1609 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1611 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1612 #define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
1613 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1615 #define read_c0_diag1() __read_32bit_c0_register($22, 1)
1616 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
1618 #define read_c0_diag2() __read_32bit_c0_register($22, 2)
1619 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
1621 #define read_c0_diag3() __read_32bit_c0_register($22, 3)
1622 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
1624 #define read_c0_diag4() __read_32bit_c0_register($22, 4)
1625 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
1627 #define read_c0_diag5() __read_32bit_c0_register($22, 5)
1628 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
1630 #define read_c0_debug() __read_32bit_c0_register($23, 0)
1631 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
1633 #define read_c0_depc() __read_ulong_c0_register($24, 0)
1634 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1637 * MIPS32 / MIPS64 performance counters
1639 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1640 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1641 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
1642 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1643 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
1644 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1645 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
1646 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1647 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
1648 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1649 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
1650 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1651 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
1652 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1653 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
1654 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1655 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
1656 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1657 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
1658 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1659 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
1660 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1661 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1662 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1664 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
1665 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1667 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1668 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1670 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1672 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1673 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1675 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
1676 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1678 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1679 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1681 #define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
1682 #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
1684 #define read_c0_staglo() __read_32bit_c0_register($28, 4)
1685 #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
1687 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
1688 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1690 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1691 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1694 #define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1695 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1697 #define read_c0_intctl() __read_32bit_c0_register($12, 1)
1698 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1700 #define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1701 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1703 #define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1704 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1706 #define read_c0_ebase() __read_32bit_c0_register($15, 1)
1707 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1709 #define read_c0_ebase_64() __read_64bit_c0_register($15, 1)
1710 #define write_c0_ebase_64(val) __write_64bit_c0_register($15, 1, val)
1712 #define read_c0_cdmmbase() __read_ulong_c0_register($15, 2)
1713 #define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
1716 #define read_c0_segctl0() __read_32bit_c0_register($5, 2)
1717 #define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
1719 #define read_c0_segctl1() __read_32bit_c0_register($5, 3)
1720 #define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
1722 #define read_c0_segctl2() __read_32bit_c0_register($5, 4)
1723 #define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
1725 /* Hardware Page Table Walker */
1726 #define read_c0_pwbase() __read_ulong_c0_register($5, 5)
1727 #define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
1729 #define read_c0_pwfield() __read_ulong_c0_register($5, 6)
1730 #define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
1732 #define read_c0_pwsize() __read_ulong_c0_register($5, 7)
1733 #define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
1735 #define read_c0_pwctl() __read_32bit_c0_register($6, 6)
1736 #define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
1738 #define read_c0_pgd() __read_64bit_c0_register($9, 7)
1739 #define write_c0_pgd(val) __write_64bit_c0_register($9, 7, val)
1741 #define read_c0_kpgd() __read_64bit_c0_register($31, 7)
1742 #define write_c0_kpgd(val) __write_64bit_c0_register($31, 7, val)
1744 /* Cavium OCTEON (cnMIPS) */
1745 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1746 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1748 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1749 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1751 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1752 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1754 #define read_c0_cvmmemctl2() __read_64bit_c0_register($16, 6)
1755 #define write_c0_cvmmemctl2(val) __write_64bit_c0_register($16, 6, val)
1757 #define read_c0_cvmvmconfig() __read_64bit_c0_register($16, 7)
1758 #define write_c0_cvmvmconfig(val) __write_64bit_c0_register($16, 7, val)
1761 * The cacheerr registers are not standardized. On OCTEON, they are
1764 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1765 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1767 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1768 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1771 #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
1772 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
1774 #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
1775 #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
1777 #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
1778 #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
1781 #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
1782 #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
1784 #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
1785 #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
1787 #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
1788 #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
1790 #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
1791 #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
1793 #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
1794 #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
1797 #define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
1798 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
1800 #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
1801 #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
1803 #define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
1804 #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
1806 #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
1807 #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
1809 #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
1810 #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
1812 #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
1813 #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
1816 * Macros to access the guest system control coprocessor
1819 #ifdef TOOLCHAIN_SUPPORTS_VIRT
1821 #define __read_32bit_gc0_register(source, sel) \
1823 __asm__ __volatile__( \
1825 ".set\tmips32r2\n\t" \
1827 "mfgc0\t%0, $%1, %2\n\t" \
1830 : "i" (source), "i" (sel)); \
1834 #define __read_64bit_gc0_register(source, sel) \
1835 ({ unsigned long long __res; \
1836 __asm__ __volatile__( \
1838 ".set\tmips64r2\n\t" \
1840 "dmfgc0\t%0, $%1, %2\n\t" \
1843 : "i" (source), "i" (sel)); \
1847 #define __write_32bit_gc0_register(register, sel, value) \
1849 __asm__ __volatile__( \
1851 ".set\tmips32r2\n\t" \
1853 "mtgc0\t%z0, $%1, %2\n\t" \
1855 : : "Jr" ((unsigned int)(value)), \
1856 "i" (register), "i" (sel)); \
1859 #define __write_64bit_gc0_register(register, sel, value) \
1861 __asm__ __volatile__( \
1863 ".set\tmips64r2\n\t" \
1865 "dmtgc0\t%z0, $%1, %2\n\t" \
1868 "i" (register), "i" (sel)); \
1871 #else /* TOOLCHAIN_SUPPORTS_VIRT */
1873 #define __read_32bit_gc0_register(source, sel) \
1875 __asm__ __volatile__( \
1878 "# mfgc0\t$1, $%1, %2\n\t" \
1879 _ASM_INSN_IF_MIPS(0x40610000 | %1 << 11 | %2) \
1880 _ASM_INSN32_IF_MM(0x002004fc | %1 << 16 | %2 << 11) \
1881 "move\t%0, $1\n\t" \
1884 : "i" (source), "i" (sel)); \
1888 #define __read_64bit_gc0_register(source, sel) \
1889 ({ unsigned long long __res; \
1890 __asm__ __volatile__( \
1893 "# dmfgc0\t$1, $%1, %2\n\t" \
1894 _ASM_INSN_IF_MIPS(0x40610100 | %1 << 11 | %2) \
1895 _ASM_INSN32_IF_MM(0x582004fc | %1 << 16 | %2 << 11) \
1896 "move\t%0, $1\n\t" \
1899 : "i" (source), "i" (sel)); \
1903 #define __write_32bit_gc0_register(register, sel, value) \
1905 __asm__ __volatile__( \
1908 "move\t$1, %z0\n\t" \
1909 "# mtgc0\t$1, $%1, %2\n\t" \
1910 _ASM_INSN_IF_MIPS(0x40610200 | %1 << 11 | %2) \
1911 _ASM_INSN32_IF_MM(0x002006fc | %1 << 16 | %2 << 11) \
1913 : : "Jr" ((unsigned int)(value)), \
1914 "i" (register), "i" (sel)); \
1917 #define __write_64bit_gc0_register(register, sel, value) \
1919 __asm__ __volatile__( \
1922 "move\t$1, %z0\n\t" \
1923 "# dmtgc0\t$1, $%1, %2\n\t" \
1924 _ASM_INSN_IF_MIPS(0x40610300 | %1 << 11 | %2) \
1925 _ASM_INSN32_IF_MM(0x582006fc | %1 << 16 | %2 << 11) \
1928 "i" (register), "i" (sel)); \
1931 #endif /* !TOOLCHAIN_SUPPORTS_VIRT */
1933 #define __read_ulong_gc0_register(reg, sel) \
1934 ((sizeof(unsigned long) == 4) ? \
1935 (unsigned long) __read_32bit_gc0_register(reg, sel) : \
1936 (unsigned long) __read_64bit_gc0_register(reg, sel))
1938 #define __write_ulong_gc0_register(reg, sel, val) \
1940 if (sizeof(unsigned long) == 4) \
1941 __write_32bit_gc0_register(reg, sel, val); \
1943 __write_64bit_gc0_register(reg, sel, val); \
1946 #define read_gc0_index() __read_32bit_gc0_register(0, 0)
1947 #define write_gc0_index(val) __write_32bit_gc0_register(0, 0, val)
1949 #define read_gc0_entrylo0() __read_ulong_gc0_register(2, 0)
1950 #define write_gc0_entrylo0(val) __write_ulong_gc0_register(2, 0, val)
1952 #define read_gc0_entrylo1() __read_ulong_gc0_register(3, 0)
1953 #define write_gc0_entrylo1(val) __write_ulong_gc0_register(3, 0, val)
1955 #define read_gc0_context() __read_ulong_gc0_register(4, 0)
1956 #define write_gc0_context(val) __write_ulong_gc0_register(4, 0, val)
1958 #define read_gc0_contextconfig() __read_32bit_gc0_register(4, 1)
1959 #define write_gc0_contextconfig(val) __write_32bit_gc0_register(4, 1, val)
1961 #define read_gc0_userlocal() __read_ulong_gc0_register(4, 2)
1962 #define write_gc0_userlocal(val) __write_ulong_gc0_register(4, 2, val)
1964 #define read_gc0_xcontextconfig() __read_ulong_gc0_register(4, 3)
1965 #define write_gc0_xcontextconfig(val) __write_ulong_gc0_register(4, 3, val)
1967 #define read_gc0_pagemask() __read_32bit_gc0_register(5, 0)
1968 #define write_gc0_pagemask(val) __write_32bit_gc0_register(5, 0, val)
1970 #define read_gc0_pagegrain() __read_32bit_gc0_register(5, 1)
1971 #define write_gc0_pagegrain(val) __write_32bit_gc0_register(5, 1, val)
1973 #define read_gc0_segctl0() __read_ulong_gc0_register(5, 2)
1974 #define write_gc0_segctl0(val) __write_ulong_gc0_register(5, 2, val)
1976 #define read_gc0_segctl1() __read_ulong_gc0_register(5, 3)
1977 #define write_gc0_segctl1(val) __write_ulong_gc0_register(5, 3, val)
1979 #define read_gc0_segctl2() __read_ulong_gc0_register(5, 4)
1980 #define write_gc0_segctl2(val) __write_ulong_gc0_register(5, 4, val)
1982 #define read_gc0_pwbase() __read_ulong_gc0_register(5, 5)
1983 #define write_gc0_pwbase(val) __write_ulong_gc0_register(5, 5, val)
1985 #define read_gc0_pwfield() __read_ulong_gc0_register(5, 6)
1986 #define write_gc0_pwfield(val) __write_ulong_gc0_register(5, 6, val)
1988 #define read_gc0_pwsize() __read_ulong_gc0_register(5, 7)
1989 #define write_gc0_pwsize(val) __write_ulong_gc0_register(5, 7, val)
1991 #define read_gc0_wired() __read_32bit_gc0_register(6, 0)
1992 #define write_gc0_wired(val) __write_32bit_gc0_register(6, 0, val)
1994 #define read_gc0_pwctl() __read_32bit_gc0_register(6, 6)
1995 #define write_gc0_pwctl(val) __write_32bit_gc0_register(6, 6, val)
1997 #define read_gc0_hwrena() __read_32bit_gc0_register(7, 0)
1998 #define write_gc0_hwrena(val) __write_32bit_gc0_register(7, 0, val)
2000 #define read_gc0_badvaddr() __read_ulong_gc0_register(8, 0)
2001 #define write_gc0_badvaddr(val) __write_ulong_gc0_register(8, 0, val)
2003 #define read_gc0_badinstr() __read_32bit_gc0_register(8, 1)
2004 #define write_gc0_badinstr(val) __write_32bit_gc0_register(8, 1, val)
2006 #define read_gc0_badinstrp() __read_32bit_gc0_register(8, 2)
2007 #define write_gc0_badinstrp(val) __write_32bit_gc0_register(8, 2, val)
2009 #define read_gc0_count() __read_32bit_gc0_register(9, 0)
2011 #define read_gc0_entryhi() __read_ulong_gc0_register(10, 0)
2012 #define write_gc0_entryhi(val) __write_ulong_gc0_register(10, 0, val)
2014 #define read_gc0_compare() __read_32bit_gc0_register(11, 0)
2015 #define write_gc0_compare(val) __write_32bit_gc0_register(11, 0, val)
2017 #define read_gc0_status() __read_32bit_gc0_register(12, 0)
2018 #define write_gc0_status(val) __write_32bit_gc0_register(12, 0, val)
2020 #define read_gc0_intctl() __read_32bit_gc0_register(12, 1)
2021 #define write_gc0_intctl(val) __write_32bit_gc0_register(12, 1, val)
2023 #define read_gc0_cause() __read_32bit_gc0_register(13, 0)
2024 #define write_gc0_cause(val) __write_32bit_gc0_register(13, 0, val)
2026 #define read_gc0_epc() __read_ulong_gc0_register(14, 0)
2027 #define write_gc0_epc(val) __write_ulong_gc0_register(14, 0, val)
2029 #define read_gc0_prid() __read_32bit_gc0_register(15, 0)
2031 #define read_gc0_ebase() __read_32bit_gc0_register(15, 1)
2032 #define write_gc0_ebase(val) __write_32bit_gc0_register(15, 1, val)
2034 #define read_gc0_ebase_64() __read_64bit_gc0_register(15, 1)
2035 #define write_gc0_ebase_64(val) __write_64bit_gc0_register(15, 1, val)
2037 #define read_gc0_config() __read_32bit_gc0_register(16, 0)
2038 #define read_gc0_config1() __read_32bit_gc0_register(16, 1)
2039 #define read_gc0_config2() __read_32bit_gc0_register(16, 2)
2040 #define read_gc0_config3() __read_32bit_gc0_register(16, 3)
2041 #define read_gc0_config4() __read_32bit_gc0_register(16, 4)
2042 #define read_gc0_config5() __read_32bit_gc0_register(16, 5)
2043 #define read_gc0_config6() __read_32bit_gc0_register(16, 6)
2044 #define read_gc0_config7() __read_32bit_gc0_register(16, 7)
2045 #define write_gc0_config(val) __write_32bit_gc0_register(16, 0, val)
2046 #define write_gc0_config1(val) __write_32bit_gc0_register(16, 1, val)
2047 #define write_gc0_config2(val) __write_32bit_gc0_register(16, 2, val)
2048 #define write_gc0_config3(val) __write_32bit_gc0_register(16, 3, val)
2049 #define write_gc0_config4(val) __write_32bit_gc0_register(16, 4, val)
2050 #define write_gc0_config5(val) __write_32bit_gc0_register(16, 5, val)
2051 #define write_gc0_config6(val) __write_32bit_gc0_register(16, 6, val)
2052 #define write_gc0_config7(val) __write_32bit_gc0_register(16, 7, val)
2054 #define read_gc0_lladdr() __read_ulong_gc0_register(17, 0)
2055 #define write_gc0_lladdr(val) __write_ulong_gc0_register(17, 0, val)
2057 #define read_gc0_watchlo0() __read_ulong_gc0_register(18, 0)
2058 #define read_gc0_watchlo1() __read_ulong_gc0_register(18, 1)
2059 #define read_gc0_watchlo2() __read_ulong_gc0_register(18, 2)
2060 #define read_gc0_watchlo3() __read_ulong_gc0_register(18, 3)
2061 #define read_gc0_watchlo4() __read_ulong_gc0_register(18, 4)
2062 #define read_gc0_watchlo5() __read_ulong_gc0_register(18, 5)
2063 #define read_gc0_watchlo6() __read_ulong_gc0_register(18, 6)
2064 #define read_gc0_watchlo7() __read_ulong_gc0_register(18, 7)
2065 #define write_gc0_watchlo0(val) __write_ulong_gc0_register(18, 0, val)
2066 #define write_gc0_watchlo1(val) __write_ulong_gc0_register(18, 1, val)
2067 #define write_gc0_watchlo2(val) __write_ulong_gc0_register(18, 2, val)
2068 #define write_gc0_watchlo3(val) __write_ulong_gc0_register(18, 3, val)
2069 #define write_gc0_watchlo4(val) __write_ulong_gc0_register(18, 4, val)
2070 #define write_gc0_watchlo5(val) __write_ulong_gc0_register(18, 5, val)
2071 #define write_gc0_watchlo6(val) __write_ulong_gc0_register(18, 6, val)
2072 #define write_gc0_watchlo7(val) __write_ulong_gc0_register(18, 7, val)
2074 #define read_gc0_watchhi0() __read_32bit_gc0_register(19, 0)
2075 #define read_gc0_watchhi1() __read_32bit_gc0_register(19, 1)
2076 #define read_gc0_watchhi2() __read_32bit_gc0_register(19, 2)
2077 #define read_gc0_watchhi3() __read_32bit_gc0_register(19, 3)
2078 #define read_gc0_watchhi4() __read_32bit_gc0_register(19, 4)
2079 #define read_gc0_watchhi5() __read_32bit_gc0_register(19, 5)
2080 #define read_gc0_watchhi6() __read_32bit_gc0_register(19, 6)
2081 #define read_gc0_watchhi7() __read_32bit_gc0_register(19, 7)
2082 #define write_gc0_watchhi0(val) __write_32bit_gc0_register(19, 0, val)
2083 #define write_gc0_watchhi1(val) __write_32bit_gc0_register(19, 1, val)
2084 #define write_gc0_watchhi2(val) __write_32bit_gc0_register(19, 2, val)
2085 #define write_gc0_watchhi3(val) __write_32bit_gc0_register(19, 3, val)
2086 #define write_gc0_watchhi4(val) __write_32bit_gc0_register(19, 4, val)
2087 #define write_gc0_watchhi5(val) __write_32bit_gc0_register(19, 5, val)
2088 #define write_gc0_watchhi6(val) __write_32bit_gc0_register(19, 6, val)
2089 #define write_gc0_watchhi7(val) __write_32bit_gc0_register(19, 7, val)
2091 #define read_gc0_xcontext() __read_ulong_gc0_register(20, 0)
2092 #define write_gc0_xcontext(val) __write_ulong_gc0_register(20, 0, val)
2094 #define read_gc0_perfctrl0() __read_32bit_gc0_register(25, 0)
2095 #define write_gc0_perfctrl0(val) __write_32bit_gc0_register(25, 0, val)
2096 #define read_gc0_perfcntr0() __read_32bit_gc0_register(25, 1)
2097 #define write_gc0_perfcntr0(val) __write_32bit_gc0_register(25, 1, val)
2098 #define read_gc0_perfcntr0_64() __read_64bit_gc0_register(25, 1)
2099 #define write_gc0_perfcntr0_64(val) __write_64bit_gc0_register(25, 1, val)
2100 #define read_gc0_perfctrl1() __read_32bit_gc0_register(25, 2)
2101 #define write_gc0_perfctrl1(val) __write_32bit_gc0_register(25, 2, val)
2102 #define read_gc0_perfcntr1() __read_32bit_gc0_register(25, 3)
2103 #define write_gc0_perfcntr1(val) __write_32bit_gc0_register(25, 3, val)
2104 #define read_gc0_perfcntr1_64() __read_64bit_gc0_register(25, 3)
2105 #define write_gc0_perfcntr1_64(val) __write_64bit_gc0_register(25, 3, val)
2106 #define read_gc0_perfctrl2() __read_32bit_gc0_register(25, 4)
2107 #define write_gc0_perfctrl2(val) __write_32bit_gc0_register(25, 4, val)
2108 #define read_gc0_perfcntr2() __read_32bit_gc0_register(25, 5)
2109 #define write_gc0_perfcntr2(val) __write_32bit_gc0_register(25, 5, val)
2110 #define read_gc0_perfcntr2_64() __read_64bit_gc0_register(25, 5)
2111 #define write_gc0_perfcntr2_64(val) __write_64bit_gc0_register(25, 5, val)
2112 #define read_gc0_perfctrl3() __read_32bit_gc0_register(25, 6)
2113 #define write_gc0_perfctrl3(val) __write_32bit_gc0_register(25, 6, val)
2114 #define read_gc0_perfcntr3() __read_32bit_gc0_register(25, 7)
2115 #define write_gc0_perfcntr3(val) __write_32bit_gc0_register(25, 7, val)
2116 #define read_gc0_perfcntr3_64() __read_64bit_gc0_register(25, 7)
2117 #define write_gc0_perfcntr3_64(val) __write_64bit_gc0_register(25, 7, val)
2119 #define read_gc0_errorepc() __read_ulong_gc0_register(30, 0)
2120 #define write_gc0_errorepc(val) __write_ulong_gc0_register(30, 0, val)
2122 #define read_gc0_kscratch1() __read_ulong_gc0_register(31, 2)
2123 #define read_gc0_kscratch2() __read_ulong_gc0_register(31, 3)
2124 #define read_gc0_kscratch3() __read_ulong_gc0_register(31, 4)
2125 #define read_gc0_kscratch4() __read_ulong_gc0_register(31, 5)
2126 #define read_gc0_kscratch5() __read_ulong_gc0_register(31, 6)
2127 #define read_gc0_kscratch6() __read_ulong_gc0_register(31, 7)
2128 #define write_gc0_kscratch1(val) __write_ulong_gc0_register(31, 2, val)
2129 #define write_gc0_kscratch2(val) __write_ulong_gc0_register(31, 3, val)
2130 #define write_gc0_kscratch3(val) __write_ulong_gc0_register(31, 4, val)
2131 #define write_gc0_kscratch4(val) __write_ulong_gc0_register(31, 5, val)
2132 #define write_gc0_kscratch5(val) __write_ulong_gc0_register(31, 6, val)
2133 #define write_gc0_kscratch6(val) __write_ulong_gc0_register(31, 7, val)
2135 /* Cavium OCTEON (cnMIPS) */
2136 #define read_gc0_cvmcount() __read_ulong_gc0_register(9, 6)
2137 #define write_gc0_cvmcount(val) __write_ulong_gc0_register(9, 6, val)
2139 #define read_gc0_cvmctl() __read_64bit_gc0_register(9, 7)
2140 #define write_gc0_cvmctl(val) __write_64bit_gc0_register(9, 7, val)
2142 #define read_gc0_cvmmemctl() __read_64bit_gc0_register(11, 7)
2143 #define write_gc0_cvmmemctl(val) __write_64bit_gc0_register(11, 7, val)
2145 #define read_gc0_cvmmemctl2() __read_64bit_gc0_register(16, 6)
2146 #define write_gc0_cvmmemctl2(val) __write_64bit_gc0_register(16, 6, val)
2149 * Macros to access the floating point coprocessor control registers
2151 #define _read_32bit_cp1_register(source, gas_hardfloat) \
2153 unsigned int __res; \
2155 __asm__ __volatile__( \
2157 " .set reorder \n" \
2158 " # gas fails to assemble cfc1 for some archs, \n" \
2159 " # like Octeon. \n" \
2161 " "STR(gas_hardfloat)" \n" \
2162 " cfc1 %0,"STR(source)" \n" \
2168 #define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
2170 __asm__ __volatile__( \
2172 " .set reorder \n" \
2173 " "STR(gas_hardfloat)" \n" \
2174 " ctc1 %0,"STR(dest)" \n" \
2179 #ifdef GAS_HAS_SET_HARDFLOAT
2180 #define read_32bit_cp1_register(source) \
2181 _read_32bit_cp1_register(source, .set hardfloat)
2182 #define write_32bit_cp1_register(dest, val) \
2183 _write_32bit_cp1_register(dest, val, .set hardfloat)
2185 #define read_32bit_cp1_register(source) \
2186 _read_32bit_cp1_register(source, )
2187 #define write_32bit_cp1_register(dest, val) \
2188 _write_32bit_cp1_register(dest, val, )
2192 #define rddsp(mask) \
2194 unsigned int __dspctl; \
2196 __asm__ __volatile__( \
2199 " rddsp %0, %x1 \n" \
2206 #define wrdsp(val, mask) \
2208 __asm__ __volatile__( \
2211 " wrdsp %0, %x1 \n" \
2214 : "r" (val), "i" (mask)); \
2223 " mflo %0, $ac0 \n" \
2235 " mflo %0, $ac1 \n" \
2247 " mflo %0, $ac2 \n" \
2259 " mflo %0, $ac3 \n" \
2271 " mfhi %0, $ac0 \n" \
2283 " mfhi %0, $ac1 \n" \
2295 " mfhi %0, $ac2 \n" \
2307 " mfhi %0, $ac3 \n" \
2319 " mtlo %0, $ac0 \n" \
2330 " mtlo %0, $ac1 \n" \
2341 " mtlo %0, $ac2 \n" \
2352 " mtlo %0, $ac3 \n" \
2363 " mthi %0, $ac0 \n" \
2374 " mthi %0, $ac1 \n" \
2385 " mthi %0, $ac2 \n" \
2396 " mthi %0, $ac3 \n" \
2404 #define rddsp(mask) \
2406 unsigned int __res; \
2408 __asm__ __volatile__( \
2411 " # rddsp $1, %x1 \n" \
2412 _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16)) \
2413 _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14)) \
2421 #define wrdsp(val, mask) \
2423 __asm__ __volatile__( \
2427 " # wrdsp $1, %x1 \n" \
2428 _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11)) \
2429 _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14)) \
2432 : "r" (val), "i" (mask)); \
2435 #define _dsp_mfxxx(ins) \
2437 unsigned long __treg; \
2439 __asm__ __volatile__( \
2442 _ASM_INSN_IF_MIPS(0x00000810 | %X1) \
2443 _ASM_INSN32_IF_MM(0x0001007c | %x1) \
2451 #define _dsp_mtxxx(val, ins) \
2453 __asm__ __volatile__( \
2457 _ASM_INSN_IF_MIPS(0x00200011 | %X1) \
2458 _ASM_INSN32_IF_MM(0x0001207c | %x1) \
2461 : "r" (val), "i" (ins)); \
2464 #ifdef CONFIG_CPU_MICROMIPS
2466 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2467 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2469 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2470 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2472 #else /* !CONFIG_CPU_MICROMIPS */
2474 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2475 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2477 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2478 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2480 #endif /* CONFIG_CPU_MICROMIPS */
2482 #define mflo0() _dsp_mflo(0)
2483 #define mflo1() _dsp_mflo(1)
2484 #define mflo2() _dsp_mflo(2)
2485 #define mflo3() _dsp_mflo(3)
2487 #define mfhi0() _dsp_mfhi(0)
2488 #define mfhi1() _dsp_mfhi(1)
2489 #define mfhi2() _dsp_mfhi(2)
2490 #define mfhi3() _dsp_mfhi(3)
2492 #define mtlo0(x) _dsp_mtlo(x, 0)
2493 #define mtlo1(x) _dsp_mtlo(x, 1)
2494 #define mtlo2(x) _dsp_mtlo(x, 2)
2495 #define mtlo3(x) _dsp_mtlo(x, 3)
2497 #define mthi0(x) _dsp_mthi(x, 0)
2498 #define mthi1(x) _dsp_mthi(x, 1)
2499 #define mthi2(x) _dsp_mthi(x, 2)
2500 #define mthi3(x) _dsp_mthi(x, 3)
2507 * It is responsibility of the caller to take care of any TLB hazards.
2509 static inline void tlb_probe(void)
2511 __asm__
__volatile__(
2512 ".set noreorder\n\t"
2517 static inline void tlb_read(void)
2519 #if MIPS34K_MISSED_ITLB_WAR
2522 __asm__
__volatile__(
2524 " .set noreorder \n"
2527 " .word 0x41610001 # dvpe $1 \n"
2533 instruction_hazard();
2536 __asm__
__volatile__(
2537 ".set noreorder\n\t"
2541 #if MIPS34K_MISSED_ITLB_WAR
2542 if ((res
& _ULCAST_(1)))
2543 __asm__
__volatile__(
2545 " .set noreorder \n"
2548 " .word 0x41600021 # evpe \n"
2554 static inline void tlb_write_indexed(void)
2556 __asm__
__volatile__(
2557 ".set noreorder\n\t"
2562 static inline void tlb_write_random(void)
2564 __asm__
__volatile__(
2565 ".set noreorder\n\t"
2570 #ifdef TOOLCHAIN_SUPPORTS_VIRT
2573 * Guest TLB operations.
2575 * It is responsibility of the caller to take care of any TLB hazards.
2577 static inline void guest_tlb_probe(void)
2579 __asm__
__volatile__(
2581 ".set noreorder\n\t"
2587 static inline void guest_tlb_read(void)
2589 __asm__
__volatile__(
2591 ".set noreorder\n\t"
2597 static inline void guest_tlb_write_indexed(void)
2599 __asm__
__volatile__(
2601 ".set noreorder\n\t"
2607 static inline void guest_tlb_write_random(void)
2609 __asm__
__volatile__(
2611 ".set noreorder\n\t"
2618 * Guest TLB Invalidate Flush
2620 static inline void guest_tlbinvf(void)
2622 __asm__
__volatile__(
2624 ".set noreorder\n\t"
2630 #else /* TOOLCHAIN_SUPPORTS_VIRT */
2633 * Guest TLB operations.
2635 * It is responsibility of the caller to take care of any TLB hazards.
2637 static inline void guest_tlb_probe(void)
2639 __asm__
__volatile__(
2641 _ASM_INSN_IF_MIPS(0x42000010)
2642 _ASM_INSN32_IF_MM(0x0000017c));
2645 static inline void guest_tlb_read(void)
2647 __asm__
__volatile__(
2649 _ASM_INSN_IF_MIPS(0x42000009)
2650 _ASM_INSN32_IF_MM(0x0000117c));
2653 static inline void guest_tlb_write_indexed(void)
2655 __asm__
__volatile__(
2657 _ASM_INSN_IF_MIPS(0x4200000a)
2658 _ASM_INSN32_IF_MM(0x0000217c));
2661 static inline void guest_tlb_write_random(void)
2663 __asm__
__volatile__(
2665 _ASM_INSN_IF_MIPS(0x4200000e)
2666 _ASM_INSN32_IF_MM(0x0000317c));
2670 * Guest TLB Invalidate Flush
2672 static inline void guest_tlbinvf(void)
2674 __asm__
__volatile__(
2676 _ASM_INSN_IF_MIPS(0x4200000c)
2677 _ASM_INSN32_IF_MM(0x0000517c));
2680 #endif /* !TOOLCHAIN_SUPPORTS_VIRT */
2683 * Manipulate bits in a register.
2685 #define __BUILD_SET_COMMON(name) \
2686 static inline unsigned int \
2687 set_##name(unsigned int set) \
2689 unsigned int res, new; \
2691 res = read_##name(); \
2693 write_##name(new); \
2698 static inline unsigned int \
2699 clear_##name(unsigned int clear) \
2701 unsigned int res, new; \
2703 res = read_##name(); \
2704 new = res & ~clear; \
2705 write_##name(new); \
2710 static inline unsigned int \
2711 change_##name(unsigned int change, unsigned int val) \
2713 unsigned int res, new; \
2715 res = read_##name(); \
2716 new = res & ~change; \
2717 new |= (val & change); \
2718 write_##name(new); \
2724 * Manipulate bits in a c0 register.
2726 #define __BUILD_SET_C0(name) __BUILD_SET_COMMON(c0_##name)
2728 __BUILD_SET_C0(status
)
2729 __BUILD_SET_C0(cause
)
2730 __BUILD_SET_C0(config
)
2731 __BUILD_SET_C0(config5
)
2732 __BUILD_SET_C0(intcontrol
)
2733 __BUILD_SET_C0(intctl
)
2734 __BUILD_SET_C0(srsmap
)
2735 __BUILD_SET_C0(pagegrain
)
2736 __BUILD_SET_C0(guestctl0
)
2737 __BUILD_SET_C0(guestctl0ext
)
2738 __BUILD_SET_C0(guestctl1
)
2739 __BUILD_SET_C0(guestctl2
)
2740 __BUILD_SET_C0(guestctl3
)
2741 __BUILD_SET_C0(brcm_config_0
)
2742 __BUILD_SET_C0(brcm_bus_pll
)
2743 __BUILD_SET_C0(brcm_reset
)
2744 __BUILD_SET_C0(brcm_cmt_intr
)
2745 __BUILD_SET_C0(brcm_cmt_ctrl
)
2746 __BUILD_SET_C0(brcm_config
)
2747 __BUILD_SET_C0(brcm_mode
)
2750 * Manipulate bits in a guest c0 register.
2752 #define __BUILD_SET_GC0(name) __BUILD_SET_COMMON(gc0_##name)
2754 __BUILD_SET_GC0(wired
)
2755 __BUILD_SET_GC0(status
)
2756 __BUILD_SET_GC0(cause
)
2757 __BUILD_SET_GC0(ebase
)
2758 __BUILD_SET_GC0(config1
)
2761 * Return low 10 bits of ebase.
2762 * Note that under KVM (MIPSVZ) this returns vcpu id.
2764 static inline unsigned int get_ebase_cpunum(void)
2766 return read_c0_ebase() & MIPS_EBASE_CPUNUM
;
2769 #endif /* !__ASSEMBLY__ */
2771 #endif /* _ASM_MIPSREGS_H */