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2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #ifndef _NLM_HAL_PIC_H
36 #define _NLM_HAL_PIC_H
38 /* PIC Specific registers */
41 /* PIC control register defines */
42 #define PIC_CTRL_ITV 32 /* interrupt timeout value */
43 #define PIC_CTRL_ICI 19 /* ICI interrupt timeout enable */
44 #define PIC_CTRL_ITE 18 /* interrupt timeout enable */
45 #define PIC_CTRL_STE 10 /* system timer interrupt enable */
46 #define PIC_CTRL_WWR1 8 /* watchdog 1 wraparound count for reset */
47 #define PIC_CTRL_WWR0 6 /* watchdog 0 wraparound count for reset */
48 #define PIC_CTRL_WWN1 4 /* watchdog 1 wraparound count for NMI */
49 #define PIC_CTRL_WWN0 2 /* watchdog 0 wraparound count for NMI */
50 #define PIC_CTRL_WTE 0 /* watchdog timer enable */
52 /* PIC Status register defines */
53 #define PIC_ICI_STATUS 33 /* ICI interrupt timeout status */
54 #define PIC_ITE_STATUS 32 /* interrupt timeout status */
55 #define PIC_STS_STATUS 4 /* System timer interrupt status */
56 #define PIC_WNS_STATUS 2 /* NMI status for watchdog timers */
57 #define PIC_WIS_STATUS 0 /* Interrupt status for watchdog timers */
59 /* PIC IPI control register offsets */
60 #define PIC_IPICTRL_NMI 32
61 #define PIC_IPICTRL_RIV 20 /* received interrupt vector */
62 #define PIC_IPICTRL_IDB 16 /* interrupt destination base */
63 #define PIC_IPICTRL_DTE 0 /* interrupt destination thread enables */
65 /* PIC IRT register offsets */
66 #define PIC_IRT_ENABLE 31
67 #define PIC_IRT_NMI 29
68 #define PIC_IRT_SCH 28 /* Scheduling scheme */
69 #define PIC_IRT_RVEC 20 /* Interrupt receive vectors */
70 #define PIC_IRT_DT 19 /* Destination type */
71 #define PIC_IRT_DB 16 /* Destination base */
72 #define PIC_IRT_DTE 0 /* Destination thread enables */
74 #define PIC_BYTESWAP 0x02
75 #define PIC_STATUS 0x04
76 #define PIC_INTR_TIMEOUT 0x06
77 #define PIC_ICI0_INTR_TIMEOUT 0x08
78 #define PIC_ICI1_INTR_TIMEOUT 0x0a
79 #define PIC_ICI2_INTR_TIMEOUT 0x0c
80 #define PIC_IPI_CTL 0x0e
81 #define PIC_INT_ACK 0x10
82 #define PIC_INT_PENDING0 0x12
83 #define PIC_INT_PENDING1 0x14
84 #define PIC_INT_PENDING2 0x16
86 #define PIC_WDOG0_MAXVAL 0x18
87 #define PIC_WDOG0_COUNT 0x1a
88 #define PIC_WDOG0_ENABLE0 0x1c
89 #define PIC_WDOG0_ENABLE1 0x1e
90 #define PIC_WDOG0_BEATCMD 0x20
91 #define PIC_WDOG0_BEAT0 0x22
92 #define PIC_WDOG0_BEAT1 0x24
94 #define PIC_WDOG1_MAXVAL 0x26
95 #define PIC_WDOG1_COUNT 0x28
96 #define PIC_WDOG1_ENABLE0 0x2a
97 #define PIC_WDOG1_ENABLE1 0x2c
98 #define PIC_WDOG1_BEATCMD 0x2e
99 #define PIC_WDOG1_BEAT0 0x30
100 #define PIC_WDOG1_BEAT1 0x32
102 #define PIC_WDOG_MAXVAL(i) (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0))
103 #define PIC_WDOG_COUNT(i) (PIC_WDOG0_COUNT + ((i) ? 7 : 0))
104 #define PIC_WDOG_ENABLE0(i) (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0))
105 #define PIC_WDOG_ENABLE1(i) (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0))
106 #define PIC_WDOG_BEATCMD(i) (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0))
107 #define PIC_WDOG_BEAT0(i) (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0))
108 #define PIC_WDOG_BEAT1(i) (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0))
110 #define PIC_TIMER0_MAXVAL 0x34
111 #define PIC_TIMER1_MAXVAL 0x36
112 #define PIC_TIMER2_MAXVAL 0x38
113 #define PIC_TIMER3_MAXVAL 0x3a
114 #define PIC_TIMER4_MAXVAL 0x3c
115 #define PIC_TIMER5_MAXVAL 0x3e
116 #define PIC_TIMER6_MAXVAL 0x40
117 #define PIC_TIMER7_MAXVAL 0x42
118 #define PIC_TIMER_MAXVAL(i) (PIC_TIMER0_MAXVAL + ((i) * 2))
120 #define PIC_TIMER0_COUNT 0x44
121 #define PIC_TIMER1_COUNT 0x46
122 #define PIC_TIMER2_COUNT 0x48
123 #define PIC_TIMER3_COUNT 0x4a
124 #define PIC_TIMER4_COUNT 0x4c
125 #define PIC_TIMER5_COUNT 0x4e
126 #define PIC_TIMER6_COUNT 0x50
127 #define PIC_TIMER7_COUNT 0x52
128 #define PIC_TIMER_COUNT(i) (PIC_TIMER0_COUNT + ((i) * 2))
130 #define PIC_ITE0_N0_N1 0x54
131 #define PIC_ITE1_N0_N1 0x58
132 #define PIC_ITE2_N0_N1 0x5c
133 #define PIC_ITE3_N0_N1 0x60
134 #define PIC_ITE4_N0_N1 0x64
135 #define PIC_ITE5_N0_N1 0x68
136 #define PIC_ITE6_N0_N1 0x6c
137 #define PIC_ITE7_N0_N1 0x70
138 #define PIC_ITE_N0_N1(i) (PIC_ITE0_N0_N1 + ((i) * 4))
140 #define PIC_ITE0_N2_N3 0x56
141 #define PIC_ITE1_N2_N3 0x5a
142 #define PIC_ITE2_N2_N3 0x5e
143 #define PIC_ITE3_N2_N3 0x62
144 #define PIC_ITE4_N2_N3 0x66
145 #define PIC_ITE5_N2_N3 0x6a
146 #define PIC_ITE6_N2_N3 0x6e
147 #define PIC_ITE7_N2_N3 0x72
148 #define PIC_ITE_N2_N3(i) (PIC_ITE0_N2_N3 + ((i) * 4))
150 #define PIC_IRT0 0x74
151 #define PIC_IRT(i) (PIC_IRT0 + ((i) * 2))
153 #define TIMER_CYCLES_MAXVAL 0xffffffffffffffffULL
158 #define PIC_NUM_IRTS 160
160 #define PIC_IRT_WD_0_INDEX 0
161 #define PIC_IRT_WD_1_INDEX 1
162 #define PIC_IRT_WD_NMI_0_INDEX 2
163 #define PIC_IRT_WD_NMI_1_INDEX 3
164 #define PIC_IRT_TIMER_0_INDEX 4
165 #define PIC_IRT_TIMER_1_INDEX 5
166 #define PIC_IRT_TIMER_2_INDEX 6
167 #define PIC_IRT_TIMER_3_INDEX 7
168 #define PIC_IRT_TIMER_4_INDEX 8
169 #define PIC_IRT_TIMER_5_INDEX 9
170 #define PIC_IRT_TIMER_6_INDEX 10
171 #define PIC_IRT_TIMER_7_INDEX 11
172 #define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX
173 #define PIC_IRT_TIMER_INDEX(num) ((num) + PIC_IRT_TIMER_0_INDEX)
177 #define PIC_NUM_MSG_Q_IRTS 32
178 #define PIC_IRT_MSG_Q0_INDEX 12
179 #define PIC_IRT_MSG_Q_INDEX(qid) ((qid) + PIC_IRT_MSG_Q0_INDEX)
181 #define PIC_IRT_MSG_0_INDEX 44
182 #define PIC_IRT_MSG_1_INDEX 45
184 #define PIC_NUM_PCIE_MSIX_IRTS 32
185 #define PIC_IRT_PCIE_MSIX_0_INDEX 46
186 #define PIC_IRT_PCIE_MSIX_INDEX(num) ((num) + PIC_IRT_PCIE_MSIX_0_INDEX)
188 #define PIC_NUM_PCIE_LINK_IRTS 4
189 #define PIC_IRT_PCIE_LINK_0_INDEX 78
190 #define PIC_IRT_PCIE_LINK_1_INDEX 79
191 #define PIC_IRT_PCIE_LINK_2_INDEX 80
192 #define PIC_IRT_PCIE_LINK_3_INDEX 81
193 #define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX)
195 #define PIC_CLOCK_TIMER 7
197 #if !defined(LOCORE) && !defined(__ASSEMBLY__)
202 #define PIC_IRT_VALID 1
203 #define PIC_LOCAL_SCHEDULING 1
204 #define PIC_GLOBAL_SCHEDULING 0
206 #define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r)
207 #define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
208 #define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))
209 #define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
211 /* We use PIC on node 0 as a timer */
212 #define pic_timer_freq() nlm_get_pic_frequency(0)
214 /* IRT and h/w interrupt routines */
216 nlm_pic_read_irt(uint64_t base
, int irt_index
)
218 return nlm_read_pic_reg(base
, PIC_IRT(irt_index
));
222 nlm_set_irt_to_cpu(uint64_t base
, int irt
, int cpu
)
226 val
= nlm_read_pic_reg(base
, PIC_IRT(irt
));
227 /* clear cpuset and mask */
228 val
&= ~((0x7ull
<< 16) | 0xffff);
229 /* set DB, cpuset and cpumask */
230 val
|= (1 << 19) | ((cpu
>> 4) << 16) | (1 << (cpu
& 0xf));
231 nlm_write_pic_reg(base
, PIC_IRT(irt
), val
);
235 nlm_pic_write_irt(uint64_t base
, int irt_num
, int en
, int nmi
,
236 int sch
, int vec
, int dt
, int db
, int dte
)
240 val
= (((uint64_t)en
& 0x1) << 31) | ((nmi
& 0x1) << 29) |
241 ((sch
& 0x1) << 28) | ((vec
& 0x3f) << 20) |
242 ((dt
& 0x1) << 19) | ((db
& 0x7) << 16) |
245 nlm_write_pic_reg(base
, PIC_IRT(irt_num
), val
);
249 nlm_pic_write_irt_direct(uint64_t base
, int irt_num
, int en
, int nmi
,
250 int sch
, int vec
, int cpu
)
252 nlm_pic_write_irt(base
, irt_num
, en
, nmi
, sch
, vec
, 1,
253 (cpu
>> 4), /* thread group */
254 1 << (cpu
& 0xf)); /* thread mask */
257 static inline uint64_t
258 nlm_pic_read_timer(uint64_t base
, int timer
)
260 return nlm_read_pic_reg(base
, PIC_TIMER_COUNT(timer
));
263 static inline uint32_t
264 nlm_pic_read_timer32(uint64_t base
, int timer
)
266 return (uint32_t)nlm_read_pic_reg(base
, PIC_TIMER_COUNT(timer
));
270 nlm_pic_write_timer(uint64_t base
, int timer
, uint64_t value
)
272 nlm_write_pic_reg(base
, PIC_TIMER_COUNT(timer
), value
);
276 nlm_pic_set_timer(uint64_t base
, int timer
, uint64_t value
, int irq
, int cpu
)
278 uint64_t pic_ctrl
= nlm_read_pic_reg(base
, PIC_CTRL
);
282 nlm_write_pic_reg(base
, PIC_TIMER_MAXVAL(timer
), value
);
283 nlm_pic_write_irt_direct(base
, PIC_IRT_TIMER_INDEX(timer
),
286 /* enable the timer */
287 pic_ctrl
|= (1 << (PIC_CTRL_STE
+ timer
));
288 nlm_write_pic_reg(base
, PIC_CTRL
, pic_ctrl
);
292 nlm_pic_enable_irt(uint64_t base
, int irt
)
296 reg
= nlm_read_pic_reg(base
, PIC_IRT(irt
));
297 nlm_write_pic_reg(base
, PIC_IRT(irt
), reg
| (1u << 31));
301 nlm_pic_disable_irt(uint64_t base
, int irt
)
305 reg
= nlm_read_pic_reg(base
, PIC_IRT(irt
));
306 nlm_write_pic_reg(base
, PIC_IRT(irt
), reg
& ~((uint64_t)1 << 31));
310 nlm_pic_send_ipi(uint64_t base
, int hwt
, int irq
, int nmi
)
314 ipi
= ((uint64_t)nmi
<< 31) | (irq
<< 20);
315 ipi
|= ((hwt
>> 4) << 16) | (1 << (hwt
& 0xf)); /* cpuset and mask */
316 nlm_write_pic_reg(base
, PIC_IPI_CTL
, ipi
);
320 nlm_pic_ack(uint64_t base
, int irt_num
)
322 nlm_write_pic_reg(base
, PIC_INT_ACK
, irt_num
);
324 /* Ack the Status register for Watchdog & System timers */
326 nlm_write_pic_reg(base
, PIC_STATUS
, (1 << irt_num
));
330 nlm_pic_init_irt(uint64_t base
, int irt
, int irq
, int hwt
, int en
)
332 nlm_pic_write_irt_direct(base
, irt
, en
, 0, 0, irq
, hwt
);
335 int nlm_irq_to_irt(int irq
);
337 #endif /* __ASSEMBLY__ */
338 #endif /* _NLM_HAL_PIC_H */