arch/mips/include/asm/octeon/octeon.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2004-2008 Cavium Networks
   7  */
   8 #ifndef __ASM_OCTEON_OCTEON_H
   9 #define __ASM_OCTEON_OCTEON_H
  10
  11 #include <asm/octeon/cvmx.h>
  12 #include <asm/bitfield.h>
  13
  14 extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size,
  15                                                 uint64_t alignment,
  16                                                 uint64_t min_addr,
  17                                                 uint64_t max_addr,
  18                                                 int do_locking);
  19 extern void *octeon_bootmem_alloc(uint64_t size, uint64_t alignment,
  20                                   int do_locking);
  21 extern void *octeon_bootmem_alloc_range(uint64_t size, uint64_t alignment,
  22                                         uint64_t min_addr, uint64_t max_addr,
  23                                         int do_locking);
  24 extern void *octeon_bootmem_alloc_named(uint64_t size, uint64_t alignment,
  25                                         char *name);
  26 extern void *octeon_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
  27                                               uint64_t max_addr, uint64_t align,
  28                                               char *name);
  29 extern void *octeon_bootmem_alloc_named_address(uint64_t size, uint64_t address,
  30                                                 char *name);
  31 extern int octeon_bootmem_free_named(char *name);
  32 extern void octeon_bootmem_lock(void);
  33 extern void octeon_bootmem_unlock(void);
  34
  35 extern int octeon_is_simulation(void);
  36 extern int octeon_is_pci_host(void);
  37 extern int octeon_usb_is_ref_clk(void);
  38 extern uint64_t octeon_get_clock_rate(void);
  39 extern u64 octeon_get_io_clock_rate(void);
  40 extern const char *octeon_board_type_string(void);
  41 extern const char *octeon_get_pci_interrupts(void);
  42 extern int octeon_get_southbridge_interrupt(void);
  43 extern int octeon_get_boot_coremask(void);
  44 extern int octeon_get_boot_num_arguments(void);
  45 extern const char *octeon_get_boot_argument(int arg);
  46 extern void octeon_hal_setup_reserved32(void);
  47 extern void octeon_user_io_init(void);
  48
  49 extern void octeon_init_cvmcount(void);
  50 extern void octeon_setup_delays(void);
  51 extern void octeon_io_clk_delay(unsigned long);
  52
  53 #define OCTEON_ARGV_MAX_ARGS    64
  54 #define OCTOEN_SERIAL_LEN       20
  55
  56 struct octeon_boot_descriptor {
  57 #ifdef __BIG_ENDIAN_BITFIELD
  58         /* Start of block referenced by assembly code - do not change! */
  59         uint32_t desc_version;
  60         uint32_t desc_size;
  61         uint64_t stack_top;
  62         uint64_t heap_base;
  63         uint64_t heap_end;
  64         /* Only used by bootloader */
  65         uint64_t entry_point;
  66         uint64_t desc_vaddr;
  67         /* End of This block referenced by assembly code - do not change! */
  68         uint32_t exception_base_addr;
  69         uint32_t stack_size;
  70         uint32_t heap_size;
  71         /* Argc count for application. */
  72         uint32_t argc;
  73         uint32_t argv[OCTEON_ARGV_MAX_ARGS];
  74
  75 #define  BOOT_FLAG_INIT_CORE            (1 << 0)
  76 #define  OCTEON_BL_FLAG_DEBUG           (1 << 1)
  77 #define  OCTEON_BL_FLAG_NO_MAGIC        (1 << 2)
  78         /* If set, use uart1 for console */
  79 #define  OCTEON_BL_FLAG_CONSOLE_UART1   (1 << 3)
  80         /* If set, use PCI console */
  81 #define  OCTEON_BL_FLAG_CONSOLE_PCI     (1 << 4)
  82         /* Call exit on break on serial port */
  83 #define  OCTEON_BL_FLAG_BREAK           (1 << 5)
  84
  85         uint32_t flags;
  86         uint32_t core_mask;
  87         /* DRAM size in megabyes. */
  88         uint32_t dram_size;
  89         /* physical address of free memory descriptor block. */
  90         uint32_t phy_mem_desc_addr;
  91         /* used to pass flags from app to debugger. */
  92         uint32_t debugger_flags_base_addr;
  93         /* CPU clock speed, in hz. */
  94         uint32_t eclock_hz;
  95         /* DRAM clock speed, in hz. */
  96         uint32_t dclock_hz;
  97         /* SPI4 clock in hz. */
  98         uint32_t spi_clock_hz;
  99         uint16_t board_type;
 100         uint8_t board_rev_major;
 101         uint8_t board_rev_minor;
 102         uint16_t chip_type;
 103         uint8_t chip_rev_major;
 104         uint8_t chip_rev_minor;
 105         char board_serial_number[OCTOEN_SERIAL_LEN];
 106         uint8_t mac_addr_base[6];
 107         uint8_t mac_addr_count;
 108         uint64_t cvmx_desc_vaddr;
 109 #else
 110         uint32_t desc_size;
 111         uint32_t desc_version;
 112         uint64_t stack_top;
 113         uint64_t heap_base;
 114         uint64_t heap_end;
 115         /* Only used by bootloader */
 116         uint64_t entry_point;
 117         uint64_t desc_vaddr;
 118         /* End of This block referenced by assembly code - do not change! */
 119         uint32_t stack_size;
 120         uint32_t exception_base_addr;
 121         uint32_t argc;
 122         uint32_t heap_size;
 123         /*
 124          * Argc count for application.
 125          * Warning low bit scrambled in little-endian.
 126          */
 127         uint32_t argv[OCTEON_ARGV_MAX_ARGS];
 128
 129 #define  BOOT_FLAG_INIT_CORE            (1 << 0)
 130 #define  OCTEON_BL_FLAG_DEBUG           (1 << 1)
 131 #define  OCTEON_BL_FLAG_NO_MAGIC        (1 << 2)
 132         /* If set, use uart1 for console */
 133 #define  OCTEON_BL_FLAG_CONSOLE_UART1   (1 << 3)
 134         /* If set, use PCI console */
 135 #define  OCTEON_BL_FLAG_CONSOLE_PCI     (1 << 4)
 136         /* Call exit on break on serial port */
 137 #define  OCTEON_BL_FLAG_BREAK           (1 << 5)
 138
 139         uint32_t core_mask;
 140         uint32_t flags;
 141         /* physical address of free memory descriptor block. */
 142         uint32_t phy_mem_desc_addr;
 143         /* DRAM size in megabyes. */
 144         uint32_t dram_size;
 145         /* CPU clock speed, in hz. */
 146         uint32_t eclock_hz;
 147         /* used to pass flags from app to debugger. */
 148         uint32_t debugger_flags_base_addr;
 149         /* SPI4 clock in hz. */
 150         uint32_t spi_clock_hz;
 151         /* DRAM clock speed, in hz. */
 152         uint32_t dclock_hz;
 153         uint8_t chip_rev_minor;
 154         uint8_t chip_rev_major;
 155         uint16_t chip_type;
 156         uint8_t board_rev_minor;
 157         uint8_t board_rev_major;
 158         uint16_t board_type;
 159
 160         uint64_t unused1[4]; /* Not even filled in by bootloader. */
 161
 162         uint64_t cvmx_desc_vaddr;
 163 #endif
 164 };
 165
 166 union octeon_cvmemctl {
 167         uint64_t u64;
 168         struct {
 169                 /* RO 1 = BIST fail, 0 = BIST pass */
 170                 __BITFIELD_FIELD(uint64_t tlbbist:1,
 171                 /* RO 1 = BIST fail, 0 = BIST pass */
 172                 __BITFIELD_FIELD(uint64_t l1cbist:1,
 173                 /* RO 1 = BIST fail, 0 = BIST pass */
 174                 __BITFIELD_FIELD(uint64_t l1dbist:1,
 175                 /* RO 1 = BIST fail, 0 = BIST pass */
 176                 __BITFIELD_FIELD(uint64_t dcmbist:1,
 177                 /* RO 1 = BIST fail, 0 = BIST pass */
 178                 __BITFIELD_FIELD(uint64_t ptgbist:1,
 179                 /* RO 1 = BIST fail, 0 = BIST pass */
 180                 __BITFIELD_FIELD(uint64_t wbfbist:1,
 181                 /* Reserved */
 182                 __BITFIELD_FIELD(uint64_t reserved:17,
 183                 /* OCTEON II - TLB replacement policy: 0 = bitmask LRU; 1 = NLU.
 184                  * This field selects between the TLB replacement policies:
 185                  * bitmask LRU or NLU. Bitmask LRU maintains a mask of
 186                  * recently used TLB entries and avoids them as new entries
 187                  * are allocated. NLU simply guarantees that the next
 188                  * allocation is not the last used TLB entry. */
 189                 __BITFIELD_FIELD(uint64_t tlbnlu:1,
 190                 /* OCTEON II - Selects the bit in the counter used for
 191                  * releasing a PAUSE. This counter trips every 2(8+PAUSETIME)
 192                  * cycles. If not already released, the cnMIPS II core will
 193                  * always release a given PAUSE instruction within
 194                  * 2(8+PAUSETIME). If the counter trip happens to line up,
 195                  * the cnMIPS II core may release the PAUSE instantly. */
 196                 __BITFIELD_FIELD(uint64_t pausetime:3,
 197                 /* OCTEON II - This field is an extension of
 198                  * CvmMemCtl[DIDTTO] */
 199                 __BITFIELD_FIELD(uint64_t didtto2:1,
 200                 /* R/W If set, marked write-buffer entries time out
 201                  * the same as as other entries; if clear, marked
 202                  * write-buffer entries use the maximum timeout. */
 203                 __BITFIELD_FIELD(uint64_t dismarkwblongto:1,
 204                 /* R/W If set, a merged store does not clear the
 205                  * write-buffer entry timeout state. */
 206                 __BITFIELD_FIELD(uint64_t dismrgclrwbto:1,
 207                 /* R/W Two bits that are the MSBs of the resultant
 208                  * CVMSEG LM word location for an IOBDMA. The other 8
 209                  * bits come from the SCRADDR field of the IOBDMA. */
 210                 __BITFIELD_FIELD(uint64_t iobdmascrmsb:2,
 211                 /* R/W If set, SYNCWS and SYNCS only order marked
 212                  * stores; if clear, SYNCWS and SYNCS only order
 213                  * unmarked stores. SYNCWSMARKED has no effect when
 214                  * DISSYNCWS is set. */
 215                 __BITFIELD_FIELD(uint64_t syncwsmarked:1,
 216                 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as
 217                  * SYNC. */
 218                 __BITFIELD_FIELD(uint64_t dissyncws:1,
 219                 /* R/W If set, no stall happens on write buffer
 220                  * full. */
 221                 __BITFIELD_FIELD(uint64_t diswbfst:1,
 222                 /* R/W If set (and SX set), supervisor-level
 223                  * loads/stores can use XKPHYS addresses with
 224                  * VA<48>==0 */
 225                 __BITFIELD_FIELD(uint64_t xkmemenas:1,
 226                 /* R/W If set (and UX set), user-level loads/stores
 227                  * can use XKPHYS addresses with VA<48>==0 */
 228                 __BITFIELD_FIELD(uint64_t xkmemenau:1,
 229                 /* R/W If set (and SX set), supervisor-level
 230                  * loads/stores can use XKPHYS addresses with
 231                  * VA<48>==1 */
 232                 __BITFIELD_FIELD(uint64_t xkioenas:1,
 233                 /* R/W If set (and UX set), user-level loads/stores
 234                  * can use XKPHYS addresses with VA<48>==1 */
 235                 __BITFIELD_FIELD(uint64_t xkioenau:1,
 236                 /* R/W If set, all stores act as SYNCW (NOMERGE must
 237                  * be set when this is set) RW, reset to 0. */
 238                 __BITFIELD_FIELD(uint64_t allsyncw:1,
 239                 /* R/W If set, no stores merge, and all stores reach
 240                  * the coherent bus in order. */
 241                 __BITFIELD_FIELD(uint64_t nomerge:1,
 242                 /* R/W Selects the bit in the counter used for DID
 243                  * time-outs 0 = 231, 1 = 230, 2 = 229, 3 =
 244                  * 214. Actual time-out is between 1x and 2x this
 245                  * interval. For example, with DIDTTO=3, expiration
 246                  * interval is between 16K and 32K. */
 247                 __BITFIELD_FIELD(uint64_t didtto:2,
 248                 /* R/W If set, the (mem) CSR clock never turns off. */
 249                 __BITFIELD_FIELD(uint64_t csrckalwys:1,
 250                 /* R/W If set, mclk never turns off. */
 251                 __BITFIELD_FIELD(uint64_t mclkalwys:1,
 252                 /* R/W Selects the bit in the counter used for write
 253                  * buffer flush time-outs (WBFLT+11) is the bit
 254                  * position in an internal counter used to determine
 255                  * expiration. The write buffer expires between 1x and
 256                  * 2x this interval. For example, with WBFLT = 0, a
 257                  * write buffer expires between 2K and 4K cycles after
 258                  * the write buffer entry is allocated. */
 259                 __BITFIELD_FIELD(uint64_t wbfltime:3,
 260                 /* R/W If set, do not put Istream in the L2 cache. */
 261                 __BITFIELD_FIELD(uint64_t istrnol2:1,
 262                 /* R/W The write buffer threshold. */
 263                 __BITFIELD_FIELD(uint64_t wbthresh:4,
 264                 /* Reserved */
 265                 __BITFIELD_FIELD(uint64_t reserved2:2,
 266                 /* R/W If set, CVMSEG is available for loads/stores in
 267                  * kernel/debug mode. */
 268                 __BITFIELD_FIELD(uint64_t cvmsegenak:1,
 269                 /* R/W If set, CVMSEG is available for loads/stores in
 270                  * supervisor mode. */
 271                 __BITFIELD_FIELD(uint64_t cvmsegenas:1,
 272                 /* R/W If set, CVMSEG is available for loads/stores in
 273                  * user mode. */
 274                 __BITFIELD_FIELD(uint64_t cvmsegenau:1,
 275                 /* R/W Size of local memory in cache blocks, 54 (6912
 276                  * bytes) is max legal value. */
 277                 __BITFIELD_FIELD(uint64_t lmemsz:6,
 278                 ;)))))))))))))))))))))))))))))))))
 279         } s;
 280 };
 281
 282 extern void octeon_write_lcd(const char *s);
 283 extern void octeon_check_cpu_bist(void);
 284 extern int octeon_get_boot_uart(void);
 285
 286 struct uart_port;
 287 extern unsigned int octeon_serial_in(struct uart_port *, int);
 288 extern void octeon_serial_out(struct uart_port *, int, int);
 289
 290 /**
 291  * Write a 32bit value to the Octeon NPI register space
 292  *
 293  * @address: Address to write to
 294  * @val:     Value to write
 295  */
 296 static inline void octeon_npi_write32(uint64_t address, uint32_t val)
 297 {
 298         cvmx_write64_uint32(address ^ 4, val);
 299         cvmx_read64_uint32(address ^ 4);
 300 }
 301
 302 /* Octeon multiplier save/restore routines from octeon_switch.S */
 303 void octeon_mult_save(void);
 304 void octeon_mult_restore(void);
 305 void octeon_mult_save_end(void);
 306 void octeon_mult_restore_end(void);
 307 void octeon_mult_save3(void);
 308 void octeon_mult_save3_end(void);
 309 void octeon_mult_save2(void);
 310 void octeon_mult_save2_end(void);
 311 void octeon_mult_restore3(void);
 312 void octeon_mult_restore3_end(void);
 313 void octeon_mult_restore2(void);
 314 void octeon_mult_restore2_end(void);
 315
 316 /**
 317  * Read a 32bit value from the Octeon NPI register space
 318  *
 319  * @address: Address to read
 320  * Returns The result
 321  */
 322 static inline uint32_t octeon_npi_read32(uint64_t address)
 323 {
 324         return cvmx_read64_uint32(address ^ 4);
 325 }
 326
 327 extern struct cvmx_bootinfo *octeon_bootinfo;
 328
 329 extern uint64_t octeon_bootloader_entry_addr;
 330
 331 extern void (*octeon_irq_setup_secondary)(void);
 332
 333 typedef void (*octeon_irq_ip4_handler_t)(void);
 334 void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t);
 335
 336 extern void octeon_fixup_irqs(void);
 337
 338 extern struct semaphore octeon_bootbus_sem;
 339
 340 #endif /* __ASM_OCTEON_OCTEON_H */