arch/mips/include/asm/processor.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994 Waldorf GMBH
   7  * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
   8  * Copyright (C) 1996 Paul M. Antoine
   9  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  10  */
  11 #ifndef _ASM_PROCESSOR_H
  12 #define _ASM_PROCESSOR_H
  13
  14 #include <linux/cpumask.h>
  15 #include <linux/threads.h>
  16
  17 #include <asm/cachectl.h>
  18 #include <asm/cpu.h>
  19 #include <asm/cpu-info.h>
  20 #include <asm/mipsregs.h>
  21 #include <asm/prefetch.h>
  22
  23 /*
  24  * Return current * instruction pointer ("program counter").
  25  */
  26 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
  27
  28 /*
  29  * System setup and hardware flags..
  30  */
  31
  32 extern unsigned int vced_count, vcei_count;
  33
  34 /*
  35  * MIPS does have an arch_pick_mmap_layout()
  36  */
  37 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
  38
  39 /*
  40  * A special page (the vdso) is mapped into all processes at the very
  41  * top of the virtual memory space.
  42  */
  43 #define SPECIAL_PAGES_SIZE PAGE_SIZE
  44
  45 #ifdef CONFIG_32BIT
  46 #ifdef CONFIG_KVM_GUEST
  47 /* User space process size is limited to 1GB in KVM Guest Mode */
  48 #define TASK_SIZE       0x3fff8000UL
  49 #else
  50 /*
  51  * User space process size: 2GB. This is hardcoded into a few places,
  52  * so don't change it unless you know what you are doing.
  53  */
  54 #define TASK_SIZE       0x7fff8000UL
  55 #endif
  56
  57 #ifdef __KERNEL__
  58 #define STACK_TOP_MAX   TASK_SIZE
  59 #endif
  60
  61 #define TASK_IS_32BIT_ADDR 1
  62
  63 #endif
  64
  65 #ifdef CONFIG_64BIT
  66 /*
  67  * User space process size: 1TB. This is hardcoded into a few places,
  68  * so don't change it unless you know what you are doing.  TASK_SIZE
  69  * is limited to 1TB by the R4000 architecture; R10000 and better can
  70  * support 16TB; the architectural reserve for future expansion is
  71  * 8192EB ...
  72  */
  73 #define TASK_SIZE32     0x7fff8000UL
  74 #define TASK_SIZE64     0x10000000000UL
  75 #define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
  76
  77 #ifdef __KERNEL__
  78 #define STACK_TOP_MAX   TASK_SIZE64
  79 #endif
  80
  81
  82 #define TASK_SIZE_OF(tsk)                                               \
  83         (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
  84
  85 #define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
  86
  87 #endif
  88
  89 #define STACK_TOP       ((TASK_SIZE & PAGE_MASK) - SPECIAL_PAGES_SIZE)
  90
  91 /*
  92  * This decides where the kernel will search for a free chunk of vm
  93  * space during mmap's.
  94  */
  95 #define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
  96
  97
  98 #define NUM_FPU_REGS    32
  99 #define FPU_REG_WIDTH   64
 100
 101 union fpureg {
 102         __u32   val32[FPU_REG_WIDTH / 32];
 103         __u64   val64[FPU_REG_WIDTH / 64];
 104 };
 105
 106 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 107 # define FPR_IDX(width, idx)    (idx)
 108 #else
 109 # define FPR_IDX(width, idx)    ((FPU_REG_WIDTH / (width)) - 1 - (idx))
 110 #endif
 111
 112 #define BUILD_FPR_ACCESS(width) \
 113 static inline u##width get_fpr##width(union fpureg *fpr, unsigned idx)  \
 114 {                                                                       \
 115         return fpr->val##width[FPR_IDX(width, idx)];                    \
 116 }                                                                       \
 117                                                                         \
 118 static inline void set_fpr##width(union fpureg *fpr, unsigned idx,      \
 119                                   u##width val)                         \
 120 {                                                                       \
 121         fpr->val##width[FPR_IDX(width, idx)] = val;                     \
 122 }
 123
 124 BUILD_FPR_ACCESS(32)
 125 BUILD_FPR_ACCESS(64)
 126
 127 /*
 128  * It would be nice to add some more fields for emulator statistics, but there
 129  * are a number of fixed offsets in offset.h and elsewhere that would have to
 130  * be recalculated by hand.  So the additional information will be private to
 131  * the FPU emulator for now.  See asm-mips/fpu_emulator.h.
 132  */
 133
 134 struct mips_fpu_struct {
 135         union fpureg    fpr[NUM_FPU_REGS];
 136         unsigned int    fcr31;
 137 };
 138
 139 #define NUM_DSP_REGS   6
 140
 141 typedef __u32 dspreg_t;
 142
 143 struct mips_dsp_state {
 144         dspreg_t        dspr[NUM_DSP_REGS];
 145         unsigned int    dspcontrol;
 146 };
 147
 148 #define INIT_CPUMASK { \
 149         {0,} \
 150 }
 151
 152 struct mips3264_watch_reg_state {
 153         /* The width of watchlo is 32 in a 32 bit kernel and 64 in a
 154            64 bit kernel.  We use unsigned long as it has the same
 155            property. */
 156         unsigned long watchlo[NUM_WATCH_REGS];
 157         /* Only the mask and IRW bits from watchhi. */
 158         u16 watchhi[NUM_WATCH_REGS];
 159 };
 160
 161 union mips_watch_reg_state {
 162         struct mips3264_watch_reg_state mips3264;
 163 };
 164
 165 #if defined(CONFIG_CPU_CAVIUM_OCTEON)
 166
 167 struct octeon_cop2_state {
 168         /* DMFC2 rt, 0x0201 */
 169         unsigned long   cop2_crc_iv;
 170         /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
 171         unsigned long   cop2_crc_length;
 172         /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
 173         unsigned long   cop2_crc_poly;
 174         /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
 175         unsigned long   cop2_llm_dat[2];
 176        /* DMFC2 rt, 0x0084 */
 177         unsigned long   cop2_3des_iv;
 178         /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
 179         unsigned long   cop2_3des_key[3];
 180         /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
 181         unsigned long   cop2_3des_result;
 182         /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
 183         unsigned long   cop2_aes_inp0;
 184         /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
 185         unsigned long   cop2_aes_iv[2];
 186         /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
 187          * rt, 0x0107 */
 188         unsigned long   cop2_aes_key[4];
 189         /* DMFC2 rt, 0x0110 */
 190         unsigned long   cop2_aes_keylen;
 191         /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
 192         unsigned long   cop2_aes_result[2];
 193         /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
 194          * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
 195          * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
 196          * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
 197          * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
 198         unsigned long   cop2_hsh_datw[15];
 199         /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
 200          * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
 201          * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
 202         unsigned long   cop2_hsh_ivw[8];
 203         /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
 204         unsigned long   cop2_gfm_mult[2];
 205         /* DMFC2 rt, 0x025E - Pass2 */
 206         unsigned long   cop2_gfm_poly;
 207         /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
 208         unsigned long   cop2_gfm_result[2];
 209 };
 210 #define COP2_INIT                                               \
 211         .cp2                    = {0,},
 212
 213 struct octeon_cvmseg_state {
 214         unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
 215                             [cpu_dcache_line_size() / sizeof(unsigned long)];
 216 };
 217
 218 #elif defined(CONFIG_CPU_XLP)
 219 struct nlm_cop2_state {
 220         u64     rx[4];
 221         u64     tx[4];
 222         u32     tx_msg_status;
 223         u32     rx_msg_status;
 224 };
 225
 226 #define COP2_INIT                                               \
 227         .cp2                    = {{0}, {0}, 0, 0},
 228 #else
 229 #define COP2_INIT
 230 #endif
 231
 232 typedef struct {
 233         unsigned long seg;
 234 } mm_segment_t;
 235
 236 #define ARCH_MIN_TASKALIGN      8
 237
 238 struct mips_abi;
 239
 240 /*
 241  * If you change thread_struct remember to change the #defines below too!
 242  */
 243 struct thread_struct {
 244         /* Saved main processor registers. */
 245         unsigned long reg16;
 246         unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
 247         unsigned long reg29, reg30, reg31;
 248
 249         /* Saved cp0 stuff. */
 250         unsigned long cp0_status;
 251
 252         /* Saved fpu/fpu emulator stuff. */
 253         struct mips_fpu_struct fpu;
 254 #ifdef CONFIG_MIPS_MT_FPAFF
 255         /* Emulated instruction count */
 256         unsigned long emulated_fp;
 257         /* Saved per-thread scheduler affinity mask */
 258         cpumask_t user_cpus_allowed;
 259 #endif /* CONFIG_MIPS_MT_FPAFF */
 260
 261         /* Saved state of the DSP ASE, if available. */
 262         struct mips_dsp_state dsp;
 263
 264         /* Saved watch register state, if available. */
 265         union mips_watch_reg_state watch;
 266
 267         /* Other stuff associated with the thread. */
 268         unsigned long cp0_badvaddr;     /* Last user fault */
 269         unsigned long cp0_baduaddr;     /* Last kernel fault accessing USEG */
 270         unsigned long error_code;
 271 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 272         struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
 273         struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
 274 #endif
 275 #ifdef CONFIG_CPU_XLP
 276         struct nlm_cop2_state cp2;
 277 #endif
 278         struct mips_abi *abi;
 279 };
 280
 281 #ifdef CONFIG_MIPS_MT_FPAFF
 282 #define FPAFF_INIT                                              \
 283         .emulated_fp                    = 0,                    \
 284         .user_cpus_allowed              = INIT_CPUMASK,
 285 #else
 286 #define FPAFF_INIT
 287 #endif /* CONFIG_MIPS_MT_FPAFF */
 288
 289 #define INIT_THREAD  {                                          \
 290         /*                                                      \
 291          * Saved main processor registers                       \
 292          */                                                     \
 293         .reg16                  = 0,                            \
 294         .reg17                  = 0,                            \
 295         .reg18                  = 0,                            \
 296         .reg19                  = 0,                            \
 297         .reg20                  = 0,                            \
 298         .reg21                  = 0,                            \
 299         .reg22                  = 0,                            \
 300         .reg23                  = 0,                            \
 301         .reg29                  = 0,                            \
 302         .reg30                  = 0,                            \
 303         .reg31                  = 0,                            \
 304         /*                                                      \
 305          * Saved cp0 stuff                                      \
 306          */                                                     \
 307         .cp0_status             = 0,                            \
 308         /*                                                      \
 309          * Saved FPU/FPU emulator stuff                         \
 310          */                                                     \
 311         .fpu                    = {                             \
 312                 .fpr            = {{{0,},},},                   \
 313                 .fcr31          = 0,                            \
 314         },                                                      \
 315         /*                                                      \
 316          * FPU affinity state (null if not FPAFF)               \
 317          */                                                     \
 318         FPAFF_INIT                                              \
 319         /*                                                      \
 320          * Saved DSP stuff                                      \
 321          */                                                     \
 322         .dsp                    = {                             \
 323                 .dspr           = {0, },                        \
 324                 .dspcontrol     = 0,                            \
 325         },                                                      \
 326         /*                                                      \
 327          * saved watch register stuff                           \
 328          */                                                     \
 329         .watch = {{{0,},},},                                    \
 330         /*                                                      \
 331          * Other stuff associated with the process              \
 332          */                                                     \
 333         .cp0_badvaddr           = 0,                            \
 334         .cp0_baduaddr           = 0,                            \
 335         .error_code             = 0,                            \
 336         /*                                                      \
 337          * Platform specific cop2 registers(null if no COP2)    \
 338          */                                                     \
 339         COP2_INIT                                               \
 340 }
 341
 342 struct task_struct;
 343
 344 /* Free all resources held by a thread. */
 345 #define release_thread(thread) do { } while(0)
 346
 347 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 348
 349 /*
 350  * Do necessary setup to start up a newly executed thread.
 351  */
 352 extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
 353
 354 unsigned long get_wchan(struct task_struct *p);
 355
 356 #define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
 357                          THREAD_SIZE - 32 - sizeof(struct pt_regs))
 358 #define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
 359 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
 360 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
 361 #define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
 362
 363 #define cpu_relax()     barrier()
 364
 365 /*
 366  * Return_address is a replacement for __builtin_return_address(count)
 367  * which on certain architectures cannot reasonably be implemented in GCC
 368  * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386).
 369  * Note that __builtin_return_address(x>=1) is forbidden because GCC
 370  * aborts compilation on some CPUs.  It's simply not possible to unwind
 371  * some CPU's stackframes.
 372  *
 373  * __builtin_return_address works only for non-leaf functions.  We avoid the
 374  * overhead of a function call by forcing the compiler to save the return
 375  * address register on the stack.
 376  */
 377 #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
 378
 379 #ifdef CONFIG_CPU_HAS_PREFETCH
 380
 381 #define ARCH_HAS_PREFETCH
 382 #define prefetch(x) __builtin_prefetch((x), 0, 1)
 383
 384 #define ARCH_HAS_PREFETCHW
 385 #define prefetchw(x) __builtin_prefetch((x), 1, 1)
 386
 387 /*
 388  * See Documentation/scheduler/sched-arch.txt; prevents deadlock on SMP
 389  * systems.
 390  */
 391 #define __ARCH_WANT_UNLOCKED_CTXSW
 392
 393 #endif
 394
 395 #endif /* _ASM_PROCESSOR_H */