arch/mips/include/asm/tlb.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __ASM_TLB_H
   3 #define __ASM_TLB_H
   4
   5 #include <asm/cpu-features.h>
   6 #include <asm/mipsregs.h>
   7
   8 /*
   9  * MIPS doesn't need any special per-pte or per-vma handling, except
  10  * we need to flush cache for area to be unmapped.
  11  */
  12 #define tlb_start_vma(tlb, vma)                                 \
  13         do {                                                    \
  14                 if (!tlb->fullmm)                               \
  15                         flush_cache_range(vma, vma->vm_start, vma->vm_end); \
  16         }  while (0)
  17 #define tlb_end_vma(tlb, vma) do { } while (0)
  18 #define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
  19
  20 /*
  21  * .. because we flush the whole mm when it fills up.
  22  */
  23 #define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
  24
  25 #define _UNIQUE_ENTRYHI(base, idx)                                      \
  26                 (((base) + ((idx) << (PAGE_SHIFT + 1))) |               \
  27                  (cpu_has_tlbinv ? MIPS_ENTRYHI_EHINV : 0))
  28 #define UNIQUE_ENTRYHI(idx)             _UNIQUE_ENTRYHI(CKSEG0, idx)
  29 #define UNIQUE_GUEST_ENTRYHI(idx)       _UNIQUE_ENTRYHI(CKSEG1, idx)
  30
  31 static inline unsigned int num_wired_entries(void)
  32 {
  33         unsigned int wired = read_c0_wired();
  34
  35         if (cpu_has_mips_r6)
  36                 wired &= MIPSR6_WIRED_WIRED;
  37
  38         return wired;
  39 }
  40
  41 #include <asm-generic/tlb.h>
  42
  43 #endif /* __ASM_TLB_H */