arch/mips/include/uapi/asm/kvm.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   7  * Copyright (C) 2013 Cavium, Inc.
   8  * Authors: Sanjay Lal <sanjayl@kymasys.com>
   9  */
  10
  11 #ifndef __LINUX_KVM_MIPS_H
  12 #define __LINUX_KVM_MIPS_H
  13
  14 #include <linux/types.h>
  15
  16 /*
  17  * KVM MIPS specific structures and definitions.
  18  *
  19  * Some parts derived from the x86 version of this file.
  20  */
  21
  22 #define __KVM_HAVE_READONLY_MEM
  23
  24 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
  25
  26 /*
  27  * for KVM_GET_REGS and KVM_SET_REGS
  28  *
  29  * If Config[AT] is zero (32-bit CPU), the register contents are
  30  * stored in the lower 32-bits of the struct kvm_regs fields and sign
  31  * extended to 64-bits.
  32  */
  33 struct kvm_regs {
  34         /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
  35         __u64 gpr[32];
  36         __u64 hi;
  37         __u64 lo;
  38         __u64 pc;
  39 };
  40
  41 /*
  42  * for KVM_GET_FPU and KVM_SET_FPU
  43  */
  44 struct kvm_fpu {
  45 };
  46
  47
  48 /*
  49  * For MIPS, we use KVM_SET_ONE_REG and KVM_GET_ONE_REG to access various
  50  * registers.  The id field is broken down as follows:
  51  *
  52  *  bits[63..52] - As per linux/kvm.h
  53  *  bits[51..32] - Must be zero.
  54  *  bits[31..16] - Register set.
  55  *
  56  * Register set = 0: GP registers from kvm_regs (see definitions below).
  57  *
  58  * Register set = 1: CP0 registers.
  59  *  bits[15..8]  - COP0 register set.
  60  *
  61  *  COP0 register set = 0: Main CP0 registers.
  62  *   bits[7..3]   - Register 'rd'  index.
  63  *   bits[2..0]   - Register 'sel' index.
  64  *
  65  *  COP0 register set = 1: MAARs.
  66  *   bits[7..0]   - MAAR index.
  67  *
  68  * Register set = 2: KVM specific registers (see definitions below).
  69  *
  70  * Register set = 3: FPU / MSA registers (see definitions below).
  71  *
  72  * Other sets registers may be added in the future.  Each set would
  73  * have its own identifier in bits[31..16].
  74  */
  75
  76 #define KVM_REG_MIPS_GP         (KVM_REG_MIPS | 0x0000000000000000ULL)
  77 #define KVM_REG_MIPS_CP0        (KVM_REG_MIPS | 0x0000000000010000ULL)
  78 #define KVM_REG_MIPS_KVM        (KVM_REG_MIPS | 0x0000000000020000ULL)
  79 #define KVM_REG_MIPS_FPU        (KVM_REG_MIPS | 0x0000000000030000ULL)
  80
  81
  82 /*
  83  * KVM_REG_MIPS_GP - General purpose registers from kvm_regs.
  84  */
  85
  86 #define KVM_REG_MIPS_R0         (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  0)
  87 #define KVM_REG_MIPS_R1         (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  1)
  88 #define KVM_REG_MIPS_R2         (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  2)
  89 #define KVM_REG_MIPS_R3         (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  3)
  90 #define KVM_REG_MIPS_R4         (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  4)
  91 #define KVM_REG_MIPS_R5         (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  5)
  92 #define KVM_REG_MIPS_R6         (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  6)
  93 #define KVM_REG_MIPS_R7         (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  7)
  94 #define KVM_REG_MIPS_R8         (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  8)
  95 #define KVM_REG_MIPS_R9         (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  9)
  96 #define KVM_REG_MIPS_R10        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 10)
  97 #define KVM_REG_MIPS_R11        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 11)
  98 #define KVM_REG_MIPS_R12        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 12)
  99 #define KVM_REG_MIPS_R13        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 13)
 100 #define KVM_REG_MIPS_R14        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 14)
 101 #define KVM_REG_MIPS_R15        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 15)
 102 #define KVM_REG_MIPS_R16        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 16)
 103 #define KVM_REG_MIPS_R17        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 17)
 104 #define KVM_REG_MIPS_R18        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 18)
 105 #define KVM_REG_MIPS_R19        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 19)
 106 #define KVM_REG_MIPS_R20        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 20)
 107 #define KVM_REG_MIPS_R21        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 21)
 108 #define KVM_REG_MIPS_R22        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 22)
 109 #define KVM_REG_MIPS_R23        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 23)
 110 #define KVM_REG_MIPS_R24        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 24)
 111 #define KVM_REG_MIPS_R25        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 25)
 112 #define KVM_REG_MIPS_R26        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 26)
 113 #define KVM_REG_MIPS_R27        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 27)
 114 #define KVM_REG_MIPS_R28        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 28)
 115 #define KVM_REG_MIPS_R29        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 29)
 116 #define KVM_REG_MIPS_R30        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 30)
 117 #define KVM_REG_MIPS_R31        (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 31)
 118
 119 #define KVM_REG_MIPS_HI         (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 32)
 120 #define KVM_REG_MIPS_LO         (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 33)
 121 #define KVM_REG_MIPS_PC         (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 34)
 122
 123
 124 /*
 125  * KVM_REG_MIPS_CP0 - Coprocessor 0 registers.
 126  */
 127
 128 #define KVM_REG_MIPS_MAAR       (KVM_REG_MIPS_CP0 | (1 << 8))
 129 #define KVM_REG_MIPS_CP0_MAAR(n)        (KVM_REG_MIPS_MAAR | \
 130                                          KVM_REG_SIZE_U64 | (n))
 131
 132
 133 /*
 134  * KVM_REG_MIPS_KVM - KVM specific control registers.
 135  */
 136
 137 /*
 138  * CP0_Count control
 139  * DC:    Set 0: Master disable CP0_Count and set COUNT_RESUME to now
 140  *        Set 1: Master re-enable CP0_Count with unchanged bias, handling timer
 141  *               interrupts since COUNT_RESUME
 142  *        This can be used to freeze the timer to get a consistent snapshot of
 143  *        the CP0_Count and timer interrupt pending state, while also resuming
 144  *        safely without losing time or guest timer interrupts.
 145  * Other: Reserved, do not change.
 146  */
 147 #define KVM_REG_MIPS_COUNT_CTL      (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 0)
 148 #define KVM_REG_MIPS_COUNT_CTL_DC       0x00000001
 149
 150 /*
 151  * CP0_Count resume monotonic nanoseconds
 152  * The monotonic nanosecond time of the last set of COUNT_CTL.DC (master
 153  * disable). Any reads and writes of Count related registers while
 154  * COUNT_CTL.DC=1 will appear to occur at this time. When COUNT_CTL.DC is
 155  * cleared again (master enable) any timer interrupts since this time will be
 156  * emulated.
 157  * Modifications to times in the future are rejected.
 158  */
 159 #define KVM_REG_MIPS_COUNT_RESUME   (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 1)
 160 /*
 161  * CP0_Count rate in Hz
 162  * Specifies the rate of the CP0_Count timer in Hz. Modifications occur without
 163  * discontinuities in CP0_Count.
 164  */
 165 #define KVM_REG_MIPS_COUNT_HZ       (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 2)
 166
 167
 168 /*
 169  * KVM_REG_MIPS_FPU - Floating Point and MIPS SIMD Architecture (MSA) registers.
 170  *
 171  *  bits[15..8]  - Register subset (see definitions below).
 172  *  bits[7..5]   - Must be zero.
 173  *  bits[4..0]   - Register number within register subset.
 174  */
 175
 176 #define KVM_REG_MIPS_FPR        (KVM_REG_MIPS_FPU | 0x0000000000000000ULL)
 177 #define KVM_REG_MIPS_FCR        (KVM_REG_MIPS_FPU | 0x0000000000000100ULL)
 178 #define KVM_REG_MIPS_MSACR      (KVM_REG_MIPS_FPU | 0x0000000000000200ULL)
 179
 180 /*
 181  * KVM_REG_MIPS_FPR - Floating point / Vector registers.
 182  */
 183 #define KVM_REG_MIPS_FPR_32(n)  (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U32  | (n))
 184 #define KVM_REG_MIPS_FPR_64(n)  (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U64  | (n))
 185 #define KVM_REG_MIPS_VEC_128(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U128 | (n))
 186
 187 /*
 188  * KVM_REG_MIPS_FCR - Floating point control registers.
 189  */
 190 #define KVM_REG_MIPS_FCR_IR     (KVM_REG_MIPS_FCR | KVM_REG_SIZE_U32 |  0)
 191 #define KVM_REG_MIPS_FCR_CSR    (KVM_REG_MIPS_FCR | KVM_REG_SIZE_U32 | 31)
 192
 193 /*
 194  * KVM_REG_MIPS_MSACR - MIPS SIMD Architecture (MSA) control registers.
 195  */
 196 #define KVM_REG_MIPS_MSA_IR      (KVM_REG_MIPS_MSACR | KVM_REG_SIZE_U32 |  0)
 197 #define KVM_REG_MIPS_MSA_CSR     (KVM_REG_MIPS_MSACR | KVM_REG_SIZE_U32 |  1)
 198
 199
 200 /*
 201  * KVM MIPS specific structures and definitions
 202  *
 203  */
 204 struct kvm_debug_exit_arch {
 205         __u64 epc;
 206 };
 207
 208 /* for KVM_SET_GUEST_DEBUG */
 209 struct kvm_guest_debug_arch {
 210 };
 211
 212 /* definition of registers in kvm_run */
 213 struct kvm_sync_regs {
 214 };
 215
 216 /* dummy definition */
 217 struct kvm_sregs {
 218 };
 219
 220 struct kvm_mips_interrupt {
 221         /* in */
 222         __u32 cpu;
 223         __u32 irq;
 224 };
 225
 226 #endif /* __LINUX_KVM_MIPS_H */