arch/mips/kernel/bmips_vec.S

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
   7  *
   8  * Reset/NMI/re-entry vectors for BMIPS processors
   9  */
  10
  11
  12 #include <asm/asm.h>
  13 #include <asm/asmmacro.h>
  14 #include <asm/cacheops.h>
  15 #include <asm/cpu.h>
  16 #include <asm/regdef.h>
  17 #include <asm/mipsregs.h>
  18 #include <asm/stackframe.h>
  19 #include <asm/addrspace.h>
  20 #include <asm/hazards.h>
  21 #include <asm/bmips.h>
  22
  23         .macro  BARRIER
  24         .set    mips32
  25         _ssnop
  26         _ssnop
  27         _ssnop
  28         .set    mips0
  29         .endm
  30
  31 /***********************************************************************
  32  * Alternate CPU1 startup vector for BMIPS4350
  33  *
  34  * On some systems the bootloader has already started CPU1 and configured
  35  * it to resume execution at 0x8000_0200 (!BEV IV vector) when it is
  36  * triggered by the SW1 interrupt.  If that is the case we try to move
  37  * it to a more convenient place: BMIPS_WARM_RESTART_VEC @ 0x8000_0380.
  38  ***********************************************************************/
  39
  40 LEAF(bmips_smp_movevec)
  41         la      k0, 1f
  42         li      k1, CKSEG1
  43         or      k0, k1
  44         jr      k0
  45
  46 1:
  47         /* clear IV, pending IPIs */
  48         mtc0    zero, CP0_CAUSE
  49
  50         /* re-enable IRQs to wait for SW1 */
  51         li      k0, ST0_IE | ST0_BEV | STATUSF_IP1
  52         mtc0    k0, CP0_STATUS
  53
  54         /* set up CPU1 CBR; move BASE to 0xa000_0000 */
  55         li      k0, 0xff400000
  56         mtc0    k0, $22, 6
  57         /* set up relocation vector address based on thread ID */
  58         mfc0    k1, $22, 3
  59         srl     k1, 16
  60         andi    k1, 0x8000
  61         or      k1, CKSEG1 | BMIPS_RELO_VECTOR_CONTROL_0
  62         or      k0, k1
  63         li      k1, 0xa0080000
  64         sw      k1, 0(k0)
  65
  66         /* wait here for SW1 interrupt from bmips_boot_secondary() */
  67         wait
  68
  69         la      k0, bmips_reset_nmi_vec
  70         li      k1, CKSEG1
  71         or      k0, k1
  72         jr      k0
  73 END(bmips_smp_movevec)
  74
  75 /***********************************************************************
  76  * Reset/NMI vector
  77  * For BMIPS processors that can relocate their exception vectors, this
  78  * entire function gets copied to 0x8000_0000.
  79  ***********************************************************************/
  80
  81 NESTED(bmips_reset_nmi_vec, PT_SIZE, sp)
  82         .set    push
  83         .set    noat
  84         .align  4
  85
  86 #ifdef CONFIG_SMP
  87         /* if the NMI bit is clear, assume this is a CPU1 reset instead */
  88         li      k1, (1 << 19)
  89         mfc0    k0, CP0_STATUS
  90         and     k0, k1
  91         beqz    k0, bmips_smp_entry
  92
  93 #if defined(CONFIG_CPU_BMIPS5000)
  94         mfc0    k0, CP0_PRID
  95         li      k1, PRID_IMP_BMIPS5000
  96         andi    k0, 0xff00
  97         bne     k0, k1, 1f
  98
  99         /* if we're not on core 0, this must be the SMP boot signal */
 100         li      k1, (3 << 25)
 101         mfc0    k0, $22
 102         and     k0, k1
 103         bnez    k0, bmips_smp_entry
 104 1:
 105 #endif /* CONFIG_CPU_BMIPS5000 */
 106 #endif /* CONFIG_SMP */
 107
 108         /* nope, it's just a regular NMI */
 109         SAVE_ALL
 110         move    a0, sp
 111
 112         /* clear EXL, ERL, BEV so that TLB refills still work */
 113         mfc0    k0, CP0_STATUS
 114         li      k1, ST0_ERL | ST0_EXL | ST0_BEV | ST0_IE
 115         or      k0, k1
 116         xor     k0, k1
 117         mtc0    k0, CP0_STATUS
 118         BARRIER
 119
 120         /* jump to the NMI handler function */
 121         la      k0, nmi_handler
 122         jr      k0
 123
 124         RESTORE_ALL
 125         .set    arch=r4000
 126         eret
 127
 128 /***********************************************************************
 129  * CPU1 reset vector (used for the initial boot only)
 130  * This is still part of bmips_reset_nmi_vec().
 131  ***********************************************************************/
 132
 133 #ifdef CONFIG_SMP
 134
 135 bmips_smp_entry:
 136
 137         /* set up CP0 STATUS; enable FPU */
 138         li      k0, 0x30000000
 139         mtc0    k0, CP0_STATUS
 140         BARRIER
 141
 142         /* set local CP0 CONFIG to make kseg0 cacheable, write-back */
 143         mfc0    k0, CP0_CONFIG
 144         ori     k0, 0x07
 145         xori    k0, 0x04
 146         mtc0    k0, CP0_CONFIG
 147
 148         mfc0    k0, CP0_PRID
 149         andi    k0, 0xff00
 150 #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
 151         li      k1, PRID_IMP_BMIPS43XX
 152         bne     k0, k1, 2f
 153
 154         /* initialize CPU1's local I-cache */
 155         li      k0, 0x80000000
 156         li      k1, 0x80010000
 157         mtc0    zero, $28
 158         mtc0    zero, $28, 1
 159         BARRIER
 160
 161 1:      cache   Index_Store_Tag_I, 0(k0)
 162         addiu   k0, 16
 163         bne     k0, k1, 1b
 164
 165         b       3f
 166 2:
 167 #endif /* CONFIG_CPU_BMIPS4350 || CONFIG_CPU_BMIPS4380 */
 168 #if defined(CONFIG_CPU_BMIPS5000)
 169         /* set exception vector base */
 170         li      k1, PRID_IMP_BMIPS5000
 171         bne     k0, k1, 3f
 172
 173         la      k0, ebase
 174         lw      k0, 0(k0)
 175         mtc0    k0, $15, 1
 176         BARRIER
 177 #endif /* CONFIG_CPU_BMIPS5000 */
 178 3:
 179         /* jump back to kseg0 in case we need to remap the kseg1 area */
 180         la      k0, 1f
 181         jr      k0
 182 1:
 183         la      k0, bmips_enable_xks01
 184         jalr    k0
 185
 186         /* use temporary stack to set up upper memory TLB */
 187         li      sp, BMIPS_WARM_RESTART_VEC
 188         la      k0, plat_wired_tlb_setup
 189         jalr    k0
 190
 191         /* switch to permanent stack and continue booting */
 192
 193         .global bmips_secondary_reentry
 194 bmips_secondary_reentry:
 195         la      k0, bmips_smp_boot_sp
 196         lw      sp, 0(k0)
 197         la      k0, bmips_smp_boot_gp
 198         lw      gp, 0(k0)
 199         la      k0, start_secondary
 200         jr      k0
 201
 202 #endif /* CONFIG_SMP */
 203
 204         .align  4
 205         .global bmips_reset_nmi_vec_end
 206 bmips_reset_nmi_vec_end:
 207
 208 END(bmips_reset_nmi_vec)
 209
 210         .set    pop
 211
 212 /***********************************************************************
 213  * CPU1 warm restart vector (used for second and subsequent boots).
 214  * Also used for S2 standby recovery (PM).
 215  * This entire function gets copied to (BMIPS_WARM_RESTART_VEC)
 216  ***********************************************************************/
 217
 218 LEAF(bmips_smp_int_vec)
 219
 220         .align  4
 221         mfc0    k0, CP0_STATUS
 222         ori     k0, 0x01
 223         xori    k0, 0x01
 224         mtc0    k0, CP0_STATUS
 225         eret
 226
 227         .align  4
 228         .global bmips_smp_int_vec_end
 229 bmips_smp_int_vec_end:
 230
 231 END(bmips_smp_int_vec)
 232
 233 /***********************************************************************
 234  * XKS01 support
 235  * Certain CPUs support extending kseg0 to 1024MB.
 236  ***********************************************************************/
 237
 238 LEAF(bmips_enable_xks01)
 239
 240 #if defined(CONFIG_XKS01)
 241         mfc0    t0, CP0_PRID
 242         andi    t2, t0, 0xff00
 243 #if defined(CONFIG_CPU_BMIPS4380)
 244         li      t1, PRID_IMP_BMIPS43XX
 245         bne     t2, t1, 1f
 246
 247         andi    t0, 0xff
 248         addiu   t1, t0, -PRID_REV_BMIPS4380_HI
 249         bgtz    t1, 2f
 250         addiu   t0, -PRID_REV_BMIPS4380_LO
 251         bltz    t0, 2f
 252
 253         mfc0    t0, $22, 3
 254         li      t1, 0x1ff0
 255         li      t2, (1 << 12) | (1 << 9)
 256         or      t0, t1
 257         xor     t0, t1
 258         or      t0, t2
 259         mtc0    t0, $22, 3
 260         BARRIER
 261         b       2f
 262 1:
 263 #endif /* CONFIG_CPU_BMIPS4380 */
 264 #if defined(CONFIG_CPU_BMIPS5000)
 265         li      t1, PRID_IMP_BMIPS5000
 266         bne     t2, t1, 2f
 267
 268         mfc0    t0, $22, 5
 269         li      t1, 0x01ff
 270         li      t2, (1 << 8) | (1 << 5)
 271         or      t0, t1
 272         xor     t0, t1
 273         or      t0, t2
 274         mtc0    t0, $22, 5
 275         BARRIER
 276 #endif /* CONFIG_CPU_BMIPS5000 */
 277 2:
 278 #endif /* defined(CONFIG_XKS01) */
 279
 280         jr      ra
 281
 282 END(bmips_enable_xks01)