2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
23 #include <asm/cpu-features.h>
24 #include <asm/cpu-type.h>
26 #include <asm/mipsregs.h>
27 #include <asm/mipsmtregs.h>
29 #include <asm/watch.h>
31 #include <asm/pgtable-bits.h>
32 #include <asm/spram.h>
33 #include <asm/uaccess.h>
35 /* Hardware capabilities */
36 unsigned int elf_hwcap __read_mostly
;
39 * Get the FPU Implementation/Revision.
41 static inline unsigned long cpu_get_fpu_id(void)
43 unsigned long tmp
, fpu_id
;
45 tmp
= read_c0_status();
46 __enable_fpu(FPU_AS_IS
);
47 fpu_id
= read_32bit_cp1_register(CP1_REVISION
);
53 * Check if the CPU has an external FPU.
55 static inline int __cpu_has_fpu(void)
57 return (cpu_get_fpu_id() & FPIR_IMP_MASK
) != FPIR_IMP_NONE
;
60 static inline unsigned long cpu_get_msa_id(void)
62 unsigned long status
, msa_id
;
64 status
= read_c0_status();
65 __enable_fpu(FPU_64BIT
);
67 msa_id
= read_msa_ir();
69 write_c0_status(status
);
74 * Determine the FCSR mask for FPU hardware.
76 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips
*c
)
78 unsigned long sr
, mask
, fcsr
, fcsr0
, fcsr1
;
81 mask
= FPU_CSR_ALL_X
| FPU_CSR_ALL_E
| FPU_CSR_ALL_S
| FPU_CSR_RM
;
83 sr
= read_c0_status();
84 __enable_fpu(FPU_AS_IS
);
87 write_32bit_cp1_register(CP1_STATUS
, fcsr0
);
88 fcsr0
= read_32bit_cp1_register(CP1_STATUS
);
91 write_32bit_cp1_register(CP1_STATUS
, fcsr1
);
92 fcsr1
= read_32bit_cp1_register(CP1_STATUS
);
94 write_32bit_cp1_register(CP1_STATUS
, fcsr
);
98 c
->fpu_msk31
= ~(fcsr0
^ fcsr1
) & ~mask
;
102 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
103 * supported by FPU hardware.
105 static void cpu_set_fpu_2008(struct cpuinfo_mips
*c
)
107 if (c
->isa_level
& (MIPS_CPU_ISA_M32R1
| MIPS_CPU_ISA_M64R1
|
108 MIPS_CPU_ISA_M32R2
| MIPS_CPU_ISA_M64R2
|
109 MIPS_CPU_ISA_M32R6
| MIPS_CPU_ISA_M64R6
)) {
110 unsigned long sr
, fir
, fcsr
, fcsr0
, fcsr1
;
112 sr
= read_c0_status();
113 __enable_fpu(FPU_AS_IS
);
115 fir
= read_32bit_cp1_register(CP1_REVISION
);
116 if (fir
& MIPS_FPIR_HAS2008
) {
117 fcsr
= read_32bit_cp1_register(CP1_STATUS
);
119 fcsr0
= fcsr
& ~(FPU_CSR_ABS2008
| FPU_CSR_NAN2008
);
120 write_32bit_cp1_register(CP1_STATUS
, fcsr0
);
121 fcsr0
= read_32bit_cp1_register(CP1_STATUS
);
123 fcsr1
= fcsr
| FPU_CSR_ABS2008
| FPU_CSR_NAN2008
;
124 write_32bit_cp1_register(CP1_STATUS
, fcsr1
);
125 fcsr1
= read_32bit_cp1_register(CP1_STATUS
);
127 write_32bit_cp1_register(CP1_STATUS
, fcsr
);
129 if (!(fcsr0
& FPU_CSR_NAN2008
))
130 c
->options
|= MIPS_CPU_NAN_LEGACY
;
131 if (fcsr1
& FPU_CSR_NAN2008
)
132 c
->options
|= MIPS_CPU_NAN_2008
;
134 if ((fcsr0
^ fcsr1
) & FPU_CSR_ABS2008
)
135 c
->fpu_msk31
&= ~FPU_CSR_ABS2008
;
137 c
->fpu_csr31
|= fcsr
& FPU_CSR_ABS2008
;
139 if ((fcsr0
^ fcsr1
) & FPU_CSR_NAN2008
)
140 c
->fpu_msk31
&= ~FPU_CSR_NAN2008
;
142 c
->fpu_csr31
|= fcsr
& FPU_CSR_NAN2008
;
144 c
->options
|= MIPS_CPU_NAN_LEGACY
;
149 c
->options
|= MIPS_CPU_NAN_LEGACY
;
154 * IEEE 754 conformance mode to use. Affects the NaN encoding and the
155 * ABS.fmt/NEG.fmt execution mode.
157 static enum { STRICT
, LEGACY
, STD2008
, RELAXED
} ieee754
= STRICT
;
160 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
161 * to support by the FPU emulator according to the IEEE 754 conformance
162 * mode selected. Note that "relaxed" straps the emulator so that it
163 * allows 2008-NaN binaries even for legacy processors.
165 static void cpu_set_nofpu_2008(struct cpuinfo_mips
*c
)
167 c
->options
&= ~(MIPS_CPU_NAN_2008
| MIPS_CPU_NAN_LEGACY
);
168 c
->fpu_csr31
&= ~(FPU_CSR_ABS2008
| FPU_CSR_NAN2008
);
169 c
->fpu_msk31
&= ~(FPU_CSR_ABS2008
| FPU_CSR_NAN2008
);
173 if (c
->isa_level
& (MIPS_CPU_ISA_M32R1
| MIPS_CPU_ISA_M64R1
|
174 MIPS_CPU_ISA_M32R2
| MIPS_CPU_ISA_M64R2
|
175 MIPS_CPU_ISA_M32R6
| MIPS_CPU_ISA_M64R6
)) {
176 c
->options
|= MIPS_CPU_NAN_2008
| MIPS_CPU_NAN_LEGACY
;
178 c
->options
|= MIPS_CPU_NAN_LEGACY
;
179 c
->fpu_msk31
|= FPU_CSR_ABS2008
| FPU_CSR_NAN2008
;
183 c
->options
|= MIPS_CPU_NAN_LEGACY
;
184 c
->fpu_msk31
|= FPU_CSR_ABS2008
| FPU_CSR_NAN2008
;
187 c
->options
|= MIPS_CPU_NAN_2008
;
188 c
->fpu_csr31
|= FPU_CSR_ABS2008
| FPU_CSR_NAN2008
;
189 c
->fpu_msk31
|= FPU_CSR_ABS2008
| FPU_CSR_NAN2008
;
192 c
->options
|= MIPS_CPU_NAN_2008
| MIPS_CPU_NAN_LEGACY
;
198 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
199 * according to the "ieee754=" parameter.
201 static void cpu_set_nan_2008(struct cpuinfo_mips
*c
)
205 mips_use_nan_legacy
= !!cpu_has_nan_legacy
;
206 mips_use_nan_2008
= !!cpu_has_nan_2008
;
209 mips_use_nan_legacy
= !!cpu_has_nan_legacy
;
210 mips_use_nan_2008
= !cpu_has_nan_legacy
;
213 mips_use_nan_legacy
= !cpu_has_nan_2008
;
214 mips_use_nan_2008
= !!cpu_has_nan_2008
;
217 mips_use_nan_legacy
= true;
218 mips_use_nan_2008
= true;
224 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
227 * strict: accept binaries that request a NaN encoding supported by the FPU
228 * legacy: only accept legacy-NaN binaries
229 * 2008: only accept 2008-NaN binaries
230 * relaxed: accept any binaries regardless of whether supported by the FPU
232 static int __init
ieee754_setup(char *s
)
236 else if (!strcmp(s
, "strict"))
238 else if (!strcmp(s
, "legacy"))
240 else if (!strcmp(s
, "2008"))
242 else if (!strcmp(s
, "relaxed"))
247 if (!(boot_cpu_data
.options
& MIPS_CPU_FPU
))
248 cpu_set_nofpu_2008(&boot_cpu_data
);
249 cpu_set_nan_2008(&boot_cpu_data
);
254 early_param("ieee754", ieee754_setup
);
257 * Set the FIR feature flags for the FPU emulator.
259 static void cpu_set_nofpu_id(struct cpuinfo_mips
*c
)
264 if (c
->isa_level
& (MIPS_CPU_ISA_M32R1
| MIPS_CPU_ISA_M64R1
|
265 MIPS_CPU_ISA_M32R2
| MIPS_CPU_ISA_M64R2
|
266 MIPS_CPU_ISA_M32R6
| MIPS_CPU_ISA_M64R6
))
267 value
|= MIPS_FPIR_D
| MIPS_FPIR_S
;
268 if (c
->isa_level
& (MIPS_CPU_ISA_M32R2
| MIPS_CPU_ISA_M64R2
|
269 MIPS_CPU_ISA_M32R6
| MIPS_CPU_ISA_M64R6
))
270 value
|= MIPS_FPIR_F64
| MIPS_FPIR_L
| MIPS_FPIR_W
;
271 if (c
->options
& MIPS_CPU_NAN_2008
)
272 value
|= MIPS_FPIR_HAS2008
;
276 /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
277 static unsigned int mips_nofpu_msk31
;
280 * Set options for FPU hardware.
282 static void cpu_set_fpu_opts(struct cpuinfo_mips
*c
)
284 c
->fpu_id
= cpu_get_fpu_id();
285 mips_nofpu_msk31
= c
->fpu_msk31
;
287 if (c
->isa_level
& (MIPS_CPU_ISA_M32R1
| MIPS_CPU_ISA_M64R1
|
288 MIPS_CPU_ISA_M32R2
| MIPS_CPU_ISA_M64R2
|
289 MIPS_CPU_ISA_M32R6
| MIPS_CPU_ISA_M64R6
)) {
290 if (c
->fpu_id
& MIPS_FPIR_3D
)
291 c
->ases
|= MIPS_ASE_MIPS3D
;
292 if (c
->fpu_id
& MIPS_FPIR_FREP
)
293 c
->options
|= MIPS_CPU_FRE
;
296 cpu_set_fpu_fcsr_mask(c
);
302 * Set options for the FPU emulator.
304 static void cpu_set_nofpu_opts(struct cpuinfo_mips
*c
)
306 c
->options
&= ~MIPS_CPU_FPU
;
307 c
->fpu_msk31
= mips_nofpu_msk31
;
309 cpu_set_nofpu_2008(c
);
314 static int mips_fpu_disabled
;
316 static int __init
fpu_disable(char *s
)
318 cpu_set_nofpu_opts(&boot_cpu_data
);
319 mips_fpu_disabled
= 1;
324 __setup("nofpu", fpu_disable
);
326 int mips_dsp_disabled
;
328 static int __init
dsp_disable(char *s
)
330 cpu_data
[0].ases
&= ~(MIPS_ASE_DSP
| MIPS_ASE_DSP2P
);
331 mips_dsp_disabled
= 1;
336 __setup("nodsp", dsp_disable
);
338 static int mips_htw_disabled
;
340 static int __init
htw_disable(char *s
)
342 mips_htw_disabled
= 1;
343 cpu_data
[0].options
&= ~MIPS_CPU_HTW
;
344 write_c0_pwctl(read_c0_pwctl() &
345 ~(1 << MIPS_PWCTL_PWEN_SHIFT
));
350 __setup("nohtw", htw_disable
);
352 static int mips_ftlb_disabled
;
353 static int mips_has_ftlb_configured
;
355 static int set_ftlb_enable(struct cpuinfo_mips
*c
, int enable
);
357 static int __init
ftlb_disable(char *s
)
359 unsigned int config4
, mmuextdef
;
362 * If the core hasn't done any FTLB configuration, there is nothing
365 if (!mips_has_ftlb_configured
)
368 /* Disable it in the boot cpu */
369 if (set_ftlb_enable(&cpu_data
[0], 0)) {
370 pr_warn("Can't turn FTLB off\n");
374 back_to_back_c0_hazard();
376 config4
= read_c0_config4();
378 /* Check that FTLB has been disabled */
379 mmuextdef
= config4
& MIPS_CONF4_MMUEXTDEF
;
380 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
381 if (mmuextdef
== MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT
) {
382 /* This should never happen */
383 pr_warn("FTLB could not be disabled!\n");
387 mips_ftlb_disabled
= 1;
388 mips_has_ftlb_configured
= 0;
391 * noftlb is mainly used for debug purposes so print
392 * an informative message instead of using pr_debug()
394 pr_info("FTLB has been disabled\n");
397 * Some of these bits are duplicated in the decode_config4.
398 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
399 * once FTLB has been disabled so undo what decode_config4 did.
401 cpu_data
[0].tlbsize
-= cpu_data
[0].tlbsizeftlbways
*
402 cpu_data
[0].tlbsizeftlbsets
;
403 cpu_data
[0].tlbsizeftlbsets
= 0;
404 cpu_data
[0].tlbsizeftlbways
= 0;
409 __setup("noftlb", ftlb_disable
);
412 static inline void check_errata(void)
414 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
416 switch (current_cpu_type()) {
419 * Erratum "RPS May Cause Incorrect Instruction Execution"
420 * This code only handles VPE0, any SMP/RTOS code
421 * making use of VPE1 will be responsable for that VPE.
423 if ((c
->processor_id
& PRID_REV_MASK
) <= PRID_REV_34K_V1_0_2
)
424 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS
);
431 void __init
check_bugs32(void)
437 * Probe whether cpu has config register by trying to play with
438 * alternate cache bit and see whether it matters.
439 * It's used by cpu_probe to distinguish between R3000A and R3081.
441 static inline int cpu_has_confreg(void)
443 #ifdef CONFIG_CPU_R3000
444 extern unsigned long r3k_cache_size(unsigned long);
445 unsigned long size1
, size2
;
446 unsigned long cfg
= read_c0_conf();
448 size1
= r3k_cache_size(ST0_ISC
);
449 write_c0_conf(cfg
^ R30XX_CONF_AC
);
450 size2
= r3k_cache_size(ST0_ISC
);
452 return size1
!= size2
;
458 static inline void set_elf_platform(int cpu
, const char *plat
)
461 __elf_platform
= plat
;
464 static inline void cpu_probe_vmbits(struct cpuinfo_mips
*c
)
466 #ifdef __NEED_VMBITS_PROBE
467 write_c0_entryhi(0x3fffffffffffe000ULL
);
468 back_to_back_c0_hazard();
469 c
->vmbits
= fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL
);
473 static void set_isa(struct cpuinfo_mips
*c
, unsigned int isa
)
476 case MIPS_CPU_ISA_M64R2
:
477 c
->isa_level
|= MIPS_CPU_ISA_M32R2
| MIPS_CPU_ISA_M64R2
;
478 case MIPS_CPU_ISA_M64R1
:
479 c
->isa_level
|= MIPS_CPU_ISA_M32R1
| MIPS_CPU_ISA_M64R1
;
481 c
->isa_level
|= MIPS_CPU_ISA_V
;
482 case MIPS_CPU_ISA_IV
:
483 c
->isa_level
|= MIPS_CPU_ISA_IV
;
484 case MIPS_CPU_ISA_III
:
485 c
->isa_level
|= MIPS_CPU_ISA_II
| MIPS_CPU_ISA_III
;
488 /* R6 incompatible with everything else */
489 case MIPS_CPU_ISA_M64R6
:
490 c
->isa_level
|= MIPS_CPU_ISA_M32R6
| MIPS_CPU_ISA_M64R6
;
491 case MIPS_CPU_ISA_M32R6
:
492 c
->isa_level
|= MIPS_CPU_ISA_M32R6
;
493 /* Break here so we don't add incompatible ISAs */
495 case MIPS_CPU_ISA_M32R2
:
496 c
->isa_level
|= MIPS_CPU_ISA_M32R2
;
497 case MIPS_CPU_ISA_M32R1
:
498 c
->isa_level
|= MIPS_CPU_ISA_M32R1
;
499 case MIPS_CPU_ISA_II
:
500 c
->isa_level
|= MIPS_CPU_ISA_II
;
505 static char unknown_isa
[] = KERN_ERR \
506 "Unsupported ISA type, c0.config0: %d.";
508 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips
*c
)
511 unsigned int probability
= c
->tlbsize
/ c
->tlbsizevtlb
;
514 * 0 = All TLBWR instructions go to FTLB
515 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
516 * FTLB and 1 goes to the VTLB.
517 * 2 = 7:1: As above with 7:1 ratio.
518 * 3 = 3:1: As above with 3:1 ratio.
520 * Use the linear midpoint as the probability threshold.
522 if (probability
>= 12)
524 else if (probability
>= 6)
528 * So FTLB is less than 4 times bigger than VTLB.
529 * A 3:1 ratio can still be useful though.
534 static int set_ftlb_enable(struct cpuinfo_mips
*c
, int enable
)
538 /* It's implementation dependent how the FTLB can be enabled */
539 switch (c
->cputype
) {
543 /* proAptiv & related cores use Config6 to enable the FTLB */
544 config
= read_c0_config6();
545 /* Clear the old probability value */
546 config
&= ~(3 << MIPS_CONF6_FTLBP_SHIFT
);
549 write_c0_config6(config
|
550 (calculate_ftlb_probability(c
)
551 << MIPS_CONF6_FTLBP_SHIFT
)
552 | MIPS_CONF6_FTLBEN
);
555 write_c0_config6(config
& ~MIPS_CONF6_FTLBEN
);
558 /* I6400 & related cores use Config7 to configure FTLB */
559 config
= read_c0_config7();
560 /* Clear the old probability value */
561 config
&= ~(3 << MIPS_CONF7_FTLBP_SHIFT
);
562 write_c0_config7(config
| (calculate_ftlb_probability(c
)
563 << MIPS_CONF7_FTLBP_SHIFT
));
566 /* Flush ITLB, DTLB, VTLB and FTLB */
567 write_c0_diag(LOONGSON_DIAG_ITLB
| LOONGSON_DIAG_DTLB
|
568 LOONGSON_DIAG_VTLB
| LOONGSON_DIAG_FTLB
);
569 /* Loongson-3 cores use Config6 to enable the FTLB */
570 config
= read_c0_config6();
573 write_c0_config6(config
& ~MIPS_CONF6_FTLBDIS
);
576 write_c0_config6(config
| MIPS_CONF6_FTLBDIS
);
585 static inline unsigned int decode_config0(struct cpuinfo_mips
*c
)
587 unsigned int config0
;
590 config0
= read_c0_config();
593 * Look for Standard TLB or Dual VTLB and FTLB
595 mt
= config0
& MIPS_CONF_MT
;
596 if (mt
== MIPS_CONF_MT_TLB
)
597 c
->options
|= MIPS_CPU_TLB
;
598 else if (mt
== MIPS_CONF_MT_FTLB
)
599 c
->options
|= MIPS_CPU_TLB
| MIPS_CPU_FTLB
;
601 isa
= (config0
& MIPS_CONF_AT
) >> 13;
604 switch ((config0
& MIPS_CONF_AR
) >> 10) {
606 set_isa(c
, MIPS_CPU_ISA_M32R1
);
609 set_isa(c
, MIPS_CPU_ISA_M32R2
);
612 set_isa(c
, MIPS_CPU_ISA_M32R6
);
619 switch ((config0
& MIPS_CONF_AR
) >> 10) {
621 set_isa(c
, MIPS_CPU_ISA_M64R1
);
624 set_isa(c
, MIPS_CPU_ISA_M64R2
);
627 set_isa(c
, MIPS_CPU_ISA_M64R6
);
637 return config0
& MIPS_CONF_M
;
640 panic(unknown_isa
, config0
);
643 static inline unsigned int decode_config1(struct cpuinfo_mips
*c
)
645 unsigned int config1
;
647 config1
= read_c0_config1();
649 if (config1
& MIPS_CONF1_MD
)
650 c
->ases
|= MIPS_ASE_MDMX
;
651 if (config1
& MIPS_CONF1_WR
)
652 c
->options
|= MIPS_CPU_WATCH
;
653 if (config1
& MIPS_CONF1_CA
)
654 c
->ases
|= MIPS_ASE_MIPS16
;
655 if (config1
& MIPS_CONF1_EP
)
656 c
->options
|= MIPS_CPU_EJTAG
;
657 if (config1
& MIPS_CONF1_FP
) {
658 c
->options
|= MIPS_CPU_FPU
;
659 c
->options
|= MIPS_CPU_32FPR
;
662 c
->tlbsize
= ((config1
& MIPS_CONF1_TLBS
) >> 25) + 1;
663 c
->tlbsizevtlb
= c
->tlbsize
;
664 c
->tlbsizeftlbsets
= 0;
667 return config1
& MIPS_CONF_M
;
670 static inline unsigned int decode_config2(struct cpuinfo_mips
*c
)
672 unsigned int config2
;
674 config2
= read_c0_config2();
676 if (config2
& MIPS_CONF2_SL
)
677 c
->scache
.flags
&= ~MIPS_CACHE_NOT_PRESENT
;
679 return config2
& MIPS_CONF_M
;
682 static inline unsigned int decode_config3(struct cpuinfo_mips
*c
)
684 unsigned int config3
;
686 config3
= read_c0_config3();
688 if (config3
& MIPS_CONF3_SM
) {
689 c
->ases
|= MIPS_ASE_SMARTMIPS
;
690 c
->options
|= MIPS_CPU_RIXI
;
692 if (config3
& MIPS_CONF3_RXI
)
693 c
->options
|= MIPS_CPU_RIXI
;
694 if (config3
& MIPS_CONF3_DSP
)
695 c
->ases
|= MIPS_ASE_DSP
;
696 if (config3
& MIPS_CONF3_DSP2P
) {
697 c
->ases
|= MIPS_ASE_DSP2P
;
699 c
->ases
|= MIPS_ASE_DSP3
;
701 if (config3
& MIPS_CONF3_VINT
)
702 c
->options
|= MIPS_CPU_VINT
;
703 if (config3
& MIPS_CONF3_VEIC
)
704 c
->options
|= MIPS_CPU_VEIC
;
705 if (config3
& MIPS_CONF3_MT
)
706 c
->ases
|= MIPS_ASE_MIPSMT
;
707 if (config3
& MIPS_CONF3_ULRI
)
708 c
->options
|= MIPS_CPU_ULRI
;
709 if (config3
& MIPS_CONF3_ISA
)
710 c
->options
|= MIPS_CPU_MICROMIPS
;
711 if (config3
& MIPS_CONF3_VZ
)
712 c
->ases
|= MIPS_ASE_VZ
;
713 if (config3
& MIPS_CONF3_SC
)
714 c
->options
|= MIPS_CPU_SEGMENTS
;
715 if (config3
& MIPS_CONF3_MSA
)
716 c
->ases
|= MIPS_ASE_MSA
;
717 if (config3
& MIPS_CONF3_PW
) {
719 c
->options
|= MIPS_CPU_HTW
;
721 if (config3
& MIPS_CONF3_CDMM
)
722 c
->options
|= MIPS_CPU_CDMM
;
723 if (config3
& MIPS_CONF3_SP
)
724 c
->options
|= MIPS_CPU_SP
;
726 return config3
& MIPS_CONF_M
;
729 static inline unsigned int decode_config4(struct cpuinfo_mips
*c
)
731 unsigned int config4
;
733 unsigned int mmuextdef
;
734 unsigned int ftlb_page
= MIPS_CONF4_FTLBPAGESIZE
;
735 unsigned long asid_mask
;
737 config4
= read_c0_config4();
740 if (((config4
& MIPS_CONF4_IE
) >> 29) == 2)
741 c
->options
|= MIPS_CPU_TLBINV
;
744 * R6 has dropped the MMUExtDef field from config4.
745 * On R6 the fields always describe the FTLB, and only if it is
746 * present according to Config.MT.
748 if (!cpu_has_mips_r6
)
749 mmuextdef
= config4
& MIPS_CONF4_MMUEXTDEF
;
750 else if (cpu_has_ftlb
)
751 mmuextdef
= MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT
;
756 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
:
757 c
->tlbsize
+= (config4
& MIPS_CONF4_MMUSIZEEXT
) * 0x40;
758 c
->tlbsizevtlb
= c
->tlbsize
;
760 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT
:
762 ((config4
& MIPS_CONF4_VTLBSIZEEXT
) >>
763 MIPS_CONF4_VTLBSIZEEXT_SHIFT
) * 0x40;
764 c
->tlbsize
= c
->tlbsizevtlb
;
765 ftlb_page
= MIPS_CONF4_VFTLBPAGESIZE
;
767 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT
:
768 if (mips_ftlb_disabled
)
770 newcf4
= (config4
& ~ftlb_page
) |
771 (page_size_ftlb(mmuextdef
) <<
772 MIPS_CONF4_FTLBPAGESIZE_SHIFT
);
773 write_c0_config4(newcf4
);
774 back_to_back_c0_hazard();
775 config4
= read_c0_config4();
776 if (config4
!= newcf4
) {
777 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
779 /* Switch FTLB off */
780 set_ftlb_enable(c
, 0);
783 c
->tlbsizeftlbsets
= 1 <<
784 ((config4
& MIPS_CONF4_FTLBSETS
) >>
785 MIPS_CONF4_FTLBSETS_SHIFT
);
786 c
->tlbsizeftlbways
= ((config4
& MIPS_CONF4_FTLBWAYS
) >>
787 MIPS_CONF4_FTLBWAYS_SHIFT
) + 2;
788 c
->tlbsize
+= c
->tlbsizeftlbways
* c
->tlbsizeftlbsets
;
789 mips_has_ftlb_configured
= 1;
794 c
->kscratch_mask
= (config4
>> 16) & 0xff;
796 asid_mask
= MIPS_ENTRYHI_ASID
;
797 if (config4
& MIPS_CONF4_AE
)
798 asid_mask
|= MIPS_ENTRYHI_ASIDX
;
799 set_cpu_asid_mask(c
, asid_mask
);
802 * Warn if the computed ASID mask doesn't match the mask the kernel
803 * is built for. This may indicate either a serious problem or an
804 * easy optimisation opportunity, but either way should be addressed.
806 WARN_ON(asid_mask
!= cpu_asid_mask(c
));
808 return config4
& MIPS_CONF_M
;
811 static inline unsigned int decode_config5(struct cpuinfo_mips
*c
)
813 unsigned int config5
;
815 config5
= read_c0_config5();
816 config5
&= ~(MIPS_CONF5_UFR
| MIPS_CONF5_UFE
);
817 write_c0_config5(config5
);
819 if (config5
& MIPS_CONF5_EVA
)
820 c
->options
|= MIPS_CPU_EVA
;
821 if (config5
& MIPS_CONF5_MRP
)
822 c
->options
|= MIPS_CPU_MAAR
;
823 if (config5
& MIPS_CONF5_LLB
)
824 c
->options
|= MIPS_CPU_RW_LLB
;
826 if (config5
& MIPS_CONF5_MVH
)
827 c
->options
|= MIPS_CPU_XPA
;
829 if (cpu_has_mips_r6
&& (config5
& MIPS_CONF5_VP
))
830 c
->options
|= MIPS_CPU_VP
;
832 return config5
& MIPS_CONF_M
;
835 static void decode_configs(struct cpuinfo_mips
*c
)
839 /* MIPS32 or MIPS64 compliant CPU. */
840 c
->options
= MIPS_CPU_4KEX
| MIPS_CPU_4K_CACHE
| MIPS_CPU_COUNTER
|
841 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
| MIPS_CPU_MCHECK
;
843 c
->scache
.flags
= MIPS_CACHE_NOT_PRESENT
;
845 /* Enable FTLB if present and not disabled */
846 set_ftlb_enable(c
, !mips_ftlb_disabled
);
848 ok
= decode_config0(c
); /* Read Config registers. */
849 BUG_ON(!ok
); /* Arch spec violation! */
851 ok
= decode_config1(c
);
853 ok
= decode_config2(c
);
855 ok
= decode_config3(c
);
857 ok
= decode_config4(c
);
859 ok
= decode_config5(c
);
861 mips_probe_watch_registers(c
);
864 /* Enable the RIXI exceptions */
865 set_c0_pagegrain(PG_IEC
);
866 back_to_back_c0_hazard();
867 /* Verify the IEC bit is set */
868 if (read_c0_pagegrain() & PG_IEC
)
869 c
->options
|= MIPS_CPU_RIXIEX
;
872 #ifndef CONFIG_MIPS_CPS
873 if (cpu_has_mips_r2_r6
) {
874 c
->core
= get_ebase_cpunum();
876 c
->core
>>= fls(core_nvpes()) - 1;
881 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
884 static inline void cpu_probe_legacy(struct cpuinfo_mips
*c
, unsigned int cpu
)
886 switch (c
->processor_id
& PRID_IMP_MASK
) {
888 c
->cputype
= CPU_R2000
;
889 __cpu_name
[cpu
] = "R2000";
890 c
->fpu_msk31
|= FPU_CSR_CONDX
| FPU_CSR_FS
;
891 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_3K_CACHE
|
894 c
->options
|= MIPS_CPU_FPU
;
898 if ((c
->processor_id
& PRID_REV_MASK
) == PRID_REV_R3000A
) {
899 if (cpu_has_confreg()) {
900 c
->cputype
= CPU_R3081E
;
901 __cpu_name
[cpu
] = "R3081";
903 c
->cputype
= CPU_R3000A
;
904 __cpu_name
[cpu
] = "R3000A";
907 c
->cputype
= CPU_R3000
;
908 __cpu_name
[cpu
] = "R3000";
910 c
->fpu_msk31
|= FPU_CSR_CONDX
| FPU_CSR_FS
;
911 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_3K_CACHE
|
914 c
->options
|= MIPS_CPU_FPU
;
918 if (read_c0_config() & CONF_SC
) {
919 if ((c
->processor_id
& PRID_REV_MASK
) >=
921 c
->cputype
= CPU_R4400PC
;
922 __cpu_name
[cpu
] = "R4400PC";
924 c
->cputype
= CPU_R4000PC
;
925 __cpu_name
[cpu
] = "R4000PC";
928 int cca
= read_c0_config() & CONF_CM_CMASK
;
932 * SC and MC versions can't be reliably told apart,
933 * but only the latter support coherent caching
934 * modes so assume the firmware has set the KSEG0
935 * coherency attribute reasonably (if uncached, we
939 case CONF_CM_CACHABLE_CE
:
940 case CONF_CM_CACHABLE_COW
:
941 case CONF_CM_CACHABLE_CUW
:
948 if ((c
->processor_id
& PRID_REV_MASK
) >=
950 c
->cputype
= mc
? CPU_R4400MC
: CPU_R4400SC
;
951 __cpu_name
[cpu
] = mc
? "R4400MC" : "R4400SC";
953 c
->cputype
= mc
? CPU_R4000MC
: CPU_R4000SC
;
954 __cpu_name
[cpu
] = mc
? "R4000MC" : "R4000SC";
958 set_isa(c
, MIPS_CPU_ISA_III
);
959 c
->fpu_msk31
|= FPU_CSR_CONDX
;
960 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
961 MIPS_CPU_WATCH
| MIPS_CPU_VCE
|
965 case PRID_IMP_VR41XX
:
966 set_isa(c
, MIPS_CPU_ISA_III
);
967 c
->fpu_msk31
|= FPU_CSR_CONDX
;
968 c
->options
= R4K_OPTS
;
970 switch (c
->processor_id
& 0xf0) {
971 case PRID_REV_VR4111
:
972 c
->cputype
= CPU_VR4111
;
973 __cpu_name
[cpu
] = "NEC VR4111";
975 case PRID_REV_VR4121
:
976 c
->cputype
= CPU_VR4121
;
977 __cpu_name
[cpu
] = "NEC VR4121";
979 case PRID_REV_VR4122
:
980 if ((c
->processor_id
& 0xf) < 0x3) {
981 c
->cputype
= CPU_VR4122
;
982 __cpu_name
[cpu
] = "NEC VR4122";
984 c
->cputype
= CPU_VR4181A
;
985 __cpu_name
[cpu
] = "NEC VR4181A";
988 case PRID_REV_VR4130
:
989 if ((c
->processor_id
& 0xf) < 0x4) {
990 c
->cputype
= CPU_VR4131
;
991 __cpu_name
[cpu
] = "NEC VR4131";
993 c
->cputype
= CPU_VR4133
;
994 c
->options
|= MIPS_CPU_LLSC
;
995 __cpu_name
[cpu
] = "NEC VR4133";
999 printk(KERN_INFO
"Unexpected CPU of NEC VR4100 series\n");
1000 c
->cputype
= CPU_VR41XX
;
1001 __cpu_name
[cpu
] = "NEC Vr41xx";
1005 case PRID_IMP_R4300
:
1006 c
->cputype
= CPU_R4300
;
1007 __cpu_name
[cpu
] = "R4300";
1008 set_isa(c
, MIPS_CPU_ISA_III
);
1009 c
->fpu_msk31
|= FPU_CSR_CONDX
;
1010 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
1014 case PRID_IMP_R4600
:
1015 c
->cputype
= CPU_R4600
;
1016 __cpu_name
[cpu
] = "R4600";
1017 set_isa(c
, MIPS_CPU_ISA_III
);
1018 c
->fpu_msk31
|= FPU_CSR_CONDX
;
1019 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
1024 case PRID_IMP_R4650
:
1026 * This processor doesn't have an MMU, so it's not
1027 * "real easy" to run Linux on it. It is left purely
1028 * for documentation. Commented out because it shares
1029 * it's c0_prid id number with the TX3900.
1031 c
->cputype
= CPU_R4650
;
1032 __cpu_name
[cpu
] = "R4650";
1033 set_isa(c
, MIPS_CPU_ISA_III
);
1034 c
->fpu_msk31
|= FPU_CSR_CONDX
;
1035 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_LLSC
;
1040 c
->fpu_msk31
|= FPU_CSR_CONDX
| FPU_CSR_FS
;
1041 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_TX39_CACHE
;
1043 if ((c
->processor_id
& 0xf0) == (PRID_REV_TX3927
& 0xf0)) {
1044 c
->cputype
= CPU_TX3927
;
1045 __cpu_name
[cpu
] = "TX3927";
1048 switch (c
->processor_id
& PRID_REV_MASK
) {
1049 case PRID_REV_TX3912
:
1050 c
->cputype
= CPU_TX3912
;
1051 __cpu_name
[cpu
] = "TX3912";
1054 case PRID_REV_TX3922
:
1055 c
->cputype
= CPU_TX3922
;
1056 __cpu_name
[cpu
] = "TX3922";
1062 case PRID_IMP_R4700
:
1063 c
->cputype
= CPU_R4700
;
1064 __cpu_name
[cpu
] = "R4700";
1065 set_isa(c
, MIPS_CPU_ISA_III
);
1066 c
->fpu_msk31
|= FPU_CSR_CONDX
;
1067 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
1072 c
->cputype
= CPU_TX49XX
;
1073 __cpu_name
[cpu
] = "R49XX";
1074 set_isa(c
, MIPS_CPU_ISA_III
);
1075 c
->fpu_msk31
|= FPU_CSR_CONDX
;
1076 c
->options
= R4K_OPTS
| MIPS_CPU_LLSC
;
1077 if (!(c
->processor_id
& 0x08))
1078 c
->options
|= MIPS_CPU_FPU
| MIPS_CPU_32FPR
;
1081 case PRID_IMP_R5000
:
1082 c
->cputype
= CPU_R5000
;
1083 __cpu_name
[cpu
] = "R5000";
1084 set_isa(c
, MIPS_CPU_ISA_IV
);
1085 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
1089 case PRID_IMP_R5432
:
1090 c
->cputype
= CPU_R5432
;
1091 __cpu_name
[cpu
] = "R5432";
1092 set_isa(c
, MIPS_CPU_ISA_IV
);
1093 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
1094 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
1097 case PRID_IMP_R5500
:
1098 c
->cputype
= CPU_R5500
;
1099 __cpu_name
[cpu
] = "R5500";
1100 set_isa(c
, MIPS_CPU_ISA_IV
);
1101 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
1102 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
1105 case PRID_IMP_NEVADA
:
1106 c
->cputype
= CPU_NEVADA
;
1107 __cpu_name
[cpu
] = "Nevada";
1108 set_isa(c
, MIPS_CPU_ISA_IV
);
1109 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
1110 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
;
1113 case PRID_IMP_R6000
:
1114 c
->cputype
= CPU_R6000
;
1115 __cpu_name
[cpu
] = "R6000";
1116 set_isa(c
, MIPS_CPU_ISA_II
);
1117 c
->fpu_msk31
|= FPU_CSR_CONDX
| FPU_CSR_FS
;
1118 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
1122 case PRID_IMP_R6000A
:
1123 c
->cputype
= CPU_R6000A
;
1124 __cpu_name
[cpu
] = "R6000A";
1125 set_isa(c
, MIPS_CPU_ISA_II
);
1126 c
->fpu_msk31
|= FPU_CSR_CONDX
| FPU_CSR_FS
;
1127 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
1131 case PRID_IMP_RM7000
:
1132 c
->cputype
= CPU_RM7000
;
1133 __cpu_name
[cpu
] = "RM7000";
1134 set_isa(c
, MIPS_CPU_ISA_IV
);
1135 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
1138 * Undocumented RM7000: Bit 29 in the info register of
1139 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1142 * 29 1 => 64 entry JTLB
1143 * 0 => 48 entry JTLB
1145 c
->tlbsize
= (read_c0_info() & (1 << 29)) ? 64 : 48;
1147 case PRID_IMP_R8000
:
1148 c
->cputype
= CPU_R8000
;
1149 __cpu_name
[cpu
] = "RM8000";
1150 set_isa(c
, MIPS_CPU_ISA_IV
);
1151 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4KEX
|
1152 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
1154 c
->tlbsize
= 384; /* has weird TLB: 3-way x 128 */
1156 case PRID_IMP_R10000
:
1157 c
->cputype
= CPU_R10000
;
1158 __cpu_name
[cpu
] = "R10000";
1159 set_isa(c
, MIPS_CPU_ISA_IV
);
1160 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
1161 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
1162 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
1166 case PRID_IMP_R12000
:
1167 c
->cputype
= CPU_R12000
;
1168 __cpu_name
[cpu
] = "R12000";
1169 set_isa(c
, MIPS_CPU_ISA_IV
);
1170 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
1171 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
1172 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
1173 MIPS_CPU_LLSC
| MIPS_CPU_BP_GHIST
;
1176 case PRID_IMP_R14000
:
1177 if (((c
->processor_id
>> 4) & 0x0f) > 2) {
1178 c
->cputype
= CPU_R16000
;
1179 __cpu_name
[cpu
] = "R16000";
1181 c
->cputype
= CPU_R14000
;
1182 __cpu_name
[cpu
] = "R14000";
1184 set_isa(c
, MIPS_CPU_ISA_IV
);
1185 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
1186 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
1187 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
1188 MIPS_CPU_LLSC
| MIPS_CPU_BP_GHIST
;
1191 case PRID_IMP_LOONGSON_64
: /* Loongson-2/3 */
1192 switch (c
->processor_id
& PRID_REV_MASK
) {
1193 case PRID_REV_LOONGSON2E
:
1194 c
->cputype
= CPU_LOONGSON2
;
1195 __cpu_name
[cpu
] = "ICT Loongson-2";
1196 set_elf_platform(cpu
, "loongson2e");
1197 set_isa(c
, MIPS_CPU_ISA_III
);
1198 c
->fpu_msk31
|= FPU_CSR_CONDX
;
1200 case PRID_REV_LOONGSON2F
:
1201 c
->cputype
= CPU_LOONGSON2
;
1202 __cpu_name
[cpu
] = "ICT Loongson-2";
1203 set_elf_platform(cpu
, "loongson2f");
1204 set_isa(c
, MIPS_CPU_ISA_III
);
1205 c
->fpu_msk31
|= FPU_CSR_CONDX
;
1207 case PRID_REV_LOONGSON3A_R1
:
1208 c
->cputype
= CPU_LOONGSON3
;
1209 __cpu_name
[cpu
] = "ICT Loongson-3";
1210 set_elf_platform(cpu
, "loongson3a");
1211 set_isa(c
, MIPS_CPU_ISA_M64R1
);
1213 case PRID_REV_LOONGSON3B_R1
:
1214 case PRID_REV_LOONGSON3B_R2
:
1215 c
->cputype
= CPU_LOONGSON3
;
1216 __cpu_name
[cpu
] = "ICT Loongson-3";
1217 set_elf_platform(cpu
, "loongson3b");
1218 set_isa(c
, MIPS_CPU_ISA_M64R1
);
1222 c
->options
= R4K_OPTS
|
1223 MIPS_CPU_FPU
| MIPS_CPU_LLSC
|
1226 c
->writecombine
= _CACHE_UNCACHED_ACCELERATED
;
1228 case PRID_IMP_LOONGSON_32
: /* Loongson-1 */
1231 c
->cputype
= CPU_LOONGSON1
;
1233 switch (c
->processor_id
& PRID_REV_MASK
) {
1234 case PRID_REV_LOONGSON1B
:
1235 __cpu_name
[cpu
] = "Loongson 1B";
1243 static inline void cpu_probe_mips(struct cpuinfo_mips
*c
, unsigned int cpu
)
1245 c
->writecombine
= _CACHE_UNCACHED_ACCELERATED
;
1246 switch (c
->processor_id
& PRID_IMP_MASK
) {
1247 case PRID_IMP_QEMU_GENERIC
:
1248 c
->writecombine
= _CACHE_UNCACHED
;
1249 c
->cputype
= CPU_QEMU_GENERIC
;
1250 __cpu_name
[cpu
] = "MIPS GENERIC QEMU";
1253 c
->cputype
= CPU_4KC
;
1254 c
->writecombine
= _CACHE_UNCACHED
;
1255 __cpu_name
[cpu
] = "MIPS 4Kc";
1258 case PRID_IMP_4KECR2
:
1259 c
->cputype
= CPU_4KEC
;
1260 c
->writecombine
= _CACHE_UNCACHED
;
1261 __cpu_name
[cpu
] = "MIPS 4KEc";
1265 c
->cputype
= CPU_4KSC
;
1266 c
->writecombine
= _CACHE_UNCACHED
;
1267 __cpu_name
[cpu
] = "MIPS 4KSc";
1270 c
->cputype
= CPU_5KC
;
1271 c
->writecombine
= _CACHE_UNCACHED
;
1272 __cpu_name
[cpu
] = "MIPS 5Kc";
1275 c
->cputype
= CPU_5KE
;
1276 c
->writecombine
= _CACHE_UNCACHED
;
1277 __cpu_name
[cpu
] = "MIPS 5KE";
1280 c
->cputype
= CPU_20KC
;
1281 c
->writecombine
= _CACHE_UNCACHED
;
1282 __cpu_name
[cpu
] = "MIPS 20Kc";
1285 c
->cputype
= CPU_24K
;
1286 c
->writecombine
= _CACHE_UNCACHED
;
1287 __cpu_name
[cpu
] = "MIPS 24Kc";
1290 c
->cputype
= CPU_24K
;
1291 c
->writecombine
= _CACHE_UNCACHED
;
1292 __cpu_name
[cpu
] = "MIPS 24KEc";
1295 c
->cputype
= CPU_25KF
;
1296 c
->writecombine
= _CACHE_UNCACHED
;
1297 __cpu_name
[cpu
] = "MIPS 25Kc";
1300 c
->cputype
= CPU_34K
;
1301 c
->writecombine
= _CACHE_UNCACHED
;
1302 __cpu_name
[cpu
] = "MIPS 34Kc";
1305 c
->cputype
= CPU_74K
;
1306 c
->writecombine
= _CACHE_UNCACHED
;
1307 __cpu_name
[cpu
] = "MIPS 74Kc";
1309 case PRID_IMP_M14KC
:
1310 c
->cputype
= CPU_M14KC
;
1311 c
->writecombine
= _CACHE_UNCACHED
;
1312 __cpu_name
[cpu
] = "MIPS M14Kc";
1314 case PRID_IMP_M14KEC
:
1315 c
->cputype
= CPU_M14KEC
;
1316 c
->writecombine
= _CACHE_UNCACHED
;
1317 __cpu_name
[cpu
] = "MIPS M14KEc";
1319 case PRID_IMP_1004K
:
1320 c
->cputype
= CPU_1004K
;
1321 c
->writecombine
= _CACHE_UNCACHED
;
1322 __cpu_name
[cpu
] = "MIPS 1004Kc";
1324 case PRID_IMP_1074K
:
1325 c
->cputype
= CPU_1074K
;
1326 c
->writecombine
= _CACHE_UNCACHED
;
1327 __cpu_name
[cpu
] = "MIPS 1074Kc";
1329 case PRID_IMP_INTERAPTIV_UP
:
1330 c
->cputype
= CPU_INTERAPTIV
;
1331 __cpu_name
[cpu
] = "MIPS interAptiv";
1333 case PRID_IMP_INTERAPTIV_MP
:
1334 c
->cputype
= CPU_INTERAPTIV
;
1335 __cpu_name
[cpu
] = "MIPS interAptiv (multi)";
1337 case PRID_IMP_PROAPTIV_UP
:
1338 c
->cputype
= CPU_PROAPTIV
;
1339 __cpu_name
[cpu
] = "MIPS proAptiv";
1341 case PRID_IMP_PROAPTIV_MP
:
1342 c
->cputype
= CPU_PROAPTIV
;
1343 __cpu_name
[cpu
] = "MIPS proAptiv (multi)";
1345 case PRID_IMP_P5600
:
1346 c
->cputype
= CPU_P5600
;
1347 __cpu_name
[cpu
] = "MIPS P5600";
1349 case PRID_IMP_P6600
:
1350 c
->cputype
= CPU_P6600
;
1351 __cpu_name
[cpu
] = "MIPS P6600";
1353 case PRID_IMP_I6400
:
1354 c
->cputype
= CPU_I6400
;
1355 __cpu_name
[cpu
] = "MIPS I6400";
1357 case PRID_IMP_M5150
:
1358 c
->cputype
= CPU_M5150
;
1359 __cpu_name
[cpu
] = "MIPS M5150";
1361 case PRID_IMP_M6250
:
1362 c
->cputype
= CPU_M6250
;
1363 __cpu_name
[cpu
] = "MIPS M6250";
1372 static inline void cpu_probe_alchemy(struct cpuinfo_mips
*c
, unsigned int cpu
)
1375 switch (c
->processor_id
& PRID_IMP_MASK
) {
1376 case PRID_IMP_AU1_REV1
:
1377 case PRID_IMP_AU1_REV2
:
1378 c
->cputype
= CPU_ALCHEMY
;
1379 switch ((c
->processor_id
>> 24) & 0xff) {
1381 __cpu_name
[cpu
] = "Au1000";
1384 __cpu_name
[cpu
] = "Au1500";
1387 __cpu_name
[cpu
] = "Au1100";
1390 __cpu_name
[cpu
] = "Au1550";
1393 __cpu_name
[cpu
] = "Au1200";
1394 if ((c
->processor_id
& PRID_REV_MASK
) == 2)
1395 __cpu_name
[cpu
] = "Au1250";
1398 __cpu_name
[cpu
] = "Au1210";
1401 __cpu_name
[cpu
] = "Au1xxx";
1408 static inline void cpu_probe_sibyte(struct cpuinfo_mips
*c
, unsigned int cpu
)
1412 c
->writecombine
= _CACHE_UNCACHED_ACCELERATED
;
1413 switch (c
->processor_id
& PRID_IMP_MASK
) {
1415 c
->cputype
= CPU_SB1
;
1416 __cpu_name
[cpu
] = "SiByte SB1";
1417 /* FPU in pass1 is known to have issues. */
1418 if ((c
->processor_id
& PRID_REV_MASK
) < 0x02)
1419 c
->options
&= ~(MIPS_CPU_FPU
| MIPS_CPU_32FPR
);
1422 c
->cputype
= CPU_SB1A
;
1423 __cpu_name
[cpu
] = "SiByte SB1A";
1428 static inline void cpu_probe_sandcraft(struct cpuinfo_mips
*c
, unsigned int cpu
)
1431 switch (c
->processor_id
& PRID_IMP_MASK
) {
1432 case PRID_IMP_SR71000
:
1433 c
->cputype
= CPU_SR71000
;
1434 __cpu_name
[cpu
] = "Sandcraft SR71000";
1441 static inline void cpu_probe_nxp(struct cpuinfo_mips
*c
, unsigned int cpu
)
1444 switch (c
->processor_id
& PRID_IMP_MASK
) {
1445 case PRID_IMP_PR4450
:
1446 c
->cputype
= CPU_PR4450
;
1447 __cpu_name
[cpu
] = "Philips PR4450";
1448 set_isa(c
, MIPS_CPU_ISA_M32R1
);
1453 static inline void cpu_probe_broadcom(struct cpuinfo_mips
*c
, unsigned int cpu
)
1456 switch (c
->processor_id
& PRID_IMP_MASK
) {
1457 case PRID_IMP_BMIPS32_REV4
:
1458 case PRID_IMP_BMIPS32_REV8
:
1459 c
->cputype
= CPU_BMIPS32
;
1460 __cpu_name
[cpu
] = "Broadcom BMIPS32";
1461 set_elf_platform(cpu
, "bmips32");
1463 case PRID_IMP_BMIPS3300
:
1464 case PRID_IMP_BMIPS3300_ALT
:
1465 case PRID_IMP_BMIPS3300_BUG
:
1466 c
->cputype
= CPU_BMIPS3300
;
1467 __cpu_name
[cpu
] = "Broadcom BMIPS3300";
1468 set_elf_platform(cpu
, "bmips3300");
1470 case PRID_IMP_BMIPS43XX
: {
1471 int rev
= c
->processor_id
& PRID_REV_MASK
;
1473 if (rev
>= PRID_REV_BMIPS4380_LO
&&
1474 rev
<= PRID_REV_BMIPS4380_HI
) {
1475 c
->cputype
= CPU_BMIPS4380
;
1476 __cpu_name
[cpu
] = "Broadcom BMIPS4380";
1477 set_elf_platform(cpu
, "bmips4380");
1479 c
->cputype
= CPU_BMIPS4350
;
1480 __cpu_name
[cpu
] = "Broadcom BMIPS4350";
1481 set_elf_platform(cpu
, "bmips4350");
1485 case PRID_IMP_BMIPS5000
:
1486 case PRID_IMP_BMIPS5200
:
1487 c
->cputype
= CPU_BMIPS5000
;
1488 if ((c
->processor_id
& PRID_IMP_MASK
) == PRID_IMP_BMIPS5200
)
1489 __cpu_name
[cpu
] = "Broadcom BMIPS5200";
1491 __cpu_name
[cpu
] = "Broadcom BMIPS5000";
1492 set_elf_platform(cpu
, "bmips5000");
1493 c
->options
|= MIPS_CPU_ULRI
;
1498 static inline void cpu_probe_cavium(struct cpuinfo_mips
*c
, unsigned int cpu
)
1501 switch (c
->processor_id
& PRID_IMP_MASK
) {
1502 case PRID_IMP_CAVIUM_CN38XX
:
1503 case PRID_IMP_CAVIUM_CN31XX
:
1504 case PRID_IMP_CAVIUM_CN30XX
:
1505 c
->cputype
= CPU_CAVIUM_OCTEON
;
1506 __cpu_name
[cpu
] = "Cavium Octeon";
1508 case PRID_IMP_CAVIUM_CN58XX
:
1509 case PRID_IMP_CAVIUM_CN56XX
:
1510 case PRID_IMP_CAVIUM_CN50XX
:
1511 case PRID_IMP_CAVIUM_CN52XX
:
1512 c
->cputype
= CPU_CAVIUM_OCTEON_PLUS
;
1513 __cpu_name
[cpu
] = "Cavium Octeon+";
1515 set_elf_platform(cpu
, "octeon");
1517 case PRID_IMP_CAVIUM_CN61XX
:
1518 case PRID_IMP_CAVIUM_CN63XX
:
1519 case PRID_IMP_CAVIUM_CN66XX
:
1520 case PRID_IMP_CAVIUM_CN68XX
:
1521 case PRID_IMP_CAVIUM_CNF71XX
:
1522 c
->cputype
= CPU_CAVIUM_OCTEON2
;
1523 __cpu_name
[cpu
] = "Cavium Octeon II";
1524 set_elf_platform(cpu
, "octeon2");
1526 case PRID_IMP_CAVIUM_CN70XX
:
1527 case PRID_IMP_CAVIUM_CN73XX
:
1528 case PRID_IMP_CAVIUM_CNF75XX
:
1529 case PRID_IMP_CAVIUM_CN78XX
:
1530 c
->cputype
= CPU_CAVIUM_OCTEON3
;
1531 __cpu_name
[cpu
] = "Cavium Octeon III";
1532 set_elf_platform(cpu
, "octeon3");
1535 printk(KERN_INFO
"Unknown Octeon chip!\n");
1536 c
->cputype
= CPU_UNKNOWN
;
1541 static inline void cpu_probe_loongson(struct cpuinfo_mips
*c
, unsigned int cpu
)
1543 switch (c
->processor_id
& PRID_IMP_MASK
) {
1544 case PRID_IMP_LOONGSON_64
: /* Loongson-2/3 */
1545 switch (c
->processor_id
& PRID_REV_MASK
) {
1546 case PRID_REV_LOONGSON3A_R2
:
1547 c
->cputype
= CPU_LOONGSON3
;
1548 __cpu_name
[cpu
] = "ICT Loongson-3";
1549 set_elf_platform(cpu
, "loongson3a");
1550 set_isa(c
, MIPS_CPU_ISA_M64R2
);
1555 c
->options
|= MIPS_CPU_TLBINV
| MIPS_CPU_LDPTE
;
1556 c
->writecombine
= _CACHE_UNCACHED_ACCELERATED
;
1559 panic("Unknown Loongson Processor ID!");
1564 static inline void cpu_probe_ingenic(struct cpuinfo_mips
*c
, unsigned int cpu
)
1567 /* JZRISC does not implement the CP0 counter. */
1568 c
->options
&= ~MIPS_CPU_COUNTER
;
1569 BUG_ON(!__builtin_constant_p(cpu_has_counter
) || cpu_has_counter
);
1570 switch (c
->processor_id
& PRID_IMP_MASK
) {
1571 case PRID_IMP_JZRISC
:
1572 c
->cputype
= CPU_JZRISC
;
1573 c
->writecombine
= _CACHE_UNCACHED_ACCELERATED
;
1574 __cpu_name
[cpu
] = "Ingenic JZRISC";
1577 panic("Unknown Ingenic Processor ID!");
1582 static inline void cpu_probe_netlogic(struct cpuinfo_mips
*c
, int cpu
)
1586 if ((c
->processor_id
& PRID_IMP_MASK
) == PRID_IMP_NETLOGIC_AU13XX
) {
1587 c
->cputype
= CPU_ALCHEMY
;
1588 __cpu_name
[cpu
] = "Au1300";
1589 /* following stuff is not for Alchemy */
1593 c
->options
= (MIPS_CPU_TLB
|
1601 switch (c
->processor_id
& PRID_IMP_MASK
) {
1602 case PRID_IMP_NETLOGIC_XLP2XX
:
1603 case PRID_IMP_NETLOGIC_XLP9XX
:
1604 case PRID_IMP_NETLOGIC_XLP5XX
:
1605 c
->cputype
= CPU_XLP
;
1606 __cpu_name
[cpu
] = "Broadcom XLPII";
1609 case PRID_IMP_NETLOGIC_XLP8XX
:
1610 case PRID_IMP_NETLOGIC_XLP3XX
:
1611 c
->cputype
= CPU_XLP
;
1612 __cpu_name
[cpu
] = "Netlogic XLP";
1615 case PRID_IMP_NETLOGIC_XLR732
:
1616 case PRID_IMP_NETLOGIC_XLR716
:
1617 case PRID_IMP_NETLOGIC_XLR532
:
1618 case PRID_IMP_NETLOGIC_XLR308
:
1619 case PRID_IMP_NETLOGIC_XLR532C
:
1620 case PRID_IMP_NETLOGIC_XLR516C
:
1621 case PRID_IMP_NETLOGIC_XLR508C
:
1622 case PRID_IMP_NETLOGIC_XLR308C
:
1623 c
->cputype
= CPU_XLR
;
1624 __cpu_name
[cpu
] = "Netlogic XLR";
1627 case PRID_IMP_NETLOGIC_XLS608
:
1628 case PRID_IMP_NETLOGIC_XLS408
:
1629 case PRID_IMP_NETLOGIC_XLS404
:
1630 case PRID_IMP_NETLOGIC_XLS208
:
1631 case PRID_IMP_NETLOGIC_XLS204
:
1632 case PRID_IMP_NETLOGIC_XLS108
:
1633 case PRID_IMP_NETLOGIC_XLS104
:
1634 case PRID_IMP_NETLOGIC_XLS616B
:
1635 case PRID_IMP_NETLOGIC_XLS608B
:
1636 case PRID_IMP_NETLOGIC_XLS416B
:
1637 case PRID_IMP_NETLOGIC_XLS412B
:
1638 case PRID_IMP_NETLOGIC_XLS408B
:
1639 case PRID_IMP_NETLOGIC_XLS404B
:
1640 c
->cputype
= CPU_XLR
;
1641 __cpu_name
[cpu
] = "Netlogic XLS";
1645 pr_info("Unknown Netlogic chip id [%02x]!\n",
1647 c
->cputype
= CPU_XLR
;
1651 if (c
->cputype
== CPU_XLP
) {
1652 set_isa(c
, MIPS_CPU_ISA_M64R2
);
1653 c
->options
|= (MIPS_CPU_FPU
| MIPS_CPU_ULRI
| MIPS_CPU_MCHECK
);
1654 /* This will be updated again after all threads are woken up */
1655 c
->tlbsize
= ((read_c0_config6() >> 16) & 0xffff) + 1;
1657 set_isa(c
, MIPS_CPU_ISA_M64R1
);
1658 c
->tlbsize
= ((read_c0_config1() >> 25) & 0x3f) + 1;
1660 c
->kscratch_mask
= 0xf;
1664 /* For use by uaccess.h */
1666 EXPORT_SYMBOL(__ua_limit
);
1669 const char *__cpu_name
[NR_CPUS
];
1670 const char *__elf_platform
;
1672 void cpu_probe(void)
1674 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1675 unsigned int cpu
= smp_processor_id();
1677 c
->processor_id
= PRID_IMP_UNKNOWN
;
1678 c
->fpu_id
= FPIR_IMP_NONE
;
1679 c
->cputype
= CPU_UNKNOWN
;
1680 c
->writecombine
= _CACHE_UNCACHED
;
1682 c
->fpu_csr31
= FPU_CSR_RN
;
1683 c
->fpu_msk31
= FPU_CSR_RSVD
| FPU_CSR_ABS2008
| FPU_CSR_NAN2008
;
1685 c
->processor_id
= read_c0_prid();
1686 switch (c
->processor_id
& PRID_COMP_MASK
) {
1687 case PRID_COMP_LEGACY
:
1688 cpu_probe_legacy(c
, cpu
);
1690 case PRID_COMP_MIPS
:
1691 cpu_probe_mips(c
, cpu
);
1693 case PRID_COMP_ALCHEMY
:
1694 cpu_probe_alchemy(c
, cpu
);
1696 case PRID_COMP_SIBYTE
:
1697 cpu_probe_sibyte(c
, cpu
);
1699 case PRID_COMP_BROADCOM
:
1700 cpu_probe_broadcom(c
, cpu
);
1702 case PRID_COMP_SANDCRAFT
:
1703 cpu_probe_sandcraft(c
, cpu
);
1706 cpu_probe_nxp(c
, cpu
);
1708 case PRID_COMP_CAVIUM
:
1709 cpu_probe_cavium(c
, cpu
);
1711 case PRID_COMP_LOONGSON
:
1712 cpu_probe_loongson(c
, cpu
);
1714 case PRID_COMP_INGENIC_D0
:
1715 case PRID_COMP_INGENIC_D1
:
1716 case PRID_COMP_INGENIC_E1
:
1717 cpu_probe_ingenic(c
, cpu
);
1719 case PRID_COMP_NETLOGIC
:
1720 cpu_probe_netlogic(c
, cpu
);
1724 BUG_ON(!__cpu_name
[cpu
]);
1725 BUG_ON(c
->cputype
== CPU_UNKNOWN
);
1728 * Platform code can force the cpu type to optimize code
1729 * generation. In that case be sure the cpu type is correctly
1730 * manually setup otherwise it could trigger some nasty bugs.
1732 BUG_ON(current_cpu_type() != c
->cputype
);
1734 if (mips_fpu_disabled
)
1735 c
->options
&= ~MIPS_CPU_FPU
;
1737 if (mips_dsp_disabled
)
1738 c
->ases
&= ~(MIPS_ASE_DSP
| MIPS_ASE_DSP2P
);
1740 if (mips_htw_disabled
) {
1741 c
->options
&= ~MIPS_CPU_HTW
;
1742 write_c0_pwctl(read_c0_pwctl() &
1743 ~(1 << MIPS_PWCTL_PWEN_SHIFT
));
1746 if (c
->options
& MIPS_CPU_FPU
)
1747 cpu_set_fpu_opts(c
);
1749 cpu_set_nofpu_opts(c
);
1751 if (cpu_has_bp_ghist
)
1752 write_c0_r10k_diag(read_c0_r10k_diag() |
1755 if (cpu_has_mips_r2_r6
) {
1756 c
->srsets
= ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1757 /* R2 has Performance Counter Interrupt indicator */
1758 c
->options
|= MIPS_CPU_PCI
;
1763 if (cpu_has_mips_r6
)
1764 elf_hwcap
|= HWCAP_MIPS_R6
;
1767 c
->msa_id
= cpu_get_msa_id();
1768 WARN(c
->msa_id
& MSA_IR_WRPF
,
1769 "Vector register partitioning unimplemented!");
1770 elf_hwcap
|= HWCAP_MIPS_MSA
;
1773 cpu_probe_vmbits(c
);
1777 __ua_limit
= ~((1ull << cpu_vmbits
) - 1);
1781 void cpu_report(void)
1783 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1785 pr_info("CPU%d revision is: %08x (%s)\n",
1786 smp_processor_id(), c
->processor_id
, cpu_name_string());
1787 if (c
->options
& MIPS_CPU_FPU
)
1788 printk(KERN_INFO
"FPU revision is: %08x\n", c
->fpu_id
);
1790 pr_info("MSA revision is: %08x\n", c
->msa_id
);