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MIPS: Support extended ASIDs
[mirror_ubuntu-eoan-kernel.git] / arch / mips / kernel / cpu-probe.c
1 /*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
20
21 #include <asm/bugs.h>
22 #include <asm/cpu.h>
23 #include <asm/cpu-features.h>
24 #include <asm/cpu-type.h>
25 #include <asm/fpu.h>
26 #include <asm/mipsregs.h>
27 #include <asm/mipsmtregs.h>
28 #include <asm/msa.h>
29 #include <asm/watch.h>
30 #include <asm/elf.h>
31 #include <asm/pgtable-bits.h>
32 #include <asm/spram.h>
33 #include <asm/uaccess.h>
34
35 /* Hardware capabilities */
36 unsigned int elf_hwcap __read_mostly;
37
38 /*
39 * Get the FPU Implementation/Revision.
40 */
41 static inline unsigned long cpu_get_fpu_id(void)
42 {
43 unsigned long tmp, fpu_id;
44
45 tmp = read_c0_status();
46 __enable_fpu(FPU_AS_IS);
47 fpu_id = read_32bit_cp1_register(CP1_REVISION);
48 write_c0_status(tmp);
49 return fpu_id;
50 }
51
52 /*
53 * Check if the CPU has an external FPU.
54 */
55 static inline int __cpu_has_fpu(void)
56 {
57 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
58 }
59
60 static inline unsigned long cpu_get_msa_id(void)
61 {
62 unsigned long status, msa_id;
63
64 status = read_c0_status();
65 __enable_fpu(FPU_64BIT);
66 enable_msa();
67 msa_id = read_msa_ir();
68 disable_msa();
69 write_c0_status(status);
70 return msa_id;
71 }
72
73 /*
74 * Determine the FCSR mask for FPU hardware.
75 */
76 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
77 {
78 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
79
80 fcsr = c->fpu_csr31;
81 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
82
83 sr = read_c0_status();
84 __enable_fpu(FPU_AS_IS);
85
86 fcsr0 = fcsr & mask;
87 write_32bit_cp1_register(CP1_STATUS, fcsr0);
88 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
89
90 fcsr1 = fcsr | ~mask;
91 write_32bit_cp1_register(CP1_STATUS, fcsr1);
92 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
93
94 write_32bit_cp1_register(CP1_STATUS, fcsr);
95
96 write_c0_status(sr);
97
98 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
99 }
100
101 /*
102 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
103 * supported by FPU hardware.
104 */
105 static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
106 {
107 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
108 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
109 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
110 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
111
112 sr = read_c0_status();
113 __enable_fpu(FPU_AS_IS);
114
115 fir = read_32bit_cp1_register(CP1_REVISION);
116 if (fir & MIPS_FPIR_HAS2008) {
117 fcsr = read_32bit_cp1_register(CP1_STATUS);
118
119 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
120 write_32bit_cp1_register(CP1_STATUS, fcsr0);
121 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
122
123 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
124 write_32bit_cp1_register(CP1_STATUS, fcsr1);
125 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
126
127 write_32bit_cp1_register(CP1_STATUS, fcsr);
128
129 if (!(fcsr0 & FPU_CSR_NAN2008))
130 c->options |= MIPS_CPU_NAN_LEGACY;
131 if (fcsr1 & FPU_CSR_NAN2008)
132 c->options |= MIPS_CPU_NAN_2008;
133
134 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
135 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
136 else
137 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
138
139 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
140 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
141 else
142 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
143 } else {
144 c->options |= MIPS_CPU_NAN_LEGACY;
145 }
146
147 write_c0_status(sr);
148 } else {
149 c->options |= MIPS_CPU_NAN_LEGACY;
150 }
151 }
152
153 /*
154 * IEEE 754 conformance mode to use. Affects the NaN encoding and the
155 * ABS.fmt/NEG.fmt execution mode.
156 */
157 static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
158
159 /*
160 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
161 * to support by the FPU emulator according to the IEEE 754 conformance
162 * mode selected. Note that "relaxed" straps the emulator so that it
163 * allows 2008-NaN binaries even for legacy processors.
164 */
165 static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
166 {
167 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
168 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
169 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
170
171 switch (ieee754) {
172 case STRICT:
173 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
174 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
175 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
176 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
177 } else {
178 c->options |= MIPS_CPU_NAN_LEGACY;
179 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
180 }
181 break;
182 case LEGACY:
183 c->options |= MIPS_CPU_NAN_LEGACY;
184 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
185 break;
186 case STD2008:
187 c->options |= MIPS_CPU_NAN_2008;
188 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
189 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
190 break;
191 case RELAXED:
192 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
193 break;
194 }
195 }
196
197 /*
198 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
199 * according to the "ieee754=" parameter.
200 */
201 static void cpu_set_nan_2008(struct cpuinfo_mips *c)
202 {
203 switch (ieee754) {
204 case STRICT:
205 mips_use_nan_legacy = !!cpu_has_nan_legacy;
206 mips_use_nan_2008 = !!cpu_has_nan_2008;
207 break;
208 case LEGACY:
209 mips_use_nan_legacy = !!cpu_has_nan_legacy;
210 mips_use_nan_2008 = !cpu_has_nan_legacy;
211 break;
212 case STD2008:
213 mips_use_nan_legacy = !cpu_has_nan_2008;
214 mips_use_nan_2008 = !!cpu_has_nan_2008;
215 break;
216 case RELAXED:
217 mips_use_nan_legacy = true;
218 mips_use_nan_2008 = true;
219 break;
220 }
221 }
222
223 /*
224 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
225 * settings:
226 *
227 * strict: accept binaries that request a NaN encoding supported by the FPU
228 * legacy: only accept legacy-NaN binaries
229 * 2008: only accept 2008-NaN binaries
230 * relaxed: accept any binaries regardless of whether supported by the FPU
231 */
232 static int __init ieee754_setup(char *s)
233 {
234 if (!s)
235 return -1;
236 else if (!strcmp(s, "strict"))
237 ieee754 = STRICT;
238 else if (!strcmp(s, "legacy"))
239 ieee754 = LEGACY;
240 else if (!strcmp(s, "2008"))
241 ieee754 = STD2008;
242 else if (!strcmp(s, "relaxed"))
243 ieee754 = RELAXED;
244 else
245 return -1;
246
247 if (!(boot_cpu_data.options & MIPS_CPU_FPU))
248 cpu_set_nofpu_2008(&boot_cpu_data);
249 cpu_set_nan_2008(&boot_cpu_data);
250
251 return 0;
252 }
253
254 early_param("ieee754", ieee754_setup);
255
256 /*
257 * Set the FIR feature flags for the FPU emulator.
258 */
259 static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
260 {
261 u32 value;
262
263 value = 0;
264 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
265 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
266 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
267 value |= MIPS_FPIR_D | MIPS_FPIR_S;
268 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
269 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
270 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
271 if (c->options & MIPS_CPU_NAN_2008)
272 value |= MIPS_FPIR_HAS2008;
273 c->fpu_id = value;
274 }
275
276 /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
277 static unsigned int mips_nofpu_msk31;
278
279 /*
280 * Set options for FPU hardware.
281 */
282 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
283 {
284 c->fpu_id = cpu_get_fpu_id();
285 mips_nofpu_msk31 = c->fpu_msk31;
286
287 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
288 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
289 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
290 if (c->fpu_id & MIPS_FPIR_3D)
291 c->ases |= MIPS_ASE_MIPS3D;
292 if (c->fpu_id & MIPS_FPIR_FREP)
293 c->options |= MIPS_CPU_FRE;
294 }
295
296 cpu_set_fpu_fcsr_mask(c);
297 cpu_set_fpu_2008(c);
298 cpu_set_nan_2008(c);
299 }
300
301 /*
302 * Set options for the FPU emulator.
303 */
304 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
305 {
306 c->options &= ~MIPS_CPU_FPU;
307 c->fpu_msk31 = mips_nofpu_msk31;
308
309 cpu_set_nofpu_2008(c);
310 cpu_set_nan_2008(c);
311 cpu_set_nofpu_id(c);
312 }
313
314 static int mips_fpu_disabled;
315
316 static int __init fpu_disable(char *s)
317 {
318 cpu_set_nofpu_opts(&boot_cpu_data);
319 mips_fpu_disabled = 1;
320
321 return 1;
322 }
323
324 __setup("nofpu", fpu_disable);
325
326 int mips_dsp_disabled;
327
328 static int __init dsp_disable(char *s)
329 {
330 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
331 mips_dsp_disabled = 1;
332
333 return 1;
334 }
335
336 __setup("nodsp", dsp_disable);
337
338 static int mips_htw_disabled;
339
340 static int __init htw_disable(char *s)
341 {
342 mips_htw_disabled = 1;
343 cpu_data[0].options &= ~MIPS_CPU_HTW;
344 write_c0_pwctl(read_c0_pwctl() &
345 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
346
347 return 1;
348 }
349
350 __setup("nohtw", htw_disable);
351
352 static int mips_ftlb_disabled;
353 static int mips_has_ftlb_configured;
354
355 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable);
356
357 static int __init ftlb_disable(char *s)
358 {
359 unsigned int config4, mmuextdef;
360
361 /*
362 * If the core hasn't done any FTLB configuration, there is nothing
363 * for us to do here.
364 */
365 if (!mips_has_ftlb_configured)
366 return 1;
367
368 /* Disable it in the boot cpu */
369 if (set_ftlb_enable(&cpu_data[0], 0)) {
370 pr_warn("Can't turn FTLB off\n");
371 return 1;
372 }
373
374 back_to_back_c0_hazard();
375
376 config4 = read_c0_config4();
377
378 /* Check that FTLB has been disabled */
379 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
380 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
381 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
382 /* This should never happen */
383 pr_warn("FTLB could not be disabled!\n");
384 return 1;
385 }
386
387 mips_ftlb_disabled = 1;
388 mips_has_ftlb_configured = 0;
389
390 /*
391 * noftlb is mainly used for debug purposes so print
392 * an informative message instead of using pr_debug()
393 */
394 pr_info("FTLB has been disabled\n");
395
396 /*
397 * Some of these bits are duplicated in the decode_config4.
398 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
399 * once FTLB has been disabled so undo what decode_config4 did.
400 */
401 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
402 cpu_data[0].tlbsizeftlbsets;
403 cpu_data[0].tlbsizeftlbsets = 0;
404 cpu_data[0].tlbsizeftlbways = 0;
405
406 return 1;
407 }
408
409 __setup("noftlb", ftlb_disable);
410
411
412 static inline void check_errata(void)
413 {
414 struct cpuinfo_mips *c = &current_cpu_data;
415
416 switch (current_cpu_type()) {
417 case CPU_34K:
418 /*
419 * Erratum "RPS May Cause Incorrect Instruction Execution"
420 * This code only handles VPE0, any SMP/RTOS code
421 * making use of VPE1 will be responsable for that VPE.
422 */
423 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
424 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
425 break;
426 default:
427 break;
428 }
429 }
430
431 void __init check_bugs32(void)
432 {
433 check_errata();
434 }
435
436 /*
437 * Probe whether cpu has config register by trying to play with
438 * alternate cache bit and see whether it matters.
439 * It's used by cpu_probe to distinguish between R3000A and R3081.
440 */
441 static inline int cpu_has_confreg(void)
442 {
443 #ifdef CONFIG_CPU_R3000
444 extern unsigned long r3k_cache_size(unsigned long);
445 unsigned long size1, size2;
446 unsigned long cfg = read_c0_conf();
447
448 size1 = r3k_cache_size(ST0_ISC);
449 write_c0_conf(cfg ^ R30XX_CONF_AC);
450 size2 = r3k_cache_size(ST0_ISC);
451 write_c0_conf(cfg);
452 return size1 != size2;
453 #else
454 return 0;
455 #endif
456 }
457
458 static inline void set_elf_platform(int cpu, const char *plat)
459 {
460 if (cpu == 0)
461 __elf_platform = plat;
462 }
463
464 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
465 {
466 #ifdef __NEED_VMBITS_PROBE
467 write_c0_entryhi(0x3fffffffffffe000ULL);
468 back_to_back_c0_hazard();
469 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
470 #endif
471 }
472
473 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
474 {
475 switch (isa) {
476 case MIPS_CPU_ISA_M64R2:
477 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
478 case MIPS_CPU_ISA_M64R1:
479 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
480 case MIPS_CPU_ISA_V:
481 c->isa_level |= MIPS_CPU_ISA_V;
482 case MIPS_CPU_ISA_IV:
483 c->isa_level |= MIPS_CPU_ISA_IV;
484 case MIPS_CPU_ISA_III:
485 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
486 break;
487
488 /* R6 incompatible with everything else */
489 case MIPS_CPU_ISA_M64R6:
490 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
491 case MIPS_CPU_ISA_M32R6:
492 c->isa_level |= MIPS_CPU_ISA_M32R6;
493 /* Break here so we don't add incompatible ISAs */
494 break;
495 case MIPS_CPU_ISA_M32R2:
496 c->isa_level |= MIPS_CPU_ISA_M32R2;
497 case MIPS_CPU_ISA_M32R1:
498 c->isa_level |= MIPS_CPU_ISA_M32R1;
499 case MIPS_CPU_ISA_II:
500 c->isa_level |= MIPS_CPU_ISA_II;
501 break;
502 }
503 }
504
505 static char unknown_isa[] = KERN_ERR \
506 "Unsupported ISA type, c0.config0: %d.";
507
508 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
509 {
510
511 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
512
513 /*
514 * 0 = All TLBWR instructions go to FTLB
515 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
516 * FTLB and 1 goes to the VTLB.
517 * 2 = 7:1: As above with 7:1 ratio.
518 * 3 = 3:1: As above with 3:1 ratio.
519 *
520 * Use the linear midpoint as the probability threshold.
521 */
522 if (probability >= 12)
523 return 1;
524 else if (probability >= 6)
525 return 2;
526 else
527 /*
528 * So FTLB is less than 4 times bigger than VTLB.
529 * A 3:1 ratio can still be useful though.
530 */
531 return 3;
532 }
533
534 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
535 {
536 unsigned int config;
537
538 /* It's implementation dependent how the FTLB can be enabled */
539 switch (c->cputype) {
540 case CPU_PROAPTIV:
541 case CPU_P5600:
542 case CPU_P6600:
543 /* proAptiv & related cores use Config6 to enable the FTLB */
544 config = read_c0_config6();
545 /* Clear the old probability value */
546 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
547 if (enable)
548 /* Enable FTLB */
549 write_c0_config6(config |
550 (calculate_ftlb_probability(c)
551 << MIPS_CONF6_FTLBP_SHIFT)
552 | MIPS_CONF6_FTLBEN);
553 else
554 /* Disable FTLB */
555 write_c0_config6(config & ~MIPS_CONF6_FTLBEN);
556 break;
557 case CPU_I6400:
558 /* I6400 & related cores use Config7 to configure FTLB */
559 config = read_c0_config7();
560 /* Clear the old probability value */
561 config &= ~(3 << MIPS_CONF7_FTLBP_SHIFT);
562 write_c0_config7(config | (calculate_ftlb_probability(c)
563 << MIPS_CONF7_FTLBP_SHIFT));
564 break;
565 case CPU_LOONGSON3:
566 /* Flush ITLB, DTLB, VTLB and FTLB */
567 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
568 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
569 /* Loongson-3 cores use Config6 to enable the FTLB */
570 config = read_c0_config6();
571 if (enable)
572 /* Enable FTLB */
573 write_c0_config6(config & ~MIPS_CONF6_FTLBDIS);
574 else
575 /* Disable FTLB */
576 write_c0_config6(config | MIPS_CONF6_FTLBDIS);
577 break;
578 default:
579 return 1;
580 }
581
582 return 0;
583 }
584
585 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
586 {
587 unsigned int config0;
588 int isa, mt;
589
590 config0 = read_c0_config();
591
592 /*
593 * Look for Standard TLB or Dual VTLB and FTLB
594 */
595 mt = config0 & MIPS_CONF_MT;
596 if (mt == MIPS_CONF_MT_TLB)
597 c->options |= MIPS_CPU_TLB;
598 else if (mt == MIPS_CONF_MT_FTLB)
599 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
600
601 isa = (config0 & MIPS_CONF_AT) >> 13;
602 switch (isa) {
603 case 0:
604 switch ((config0 & MIPS_CONF_AR) >> 10) {
605 case 0:
606 set_isa(c, MIPS_CPU_ISA_M32R1);
607 break;
608 case 1:
609 set_isa(c, MIPS_CPU_ISA_M32R2);
610 break;
611 case 2:
612 set_isa(c, MIPS_CPU_ISA_M32R6);
613 break;
614 default:
615 goto unknown;
616 }
617 break;
618 case 2:
619 switch ((config0 & MIPS_CONF_AR) >> 10) {
620 case 0:
621 set_isa(c, MIPS_CPU_ISA_M64R1);
622 break;
623 case 1:
624 set_isa(c, MIPS_CPU_ISA_M64R2);
625 break;
626 case 2:
627 set_isa(c, MIPS_CPU_ISA_M64R6);
628 break;
629 default:
630 goto unknown;
631 }
632 break;
633 default:
634 goto unknown;
635 }
636
637 return config0 & MIPS_CONF_M;
638
639 unknown:
640 panic(unknown_isa, config0);
641 }
642
643 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
644 {
645 unsigned int config1;
646
647 config1 = read_c0_config1();
648
649 if (config1 & MIPS_CONF1_MD)
650 c->ases |= MIPS_ASE_MDMX;
651 if (config1 & MIPS_CONF1_WR)
652 c->options |= MIPS_CPU_WATCH;
653 if (config1 & MIPS_CONF1_CA)
654 c->ases |= MIPS_ASE_MIPS16;
655 if (config1 & MIPS_CONF1_EP)
656 c->options |= MIPS_CPU_EJTAG;
657 if (config1 & MIPS_CONF1_FP) {
658 c->options |= MIPS_CPU_FPU;
659 c->options |= MIPS_CPU_32FPR;
660 }
661 if (cpu_has_tlb) {
662 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
663 c->tlbsizevtlb = c->tlbsize;
664 c->tlbsizeftlbsets = 0;
665 }
666
667 return config1 & MIPS_CONF_M;
668 }
669
670 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
671 {
672 unsigned int config2;
673
674 config2 = read_c0_config2();
675
676 if (config2 & MIPS_CONF2_SL)
677 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
678
679 return config2 & MIPS_CONF_M;
680 }
681
682 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
683 {
684 unsigned int config3;
685
686 config3 = read_c0_config3();
687
688 if (config3 & MIPS_CONF3_SM) {
689 c->ases |= MIPS_ASE_SMARTMIPS;
690 c->options |= MIPS_CPU_RIXI;
691 }
692 if (config3 & MIPS_CONF3_RXI)
693 c->options |= MIPS_CPU_RIXI;
694 if (config3 & MIPS_CONF3_DSP)
695 c->ases |= MIPS_ASE_DSP;
696 if (config3 & MIPS_CONF3_DSP2P) {
697 c->ases |= MIPS_ASE_DSP2P;
698 if (cpu_has_mips_r6)
699 c->ases |= MIPS_ASE_DSP3;
700 }
701 if (config3 & MIPS_CONF3_VINT)
702 c->options |= MIPS_CPU_VINT;
703 if (config3 & MIPS_CONF3_VEIC)
704 c->options |= MIPS_CPU_VEIC;
705 if (config3 & MIPS_CONF3_MT)
706 c->ases |= MIPS_ASE_MIPSMT;
707 if (config3 & MIPS_CONF3_ULRI)
708 c->options |= MIPS_CPU_ULRI;
709 if (config3 & MIPS_CONF3_ISA)
710 c->options |= MIPS_CPU_MICROMIPS;
711 if (config3 & MIPS_CONF3_VZ)
712 c->ases |= MIPS_ASE_VZ;
713 if (config3 & MIPS_CONF3_SC)
714 c->options |= MIPS_CPU_SEGMENTS;
715 if (config3 & MIPS_CONF3_MSA)
716 c->ases |= MIPS_ASE_MSA;
717 if (config3 & MIPS_CONF3_PW) {
718 c->htw_seq = 0;
719 c->options |= MIPS_CPU_HTW;
720 }
721 if (config3 & MIPS_CONF3_CDMM)
722 c->options |= MIPS_CPU_CDMM;
723 if (config3 & MIPS_CONF3_SP)
724 c->options |= MIPS_CPU_SP;
725
726 return config3 & MIPS_CONF_M;
727 }
728
729 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
730 {
731 unsigned int config4;
732 unsigned int newcf4;
733 unsigned int mmuextdef;
734 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
735 unsigned long asid_mask;
736
737 config4 = read_c0_config4();
738
739 if (cpu_has_tlb) {
740 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
741 c->options |= MIPS_CPU_TLBINV;
742
743 /*
744 * R6 has dropped the MMUExtDef field from config4.
745 * On R6 the fields always describe the FTLB, and only if it is
746 * present according to Config.MT.
747 */
748 if (!cpu_has_mips_r6)
749 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
750 else if (cpu_has_ftlb)
751 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
752 else
753 mmuextdef = 0;
754
755 switch (mmuextdef) {
756 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
757 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
758 c->tlbsizevtlb = c->tlbsize;
759 break;
760 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
761 c->tlbsizevtlb +=
762 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
763 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
764 c->tlbsize = c->tlbsizevtlb;
765 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
766 /* fall through */
767 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
768 if (mips_ftlb_disabled)
769 break;
770 newcf4 = (config4 & ~ftlb_page) |
771 (page_size_ftlb(mmuextdef) <<
772 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
773 write_c0_config4(newcf4);
774 back_to_back_c0_hazard();
775 config4 = read_c0_config4();
776 if (config4 != newcf4) {
777 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
778 PAGE_SIZE, config4);
779 /* Switch FTLB off */
780 set_ftlb_enable(c, 0);
781 break;
782 }
783 c->tlbsizeftlbsets = 1 <<
784 ((config4 & MIPS_CONF4_FTLBSETS) >>
785 MIPS_CONF4_FTLBSETS_SHIFT);
786 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
787 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
788 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
789 mips_has_ftlb_configured = 1;
790 break;
791 }
792 }
793
794 c->kscratch_mask = (config4 >> 16) & 0xff;
795
796 asid_mask = MIPS_ENTRYHI_ASID;
797 if (config4 & MIPS_CONF4_AE)
798 asid_mask |= MIPS_ENTRYHI_ASIDX;
799 set_cpu_asid_mask(c, asid_mask);
800
801 /*
802 * Warn if the computed ASID mask doesn't match the mask the kernel
803 * is built for. This may indicate either a serious problem or an
804 * easy optimisation opportunity, but either way should be addressed.
805 */
806 WARN_ON(asid_mask != cpu_asid_mask(c));
807
808 return config4 & MIPS_CONF_M;
809 }
810
811 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
812 {
813 unsigned int config5;
814
815 config5 = read_c0_config5();
816 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
817 write_c0_config5(config5);
818
819 if (config5 & MIPS_CONF5_EVA)
820 c->options |= MIPS_CPU_EVA;
821 if (config5 & MIPS_CONF5_MRP)
822 c->options |= MIPS_CPU_MAAR;
823 if (config5 & MIPS_CONF5_LLB)
824 c->options |= MIPS_CPU_RW_LLB;
825 #ifdef CONFIG_XPA
826 if (config5 & MIPS_CONF5_MVH)
827 c->options |= MIPS_CPU_XPA;
828 #endif
829 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
830 c->options |= MIPS_CPU_VP;
831
832 return config5 & MIPS_CONF_M;
833 }
834
835 static void decode_configs(struct cpuinfo_mips *c)
836 {
837 int ok;
838
839 /* MIPS32 or MIPS64 compliant CPU. */
840 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
841 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
842
843 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
844
845 /* Enable FTLB if present and not disabled */
846 set_ftlb_enable(c, !mips_ftlb_disabled);
847
848 ok = decode_config0(c); /* Read Config registers. */
849 BUG_ON(!ok); /* Arch spec violation! */
850 if (ok)
851 ok = decode_config1(c);
852 if (ok)
853 ok = decode_config2(c);
854 if (ok)
855 ok = decode_config3(c);
856 if (ok)
857 ok = decode_config4(c);
858 if (ok)
859 ok = decode_config5(c);
860
861 mips_probe_watch_registers(c);
862
863 if (cpu_has_rixi) {
864 /* Enable the RIXI exceptions */
865 set_c0_pagegrain(PG_IEC);
866 back_to_back_c0_hazard();
867 /* Verify the IEC bit is set */
868 if (read_c0_pagegrain() & PG_IEC)
869 c->options |= MIPS_CPU_RIXIEX;
870 }
871
872 #ifndef CONFIG_MIPS_CPS
873 if (cpu_has_mips_r2_r6) {
874 c->core = get_ebase_cpunum();
875 if (cpu_has_mipsmt)
876 c->core >>= fls(core_nvpes()) - 1;
877 }
878 #endif
879 }
880
881 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
882 | MIPS_CPU_COUNTER)
883
884 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
885 {
886 switch (c->processor_id & PRID_IMP_MASK) {
887 case PRID_IMP_R2000:
888 c->cputype = CPU_R2000;
889 __cpu_name[cpu] = "R2000";
890 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
891 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
892 MIPS_CPU_NOFPUEX;
893 if (__cpu_has_fpu())
894 c->options |= MIPS_CPU_FPU;
895 c->tlbsize = 64;
896 break;
897 case PRID_IMP_R3000:
898 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
899 if (cpu_has_confreg()) {
900 c->cputype = CPU_R3081E;
901 __cpu_name[cpu] = "R3081";
902 } else {
903 c->cputype = CPU_R3000A;
904 __cpu_name[cpu] = "R3000A";
905 }
906 } else {
907 c->cputype = CPU_R3000;
908 __cpu_name[cpu] = "R3000";
909 }
910 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
911 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
912 MIPS_CPU_NOFPUEX;
913 if (__cpu_has_fpu())
914 c->options |= MIPS_CPU_FPU;
915 c->tlbsize = 64;
916 break;
917 case PRID_IMP_R4000:
918 if (read_c0_config() & CONF_SC) {
919 if ((c->processor_id & PRID_REV_MASK) >=
920 PRID_REV_R4400) {
921 c->cputype = CPU_R4400PC;
922 __cpu_name[cpu] = "R4400PC";
923 } else {
924 c->cputype = CPU_R4000PC;
925 __cpu_name[cpu] = "R4000PC";
926 }
927 } else {
928 int cca = read_c0_config() & CONF_CM_CMASK;
929 int mc;
930
931 /*
932 * SC and MC versions can't be reliably told apart,
933 * but only the latter support coherent caching
934 * modes so assume the firmware has set the KSEG0
935 * coherency attribute reasonably (if uncached, we
936 * assume SC).
937 */
938 switch (cca) {
939 case CONF_CM_CACHABLE_CE:
940 case CONF_CM_CACHABLE_COW:
941 case CONF_CM_CACHABLE_CUW:
942 mc = 1;
943 break;
944 default:
945 mc = 0;
946 break;
947 }
948 if ((c->processor_id & PRID_REV_MASK) >=
949 PRID_REV_R4400) {
950 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
951 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
952 } else {
953 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
954 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
955 }
956 }
957
958 set_isa(c, MIPS_CPU_ISA_III);
959 c->fpu_msk31 |= FPU_CSR_CONDX;
960 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
961 MIPS_CPU_WATCH | MIPS_CPU_VCE |
962 MIPS_CPU_LLSC;
963 c->tlbsize = 48;
964 break;
965 case PRID_IMP_VR41XX:
966 set_isa(c, MIPS_CPU_ISA_III);
967 c->fpu_msk31 |= FPU_CSR_CONDX;
968 c->options = R4K_OPTS;
969 c->tlbsize = 32;
970 switch (c->processor_id & 0xf0) {
971 case PRID_REV_VR4111:
972 c->cputype = CPU_VR4111;
973 __cpu_name[cpu] = "NEC VR4111";
974 break;
975 case PRID_REV_VR4121:
976 c->cputype = CPU_VR4121;
977 __cpu_name[cpu] = "NEC VR4121";
978 break;
979 case PRID_REV_VR4122:
980 if ((c->processor_id & 0xf) < 0x3) {
981 c->cputype = CPU_VR4122;
982 __cpu_name[cpu] = "NEC VR4122";
983 } else {
984 c->cputype = CPU_VR4181A;
985 __cpu_name[cpu] = "NEC VR4181A";
986 }
987 break;
988 case PRID_REV_VR4130:
989 if ((c->processor_id & 0xf) < 0x4) {
990 c->cputype = CPU_VR4131;
991 __cpu_name[cpu] = "NEC VR4131";
992 } else {
993 c->cputype = CPU_VR4133;
994 c->options |= MIPS_CPU_LLSC;
995 __cpu_name[cpu] = "NEC VR4133";
996 }
997 break;
998 default:
999 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
1000 c->cputype = CPU_VR41XX;
1001 __cpu_name[cpu] = "NEC Vr41xx";
1002 break;
1003 }
1004 break;
1005 case PRID_IMP_R4300:
1006 c->cputype = CPU_R4300;
1007 __cpu_name[cpu] = "R4300";
1008 set_isa(c, MIPS_CPU_ISA_III);
1009 c->fpu_msk31 |= FPU_CSR_CONDX;
1010 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1011 MIPS_CPU_LLSC;
1012 c->tlbsize = 32;
1013 break;
1014 case PRID_IMP_R4600:
1015 c->cputype = CPU_R4600;
1016 __cpu_name[cpu] = "R4600";
1017 set_isa(c, MIPS_CPU_ISA_III);
1018 c->fpu_msk31 |= FPU_CSR_CONDX;
1019 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1020 MIPS_CPU_LLSC;
1021 c->tlbsize = 48;
1022 break;
1023 #if 0
1024 case PRID_IMP_R4650:
1025 /*
1026 * This processor doesn't have an MMU, so it's not
1027 * "real easy" to run Linux on it. It is left purely
1028 * for documentation. Commented out because it shares
1029 * it's c0_prid id number with the TX3900.
1030 */
1031 c->cputype = CPU_R4650;
1032 __cpu_name[cpu] = "R4650";
1033 set_isa(c, MIPS_CPU_ISA_III);
1034 c->fpu_msk31 |= FPU_CSR_CONDX;
1035 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
1036 c->tlbsize = 48;
1037 break;
1038 #endif
1039 case PRID_IMP_TX39:
1040 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1041 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1042
1043 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1044 c->cputype = CPU_TX3927;
1045 __cpu_name[cpu] = "TX3927";
1046 c->tlbsize = 64;
1047 } else {
1048 switch (c->processor_id & PRID_REV_MASK) {
1049 case PRID_REV_TX3912:
1050 c->cputype = CPU_TX3912;
1051 __cpu_name[cpu] = "TX3912";
1052 c->tlbsize = 32;
1053 break;
1054 case PRID_REV_TX3922:
1055 c->cputype = CPU_TX3922;
1056 __cpu_name[cpu] = "TX3922";
1057 c->tlbsize = 64;
1058 break;
1059 }
1060 }
1061 break;
1062 case PRID_IMP_R4700:
1063 c->cputype = CPU_R4700;
1064 __cpu_name[cpu] = "R4700";
1065 set_isa(c, MIPS_CPU_ISA_III);
1066 c->fpu_msk31 |= FPU_CSR_CONDX;
1067 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1068 MIPS_CPU_LLSC;
1069 c->tlbsize = 48;
1070 break;
1071 case PRID_IMP_TX49:
1072 c->cputype = CPU_TX49XX;
1073 __cpu_name[cpu] = "R49XX";
1074 set_isa(c, MIPS_CPU_ISA_III);
1075 c->fpu_msk31 |= FPU_CSR_CONDX;
1076 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1077 if (!(c->processor_id & 0x08))
1078 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1079 c->tlbsize = 48;
1080 break;
1081 case PRID_IMP_R5000:
1082 c->cputype = CPU_R5000;
1083 __cpu_name[cpu] = "R5000";
1084 set_isa(c, MIPS_CPU_ISA_IV);
1085 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1086 MIPS_CPU_LLSC;
1087 c->tlbsize = 48;
1088 break;
1089 case PRID_IMP_R5432:
1090 c->cputype = CPU_R5432;
1091 __cpu_name[cpu] = "R5432";
1092 set_isa(c, MIPS_CPU_ISA_IV);
1093 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1094 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1095 c->tlbsize = 48;
1096 break;
1097 case PRID_IMP_R5500:
1098 c->cputype = CPU_R5500;
1099 __cpu_name[cpu] = "R5500";
1100 set_isa(c, MIPS_CPU_ISA_IV);
1101 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1102 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1103 c->tlbsize = 48;
1104 break;
1105 case PRID_IMP_NEVADA:
1106 c->cputype = CPU_NEVADA;
1107 __cpu_name[cpu] = "Nevada";
1108 set_isa(c, MIPS_CPU_ISA_IV);
1109 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1110 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1111 c->tlbsize = 48;
1112 break;
1113 case PRID_IMP_R6000:
1114 c->cputype = CPU_R6000;
1115 __cpu_name[cpu] = "R6000";
1116 set_isa(c, MIPS_CPU_ISA_II);
1117 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1118 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
1119 MIPS_CPU_LLSC;
1120 c->tlbsize = 32;
1121 break;
1122 case PRID_IMP_R6000A:
1123 c->cputype = CPU_R6000A;
1124 __cpu_name[cpu] = "R6000A";
1125 set_isa(c, MIPS_CPU_ISA_II);
1126 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1127 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
1128 MIPS_CPU_LLSC;
1129 c->tlbsize = 32;
1130 break;
1131 case PRID_IMP_RM7000:
1132 c->cputype = CPU_RM7000;
1133 __cpu_name[cpu] = "RM7000";
1134 set_isa(c, MIPS_CPU_ISA_IV);
1135 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1136 MIPS_CPU_LLSC;
1137 /*
1138 * Undocumented RM7000: Bit 29 in the info register of
1139 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1140 * entries.
1141 *
1142 * 29 1 => 64 entry JTLB
1143 * 0 => 48 entry JTLB
1144 */
1145 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1146 break;
1147 case PRID_IMP_R8000:
1148 c->cputype = CPU_R8000;
1149 __cpu_name[cpu] = "RM8000";
1150 set_isa(c, MIPS_CPU_ISA_IV);
1151 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
1152 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1153 MIPS_CPU_LLSC;
1154 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
1155 break;
1156 case PRID_IMP_R10000:
1157 c->cputype = CPU_R10000;
1158 __cpu_name[cpu] = "R10000";
1159 set_isa(c, MIPS_CPU_ISA_IV);
1160 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1161 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1162 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1163 MIPS_CPU_LLSC;
1164 c->tlbsize = 64;
1165 break;
1166 case PRID_IMP_R12000:
1167 c->cputype = CPU_R12000;
1168 __cpu_name[cpu] = "R12000";
1169 set_isa(c, MIPS_CPU_ISA_IV);
1170 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1171 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1172 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1173 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1174 c->tlbsize = 64;
1175 break;
1176 case PRID_IMP_R14000:
1177 if (((c->processor_id >> 4) & 0x0f) > 2) {
1178 c->cputype = CPU_R16000;
1179 __cpu_name[cpu] = "R16000";
1180 } else {
1181 c->cputype = CPU_R14000;
1182 __cpu_name[cpu] = "R14000";
1183 }
1184 set_isa(c, MIPS_CPU_ISA_IV);
1185 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1186 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1187 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1188 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1189 c->tlbsize = 64;
1190 break;
1191 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1192 switch (c->processor_id & PRID_REV_MASK) {
1193 case PRID_REV_LOONGSON2E:
1194 c->cputype = CPU_LOONGSON2;
1195 __cpu_name[cpu] = "ICT Loongson-2";
1196 set_elf_platform(cpu, "loongson2e");
1197 set_isa(c, MIPS_CPU_ISA_III);
1198 c->fpu_msk31 |= FPU_CSR_CONDX;
1199 break;
1200 case PRID_REV_LOONGSON2F:
1201 c->cputype = CPU_LOONGSON2;
1202 __cpu_name[cpu] = "ICT Loongson-2";
1203 set_elf_platform(cpu, "loongson2f");
1204 set_isa(c, MIPS_CPU_ISA_III);
1205 c->fpu_msk31 |= FPU_CSR_CONDX;
1206 break;
1207 case PRID_REV_LOONGSON3A_R1:
1208 c->cputype = CPU_LOONGSON3;
1209 __cpu_name[cpu] = "ICT Loongson-3";
1210 set_elf_platform(cpu, "loongson3a");
1211 set_isa(c, MIPS_CPU_ISA_M64R1);
1212 break;
1213 case PRID_REV_LOONGSON3B_R1:
1214 case PRID_REV_LOONGSON3B_R2:
1215 c->cputype = CPU_LOONGSON3;
1216 __cpu_name[cpu] = "ICT Loongson-3";
1217 set_elf_platform(cpu, "loongson3b");
1218 set_isa(c, MIPS_CPU_ISA_M64R1);
1219 break;
1220 }
1221
1222 c->options = R4K_OPTS |
1223 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1224 MIPS_CPU_32FPR;
1225 c->tlbsize = 64;
1226 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1227 break;
1228 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
1229 decode_configs(c);
1230
1231 c->cputype = CPU_LOONGSON1;
1232
1233 switch (c->processor_id & PRID_REV_MASK) {
1234 case PRID_REV_LOONGSON1B:
1235 __cpu_name[cpu] = "Loongson 1B";
1236 break;
1237 }
1238
1239 break;
1240 }
1241 }
1242
1243 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1244 {
1245 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1246 switch (c->processor_id & PRID_IMP_MASK) {
1247 case PRID_IMP_QEMU_GENERIC:
1248 c->writecombine = _CACHE_UNCACHED;
1249 c->cputype = CPU_QEMU_GENERIC;
1250 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1251 break;
1252 case PRID_IMP_4KC:
1253 c->cputype = CPU_4KC;
1254 c->writecombine = _CACHE_UNCACHED;
1255 __cpu_name[cpu] = "MIPS 4Kc";
1256 break;
1257 case PRID_IMP_4KEC:
1258 case PRID_IMP_4KECR2:
1259 c->cputype = CPU_4KEC;
1260 c->writecombine = _CACHE_UNCACHED;
1261 __cpu_name[cpu] = "MIPS 4KEc";
1262 break;
1263 case PRID_IMP_4KSC:
1264 case PRID_IMP_4KSD:
1265 c->cputype = CPU_4KSC;
1266 c->writecombine = _CACHE_UNCACHED;
1267 __cpu_name[cpu] = "MIPS 4KSc";
1268 break;
1269 case PRID_IMP_5KC:
1270 c->cputype = CPU_5KC;
1271 c->writecombine = _CACHE_UNCACHED;
1272 __cpu_name[cpu] = "MIPS 5Kc";
1273 break;
1274 case PRID_IMP_5KE:
1275 c->cputype = CPU_5KE;
1276 c->writecombine = _CACHE_UNCACHED;
1277 __cpu_name[cpu] = "MIPS 5KE";
1278 break;
1279 case PRID_IMP_20KC:
1280 c->cputype = CPU_20KC;
1281 c->writecombine = _CACHE_UNCACHED;
1282 __cpu_name[cpu] = "MIPS 20Kc";
1283 break;
1284 case PRID_IMP_24K:
1285 c->cputype = CPU_24K;
1286 c->writecombine = _CACHE_UNCACHED;
1287 __cpu_name[cpu] = "MIPS 24Kc";
1288 break;
1289 case PRID_IMP_24KE:
1290 c->cputype = CPU_24K;
1291 c->writecombine = _CACHE_UNCACHED;
1292 __cpu_name[cpu] = "MIPS 24KEc";
1293 break;
1294 case PRID_IMP_25KF:
1295 c->cputype = CPU_25KF;
1296 c->writecombine = _CACHE_UNCACHED;
1297 __cpu_name[cpu] = "MIPS 25Kc";
1298 break;
1299 case PRID_IMP_34K:
1300 c->cputype = CPU_34K;
1301 c->writecombine = _CACHE_UNCACHED;
1302 __cpu_name[cpu] = "MIPS 34Kc";
1303 break;
1304 case PRID_IMP_74K:
1305 c->cputype = CPU_74K;
1306 c->writecombine = _CACHE_UNCACHED;
1307 __cpu_name[cpu] = "MIPS 74Kc";
1308 break;
1309 case PRID_IMP_M14KC:
1310 c->cputype = CPU_M14KC;
1311 c->writecombine = _CACHE_UNCACHED;
1312 __cpu_name[cpu] = "MIPS M14Kc";
1313 break;
1314 case PRID_IMP_M14KEC:
1315 c->cputype = CPU_M14KEC;
1316 c->writecombine = _CACHE_UNCACHED;
1317 __cpu_name[cpu] = "MIPS M14KEc";
1318 break;
1319 case PRID_IMP_1004K:
1320 c->cputype = CPU_1004K;
1321 c->writecombine = _CACHE_UNCACHED;
1322 __cpu_name[cpu] = "MIPS 1004Kc";
1323 break;
1324 case PRID_IMP_1074K:
1325 c->cputype = CPU_1074K;
1326 c->writecombine = _CACHE_UNCACHED;
1327 __cpu_name[cpu] = "MIPS 1074Kc";
1328 break;
1329 case PRID_IMP_INTERAPTIV_UP:
1330 c->cputype = CPU_INTERAPTIV;
1331 __cpu_name[cpu] = "MIPS interAptiv";
1332 break;
1333 case PRID_IMP_INTERAPTIV_MP:
1334 c->cputype = CPU_INTERAPTIV;
1335 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1336 break;
1337 case PRID_IMP_PROAPTIV_UP:
1338 c->cputype = CPU_PROAPTIV;
1339 __cpu_name[cpu] = "MIPS proAptiv";
1340 break;
1341 case PRID_IMP_PROAPTIV_MP:
1342 c->cputype = CPU_PROAPTIV;
1343 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1344 break;
1345 case PRID_IMP_P5600:
1346 c->cputype = CPU_P5600;
1347 __cpu_name[cpu] = "MIPS P5600";
1348 break;
1349 case PRID_IMP_P6600:
1350 c->cputype = CPU_P6600;
1351 __cpu_name[cpu] = "MIPS P6600";
1352 break;
1353 case PRID_IMP_I6400:
1354 c->cputype = CPU_I6400;
1355 __cpu_name[cpu] = "MIPS I6400";
1356 break;
1357 case PRID_IMP_M5150:
1358 c->cputype = CPU_M5150;
1359 __cpu_name[cpu] = "MIPS M5150";
1360 break;
1361 case PRID_IMP_M6250:
1362 c->cputype = CPU_M6250;
1363 __cpu_name[cpu] = "MIPS M6250";
1364 break;
1365 }
1366
1367 decode_configs(c);
1368
1369 spram_config();
1370 }
1371
1372 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1373 {
1374 decode_configs(c);
1375 switch (c->processor_id & PRID_IMP_MASK) {
1376 case PRID_IMP_AU1_REV1:
1377 case PRID_IMP_AU1_REV2:
1378 c->cputype = CPU_ALCHEMY;
1379 switch ((c->processor_id >> 24) & 0xff) {
1380 case 0:
1381 __cpu_name[cpu] = "Au1000";
1382 break;
1383 case 1:
1384 __cpu_name[cpu] = "Au1500";
1385 break;
1386 case 2:
1387 __cpu_name[cpu] = "Au1100";
1388 break;
1389 case 3:
1390 __cpu_name[cpu] = "Au1550";
1391 break;
1392 case 4:
1393 __cpu_name[cpu] = "Au1200";
1394 if ((c->processor_id & PRID_REV_MASK) == 2)
1395 __cpu_name[cpu] = "Au1250";
1396 break;
1397 case 5:
1398 __cpu_name[cpu] = "Au1210";
1399 break;
1400 default:
1401 __cpu_name[cpu] = "Au1xxx";
1402 break;
1403 }
1404 break;
1405 }
1406 }
1407
1408 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1409 {
1410 decode_configs(c);
1411
1412 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1413 switch (c->processor_id & PRID_IMP_MASK) {
1414 case PRID_IMP_SB1:
1415 c->cputype = CPU_SB1;
1416 __cpu_name[cpu] = "SiByte SB1";
1417 /* FPU in pass1 is known to have issues. */
1418 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1419 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1420 break;
1421 case PRID_IMP_SB1A:
1422 c->cputype = CPU_SB1A;
1423 __cpu_name[cpu] = "SiByte SB1A";
1424 break;
1425 }
1426 }
1427
1428 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1429 {
1430 decode_configs(c);
1431 switch (c->processor_id & PRID_IMP_MASK) {
1432 case PRID_IMP_SR71000:
1433 c->cputype = CPU_SR71000;
1434 __cpu_name[cpu] = "Sandcraft SR71000";
1435 c->scache.ways = 8;
1436 c->tlbsize = 64;
1437 break;
1438 }
1439 }
1440
1441 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1442 {
1443 decode_configs(c);
1444 switch (c->processor_id & PRID_IMP_MASK) {
1445 case PRID_IMP_PR4450:
1446 c->cputype = CPU_PR4450;
1447 __cpu_name[cpu] = "Philips PR4450";
1448 set_isa(c, MIPS_CPU_ISA_M32R1);
1449 break;
1450 }
1451 }
1452
1453 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1454 {
1455 decode_configs(c);
1456 switch (c->processor_id & PRID_IMP_MASK) {
1457 case PRID_IMP_BMIPS32_REV4:
1458 case PRID_IMP_BMIPS32_REV8:
1459 c->cputype = CPU_BMIPS32;
1460 __cpu_name[cpu] = "Broadcom BMIPS32";
1461 set_elf_platform(cpu, "bmips32");
1462 break;
1463 case PRID_IMP_BMIPS3300:
1464 case PRID_IMP_BMIPS3300_ALT:
1465 case PRID_IMP_BMIPS3300_BUG:
1466 c->cputype = CPU_BMIPS3300;
1467 __cpu_name[cpu] = "Broadcom BMIPS3300";
1468 set_elf_platform(cpu, "bmips3300");
1469 break;
1470 case PRID_IMP_BMIPS43XX: {
1471 int rev = c->processor_id & PRID_REV_MASK;
1472
1473 if (rev >= PRID_REV_BMIPS4380_LO &&
1474 rev <= PRID_REV_BMIPS4380_HI) {
1475 c->cputype = CPU_BMIPS4380;
1476 __cpu_name[cpu] = "Broadcom BMIPS4380";
1477 set_elf_platform(cpu, "bmips4380");
1478 } else {
1479 c->cputype = CPU_BMIPS4350;
1480 __cpu_name[cpu] = "Broadcom BMIPS4350";
1481 set_elf_platform(cpu, "bmips4350");
1482 }
1483 break;
1484 }
1485 case PRID_IMP_BMIPS5000:
1486 case PRID_IMP_BMIPS5200:
1487 c->cputype = CPU_BMIPS5000;
1488 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1489 __cpu_name[cpu] = "Broadcom BMIPS5200";
1490 else
1491 __cpu_name[cpu] = "Broadcom BMIPS5000";
1492 set_elf_platform(cpu, "bmips5000");
1493 c->options |= MIPS_CPU_ULRI;
1494 break;
1495 }
1496 }
1497
1498 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1499 {
1500 decode_configs(c);
1501 switch (c->processor_id & PRID_IMP_MASK) {
1502 case PRID_IMP_CAVIUM_CN38XX:
1503 case PRID_IMP_CAVIUM_CN31XX:
1504 case PRID_IMP_CAVIUM_CN30XX:
1505 c->cputype = CPU_CAVIUM_OCTEON;
1506 __cpu_name[cpu] = "Cavium Octeon";
1507 goto platform;
1508 case PRID_IMP_CAVIUM_CN58XX:
1509 case PRID_IMP_CAVIUM_CN56XX:
1510 case PRID_IMP_CAVIUM_CN50XX:
1511 case PRID_IMP_CAVIUM_CN52XX:
1512 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1513 __cpu_name[cpu] = "Cavium Octeon+";
1514 platform:
1515 set_elf_platform(cpu, "octeon");
1516 break;
1517 case PRID_IMP_CAVIUM_CN61XX:
1518 case PRID_IMP_CAVIUM_CN63XX:
1519 case PRID_IMP_CAVIUM_CN66XX:
1520 case PRID_IMP_CAVIUM_CN68XX:
1521 case PRID_IMP_CAVIUM_CNF71XX:
1522 c->cputype = CPU_CAVIUM_OCTEON2;
1523 __cpu_name[cpu] = "Cavium Octeon II";
1524 set_elf_platform(cpu, "octeon2");
1525 break;
1526 case PRID_IMP_CAVIUM_CN70XX:
1527 case PRID_IMP_CAVIUM_CN73XX:
1528 case PRID_IMP_CAVIUM_CNF75XX:
1529 case PRID_IMP_CAVIUM_CN78XX:
1530 c->cputype = CPU_CAVIUM_OCTEON3;
1531 __cpu_name[cpu] = "Cavium Octeon III";
1532 set_elf_platform(cpu, "octeon3");
1533 break;
1534 default:
1535 printk(KERN_INFO "Unknown Octeon chip!\n");
1536 c->cputype = CPU_UNKNOWN;
1537 break;
1538 }
1539 }
1540
1541 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
1542 {
1543 switch (c->processor_id & PRID_IMP_MASK) {
1544 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1545 switch (c->processor_id & PRID_REV_MASK) {
1546 case PRID_REV_LOONGSON3A_R2:
1547 c->cputype = CPU_LOONGSON3;
1548 __cpu_name[cpu] = "ICT Loongson-3";
1549 set_elf_platform(cpu, "loongson3a");
1550 set_isa(c, MIPS_CPU_ISA_M64R2);
1551 break;
1552 }
1553
1554 decode_configs(c);
1555 c->options |= MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
1556 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1557 break;
1558 default:
1559 panic("Unknown Loongson Processor ID!");
1560 break;
1561 }
1562 }
1563
1564 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1565 {
1566 decode_configs(c);
1567 /* JZRISC does not implement the CP0 counter. */
1568 c->options &= ~MIPS_CPU_COUNTER;
1569 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1570 switch (c->processor_id & PRID_IMP_MASK) {
1571 case PRID_IMP_JZRISC:
1572 c->cputype = CPU_JZRISC;
1573 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1574 __cpu_name[cpu] = "Ingenic JZRISC";
1575 break;
1576 default:
1577 panic("Unknown Ingenic Processor ID!");
1578 break;
1579 }
1580 }
1581
1582 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1583 {
1584 decode_configs(c);
1585
1586 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1587 c->cputype = CPU_ALCHEMY;
1588 __cpu_name[cpu] = "Au1300";
1589 /* following stuff is not for Alchemy */
1590 return;
1591 }
1592
1593 c->options = (MIPS_CPU_TLB |
1594 MIPS_CPU_4KEX |
1595 MIPS_CPU_COUNTER |
1596 MIPS_CPU_DIVEC |
1597 MIPS_CPU_WATCH |
1598 MIPS_CPU_EJTAG |
1599 MIPS_CPU_LLSC);
1600
1601 switch (c->processor_id & PRID_IMP_MASK) {
1602 case PRID_IMP_NETLOGIC_XLP2XX:
1603 case PRID_IMP_NETLOGIC_XLP9XX:
1604 case PRID_IMP_NETLOGIC_XLP5XX:
1605 c->cputype = CPU_XLP;
1606 __cpu_name[cpu] = "Broadcom XLPII";
1607 break;
1608
1609 case PRID_IMP_NETLOGIC_XLP8XX:
1610 case PRID_IMP_NETLOGIC_XLP3XX:
1611 c->cputype = CPU_XLP;
1612 __cpu_name[cpu] = "Netlogic XLP";
1613 break;
1614
1615 case PRID_IMP_NETLOGIC_XLR732:
1616 case PRID_IMP_NETLOGIC_XLR716:
1617 case PRID_IMP_NETLOGIC_XLR532:
1618 case PRID_IMP_NETLOGIC_XLR308:
1619 case PRID_IMP_NETLOGIC_XLR532C:
1620 case PRID_IMP_NETLOGIC_XLR516C:
1621 case PRID_IMP_NETLOGIC_XLR508C:
1622 case PRID_IMP_NETLOGIC_XLR308C:
1623 c->cputype = CPU_XLR;
1624 __cpu_name[cpu] = "Netlogic XLR";
1625 break;
1626
1627 case PRID_IMP_NETLOGIC_XLS608:
1628 case PRID_IMP_NETLOGIC_XLS408:
1629 case PRID_IMP_NETLOGIC_XLS404:
1630 case PRID_IMP_NETLOGIC_XLS208:
1631 case PRID_IMP_NETLOGIC_XLS204:
1632 case PRID_IMP_NETLOGIC_XLS108:
1633 case PRID_IMP_NETLOGIC_XLS104:
1634 case PRID_IMP_NETLOGIC_XLS616B:
1635 case PRID_IMP_NETLOGIC_XLS608B:
1636 case PRID_IMP_NETLOGIC_XLS416B:
1637 case PRID_IMP_NETLOGIC_XLS412B:
1638 case PRID_IMP_NETLOGIC_XLS408B:
1639 case PRID_IMP_NETLOGIC_XLS404B:
1640 c->cputype = CPU_XLR;
1641 __cpu_name[cpu] = "Netlogic XLS";
1642 break;
1643
1644 default:
1645 pr_info("Unknown Netlogic chip id [%02x]!\n",
1646 c->processor_id);
1647 c->cputype = CPU_XLR;
1648 break;
1649 }
1650
1651 if (c->cputype == CPU_XLP) {
1652 set_isa(c, MIPS_CPU_ISA_M64R2);
1653 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1654 /* This will be updated again after all threads are woken up */
1655 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1656 } else {
1657 set_isa(c, MIPS_CPU_ISA_M64R1);
1658 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1659 }
1660 c->kscratch_mask = 0xf;
1661 }
1662
1663 #ifdef CONFIG_64BIT
1664 /* For use by uaccess.h */
1665 u64 __ua_limit;
1666 EXPORT_SYMBOL(__ua_limit);
1667 #endif
1668
1669 const char *__cpu_name[NR_CPUS];
1670 const char *__elf_platform;
1671
1672 void cpu_probe(void)
1673 {
1674 struct cpuinfo_mips *c = &current_cpu_data;
1675 unsigned int cpu = smp_processor_id();
1676
1677 c->processor_id = PRID_IMP_UNKNOWN;
1678 c->fpu_id = FPIR_IMP_NONE;
1679 c->cputype = CPU_UNKNOWN;
1680 c->writecombine = _CACHE_UNCACHED;
1681
1682 c->fpu_csr31 = FPU_CSR_RN;
1683 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1684
1685 c->processor_id = read_c0_prid();
1686 switch (c->processor_id & PRID_COMP_MASK) {
1687 case PRID_COMP_LEGACY:
1688 cpu_probe_legacy(c, cpu);
1689 break;
1690 case PRID_COMP_MIPS:
1691 cpu_probe_mips(c, cpu);
1692 break;
1693 case PRID_COMP_ALCHEMY:
1694 cpu_probe_alchemy(c, cpu);
1695 break;
1696 case PRID_COMP_SIBYTE:
1697 cpu_probe_sibyte(c, cpu);
1698 break;
1699 case PRID_COMP_BROADCOM:
1700 cpu_probe_broadcom(c, cpu);
1701 break;
1702 case PRID_COMP_SANDCRAFT:
1703 cpu_probe_sandcraft(c, cpu);
1704 break;
1705 case PRID_COMP_NXP:
1706 cpu_probe_nxp(c, cpu);
1707 break;
1708 case PRID_COMP_CAVIUM:
1709 cpu_probe_cavium(c, cpu);
1710 break;
1711 case PRID_COMP_LOONGSON:
1712 cpu_probe_loongson(c, cpu);
1713 break;
1714 case PRID_COMP_INGENIC_D0:
1715 case PRID_COMP_INGENIC_D1:
1716 case PRID_COMP_INGENIC_E1:
1717 cpu_probe_ingenic(c, cpu);
1718 break;
1719 case PRID_COMP_NETLOGIC:
1720 cpu_probe_netlogic(c, cpu);
1721 break;
1722 }
1723
1724 BUG_ON(!__cpu_name[cpu]);
1725 BUG_ON(c->cputype == CPU_UNKNOWN);
1726
1727 /*
1728 * Platform code can force the cpu type to optimize code
1729 * generation. In that case be sure the cpu type is correctly
1730 * manually setup otherwise it could trigger some nasty bugs.
1731 */
1732 BUG_ON(current_cpu_type() != c->cputype);
1733
1734 if (mips_fpu_disabled)
1735 c->options &= ~MIPS_CPU_FPU;
1736
1737 if (mips_dsp_disabled)
1738 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1739
1740 if (mips_htw_disabled) {
1741 c->options &= ~MIPS_CPU_HTW;
1742 write_c0_pwctl(read_c0_pwctl() &
1743 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1744 }
1745
1746 if (c->options & MIPS_CPU_FPU)
1747 cpu_set_fpu_opts(c);
1748 else
1749 cpu_set_nofpu_opts(c);
1750
1751 if (cpu_has_bp_ghist)
1752 write_c0_r10k_diag(read_c0_r10k_diag() |
1753 R10K_DIAG_E_GHIST);
1754
1755 if (cpu_has_mips_r2_r6) {
1756 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1757 /* R2 has Performance Counter Interrupt indicator */
1758 c->options |= MIPS_CPU_PCI;
1759 }
1760 else
1761 c->srsets = 1;
1762
1763 if (cpu_has_mips_r6)
1764 elf_hwcap |= HWCAP_MIPS_R6;
1765
1766 if (cpu_has_msa) {
1767 c->msa_id = cpu_get_msa_id();
1768 WARN(c->msa_id & MSA_IR_WRPF,
1769 "Vector register partitioning unimplemented!");
1770 elf_hwcap |= HWCAP_MIPS_MSA;
1771 }
1772
1773 cpu_probe_vmbits(c);
1774
1775 #ifdef CONFIG_64BIT
1776 if (cpu == 0)
1777 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1778 #endif
1779 }
1780
1781 void cpu_report(void)
1782 {
1783 struct cpuinfo_mips *c = &current_cpu_data;
1784
1785 pr_info("CPU%d revision is: %08x (%s)\n",
1786 smp_processor_id(), c->processor_id, cpu_name_string());
1787 if (c->options & MIPS_CPU_FPU)
1788 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1789 if (cpu_has_msa)
1790 pr_info("MSA revision is: %08x\n", c->msa_id);
1791 }
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