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1 /*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
20
21 #include <asm/bugs.h>
22 #include <asm/cpu.h>
23 #include <asm/cpu-features.h>
24 #include <asm/cpu-type.h>
25 #include <asm/fpu.h>
26 #include <asm/mipsregs.h>
27 #include <asm/mipsmtregs.h>
28 #include <asm/msa.h>
29 #include <asm/watch.h>
30 #include <asm/elf.h>
31 #include <asm/pgtable-bits.h>
32 #include <asm/spram.h>
33 #include <linux/uaccess.h>
34
35 /* Hardware capabilities */
36 unsigned int elf_hwcap __read_mostly;
37 EXPORT_SYMBOL_GPL(elf_hwcap);
38
39 /*
40 * Get the FPU Implementation/Revision.
41 */
42 static inline unsigned long cpu_get_fpu_id(void)
43 {
44 unsigned long tmp, fpu_id;
45
46 tmp = read_c0_status();
47 __enable_fpu(FPU_AS_IS);
48 fpu_id = read_32bit_cp1_register(CP1_REVISION);
49 write_c0_status(tmp);
50 return fpu_id;
51 }
52
53 /*
54 * Check if the CPU has an external FPU.
55 */
56 static inline int __cpu_has_fpu(void)
57 {
58 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
59 }
60
61 static inline unsigned long cpu_get_msa_id(void)
62 {
63 unsigned long status, msa_id;
64
65 status = read_c0_status();
66 __enable_fpu(FPU_64BIT);
67 enable_msa();
68 msa_id = read_msa_ir();
69 disable_msa();
70 write_c0_status(status);
71 return msa_id;
72 }
73
74 /*
75 * Determine the FCSR mask for FPU hardware.
76 */
77 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
78 {
79 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
80
81 fcsr = c->fpu_csr31;
82 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
83
84 sr = read_c0_status();
85 __enable_fpu(FPU_AS_IS);
86
87 fcsr0 = fcsr & mask;
88 write_32bit_cp1_register(CP1_STATUS, fcsr0);
89 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
90
91 fcsr1 = fcsr | ~mask;
92 write_32bit_cp1_register(CP1_STATUS, fcsr1);
93 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
94
95 write_32bit_cp1_register(CP1_STATUS, fcsr);
96
97 write_c0_status(sr);
98
99 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
100 }
101
102 /*
103 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
104 * supported by FPU hardware.
105 */
106 static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
107 {
108 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
109 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
110 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
111 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
112
113 sr = read_c0_status();
114 __enable_fpu(FPU_AS_IS);
115
116 fir = read_32bit_cp1_register(CP1_REVISION);
117 if (fir & MIPS_FPIR_HAS2008) {
118 fcsr = read_32bit_cp1_register(CP1_STATUS);
119
120 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
121 write_32bit_cp1_register(CP1_STATUS, fcsr0);
122 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
123
124 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
125 write_32bit_cp1_register(CP1_STATUS, fcsr1);
126 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
127
128 write_32bit_cp1_register(CP1_STATUS, fcsr);
129
130 if (!(fcsr0 & FPU_CSR_NAN2008))
131 c->options |= MIPS_CPU_NAN_LEGACY;
132 if (fcsr1 & FPU_CSR_NAN2008)
133 c->options |= MIPS_CPU_NAN_2008;
134
135 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
136 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
137 else
138 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
139
140 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
141 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
142 else
143 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
144 } else {
145 c->options |= MIPS_CPU_NAN_LEGACY;
146 }
147
148 write_c0_status(sr);
149 } else {
150 c->options |= MIPS_CPU_NAN_LEGACY;
151 }
152 }
153
154 /*
155 * IEEE 754 conformance mode to use. Affects the NaN encoding and the
156 * ABS.fmt/NEG.fmt execution mode.
157 */
158 static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
159
160 /*
161 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
162 * to support by the FPU emulator according to the IEEE 754 conformance
163 * mode selected. Note that "relaxed" straps the emulator so that it
164 * allows 2008-NaN binaries even for legacy processors.
165 */
166 static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
167 {
168 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
169 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
170 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
171
172 switch (ieee754) {
173 case STRICT:
174 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
175 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
176 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
177 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
178 } else {
179 c->options |= MIPS_CPU_NAN_LEGACY;
180 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
181 }
182 break;
183 case LEGACY:
184 c->options |= MIPS_CPU_NAN_LEGACY;
185 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
186 break;
187 case STD2008:
188 c->options |= MIPS_CPU_NAN_2008;
189 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
190 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
191 break;
192 case RELAXED:
193 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
194 break;
195 }
196 }
197
198 /*
199 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
200 * according to the "ieee754=" parameter.
201 */
202 static void cpu_set_nan_2008(struct cpuinfo_mips *c)
203 {
204 switch (ieee754) {
205 case STRICT:
206 mips_use_nan_legacy = !!cpu_has_nan_legacy;
207 mips_use_nan_2008 = !!cpu_has_nan_2008;
208 break;
209 case LEGACY:
210 mips_use_nan_legacy = !!cpu_has_nan_legacy;
211 mips_use_nan_2008 = !cpu_has_nan_legacy;
212 break;
213 case STD2008:
214 mips_use_nan_legacy = !cpu_has_nan_2008;
215 mips_use_nan_2008 = !!cpu_has_nan_2008;
216 break;
217 case RELAXED:
218 mips_use_nan_legacy = true;
219 mips_use_nan_2008 = true;
220 break;
221 }
222 }
223
224 /*
225 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
226 * settings:
227 *
228 * strict: accept binaries that request a NaN encoding supported by the FPU
229 * legacy: only accept legacy-NaN binaries
230 * 2008: only accept 2008-NaN binaries
231 * relaxed: accept any binaries regardless of whether supported by the FPU
232 */
233 static int __init ieee754_setup(char *s)
234 {
235 if (!s)
236 return -1;
237 else if (!strcmp(s, "strict"))
238 ieee754 = STRICT;
239 else if (!strcmp(s, "legacy"))
240 ieee754 = LEGACY;
241 else if (!strcmp(s, "2008"))
242 ieee754 = STD2008;
243 else if (!strcmp(s, "relaxed"))
244 ieee754 = RELAXED;
245 else
246 return -1;
247
248 if (!(boot_cpu_data.options & MIPS_CPU_FPU))
249 cpu_set_nofpu_2008(&boot_cpu_data);
250 cpu_set_nan_2008(&boot_cpu_data);
251
252 return 0;
253 }
254
255 early_param("ieee754", ieee754_setup);
256
257 /*
258 * Set the FIR feature flags for the FPU emulator.
259 */
260 static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
261 {
262 u32 value;
263
264 value = 0;
265 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
266 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
267 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
268 value |= MIPS_FPIR_D | MIPS_FPIR_S;
269 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
270 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
271 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
272 if (c->options & MIPS_CPU_NAN_2008)
273 value |= MIPS_FPIR_HAS2008;
274 c->fpu_id = value;
275 }
276
277 /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
278 static unsigned int mips_nofpu_msk31;
279
280 /*
281 * Set options for FPU hardware.
282 */
283 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
284 {
285 c->fpu_id = cpu_get_fpu_id();
286 mips_nofpu_msk31 = c->fpu_msk31;
287
288 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
289 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
290 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
291 if (c->fpu_id & MIPS_FPIR_3D)
292 c->ases |= MIPS_ASE_MIPS3D;
293 if (c->fpu_id & MIPS_FPIR_UFRP)
294 c->options |= MIPS_CPU_UFR;
295 if (c->fpu_id & MIPS_FPIR_FREP)
296 c->options |= MIPS_CPU_FRE;
297 }
298
299 cpu_set_fpu_fcsr_mask(c);
300 cpu_set_fpu_2008(c);
301 cpu_set_nan_2008(c);
302 }
303
304 /*
305 * Set options for the FPU emulator.
306 */
307 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
308 {
309 c->options &= ~MIPS_CPU_FPU;
310 c->fpu_msk31 = mips_nofpu_msk31;
311
312 cpu_set_nofpu_2008(c);
313 cpu_set_nan_2008(c);
314 cpu_set_nofpu_id(c);
315 }
316
317 static int mips_fpu_disabled;
318
319 static int __init fpu_disable(char *s)
320 {
321 cpu_set_nofpu_opts(&boot_cpu_data);
322 mips_fpu_disabled = 1;
323
324 return 1;
325 }
326
327 __setup("nofpu", fpu_disable);
328
329 static int mips_dsp_disabled;
330
331 static int __init dsp_disable(char *s)
332 {
333 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
334 mips_dsp_disabled = 1;
335
336 return 1;
337 }
338
339 __setup("nodsp", dsp_disable);
340
341 static int mips_htw_disabled;
342
343 static int __init htw_disable(char *s)
344 {
345 mips_htw_disabled = 1;
346 cpu_data[0].options &= ~MIPS_CPU_HTW;
347 write_c0_pwctl(read_c0_pwctl() &
348 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
349
350 return 1;
351 }
352
353 __setup("nohtw", htw_disable);
354
355 static int mips_ftlb_disabled;
356 static int mips_has_ftlb_configured;
357
358 enum ftlb_flags {
359 FTLB_EN = 1 << 0,
360 FTLB_SET_PROB = 1 << 1,
361 };
362
363 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags);
364
365 static int __init ftlb_disable(char *s)
366 {
367 unsigned int config4, mmuextdef;
368
369 /*
370 * If the core hasn't done any FTLB configuration, there is nothing
371 * for us to do here.
372 */
373 if (!mips_has_ftlb_configured)
374 return 1;
375
376 /* Disable it in the boot cpu */
377 if (set_ftlb_enable(&cpu_data[0], 0)) {
378 pr_warn("Can't turn FTLB off\n");
379 return 1;
380 }
381
382 config4 = read_c0_config4();
383
384 /* Check that FTLB has been disabled */
385 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
386 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
387 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
388 /* This should never happen */
389 pr_warn("FTLB could not be disabled!\n");
390 return 1;
391 }
392
393 mips_ftlb_disabled = 1;
394 mips_has_ftlb_configured = 0;
395
396 /*
397 * noftlb is mainly used for debug purposes so print
398 * an informative message instead of using pr_debug()
399 */
400 pr_info("FTLB has been disabled\n");
401
402 /*
403 * Some of these bits are duplicated in the decode_config4.
404 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
405 * once FTLB has been disabled so undo what decode_config4 did.
406 */
407 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
408 cpu_data[0].tlbsizeftlbsets;
409 cpu_data[0].tlbsizeftlbsets = 0;
410 cpu_data[0].tlbsizeftlbways = 0;
411
412 return 1;
413 }
414
415 __setup("noftlb", ftlb_disable);
416
417
418 static inline void check_errata(void)
419 {
420 struct cpuinfo_mips *c = &current_cpu_data;
421
422 switch (current_cpu_type()) {
423 case CPU_34K:
424 /*
425 * Erratum "RPS May Cause Incorrect Instruction Execution"
426 * This code only handles VPE0, any SMP/RTOS code
427 * making use of VPE1 will be responsable for that VPE.
428 */
429 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
430 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
431 break;
432 default:
433 break;
434 }
435 }
436
437 void __init check_bugs32(void)
438 {
439 check_errata();
440 }
441
442 /*
443 * Probe whether cpu has config register by trying to play with
444 * alternate cache bit and see whether it matters.
445 * It's used by cpu_probe to distinguish between R3000A and R3081.
446 */
447 static inline int cpu_has_confreg(void)
448 {
449 #ifdef CONFIG_CPU_R3000
450 extern unsigned long r3k_cache_size(unsigned long);
451 unsigned long size1, size2;
452 unsigned long cfg = read_c0_conf();
453
454 size1 = r3k_cache_size(ST0_ISC);
455 write_c0_conf(cfg ^ R30XX_CONF_AC);
456 size2 = r3k_cache_size(ST0_ISC);
457 write_c0_conf(cfg);
458 return size1 != size2;
459 #else
460 return 0;
461 #endif
462 }
463
464 static inline void set_elf_platform(int cpu, const char *plat)
465 {
466 if (cpu == 0)
467 __elf_platform = plat;
468 }
469
470 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
471 {
472 #ifdef __NEED_VMBITS_PROBE
473 write_c0_entryhi(0x3fffffffffffe000ULL);
474 back_to_back_c0_hazard();
475 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
476 #endif
477 }
478
479 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
480 {
481 switch (isa) {
482 case MIPS_CPU_ISA_M64R2:
483 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
484 case MIPS_CPU_ISA_M64R1:
485 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
486 case MIPS_CPU_ISA_V:
487 c->isa_level |= MIPS_CPU_ISA_V;
488 case MIPS_CPU_ISA_IV:
489 c->isa_level |= MIPS_CPU_ISA_IV;
490 case MIPS_CPU_ISA_III:
491 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
492 break;
493
494 /* R6 incompatible with everything else */
495 case MIPS_CPU_ISA_M64R6:
496 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
497 case MIPS_CPU_ISA_M32R6:
498 c->isa_level |= MIPS_CPU_ISA_M32R6;
499 /* Break here so we don't add incompatible ISAs */
500 break;
501 case MIPS_CPU_ISA_M32R2:
502 c->isa_level |= MIPS_CPU_ISA_M32R2;
503 case MIPS_CPU_ISA_M32R1:
504 c->isa_level |= MIPS_CPU_ISA_M32R1;
505 case MIPS_CPU_ISA_II:
506 c->isa_level |= MIPS_CPU_ISA_II;
507 break;
508 }
509 }
510
511 static char unknown_isa[] = KERN_ERR \
512 "Unsupported ISA type, c0.config0: %d.";
513
514 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
515 {
516
517 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
518
519 /*
520 * 0 = All TLBWR instructions go to FTLB
521 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
522 * FTLB and 1 goes to the VTLB.
523 * 2 = 7:1: As above with 7:1 ratio.
524 * 3 = 3:1: As above with 3:1 ratio.
525 *
526 * Use the linear midpoint as the probability threshold.
527 */
528 if (probability >= 12)
529 return 1;
530 else if (probability >= 6)
531 return 2;
532 else
533 /*
534 * So FTLB is less than 4 times bigger than VTLB.
535 * A 3:1 ratio can still be useful though.
536 */
537 return 3;
538 }
539
540 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
541 {
542 unsigned int config;
543
544 /* It's implementation dependent how the FTLB can be enabled */
545 switch (c->cputype) {
546 case CPU_PROAPTIV:
547 case CPU_P5600:
548 case CPU_P6600:
549 /* proAptiv & related cores use Config6 to enable the FTLB */
550 config = read_c0_config6();
551
552 if (flags & FTLB_EN)
553 config |= MIPS_CONF6_FTLBEN;
554 else
555 config &= ~MIPS_CONF6_FTLBEN;
556
557 if (flags & FTLB_SET_PROB) {
558 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
559 config |= calculate_ftlb_probability(c)
560 << MIPS_CONF6_FTLBP_SHIFT;
561 }
562
563 write_c0_config6(config);
564 back_to_back_c0_hazard();
565 break;
566 case CPU_I6400:
567 case CPU_I6500:
568 /* There's no way to disable the FTLB */
569 if (!(flags & FTLB_EN))
570 return 1;
571 return 0;
572 case CPU_LOONGSON3:
573 /* Flush ITLB, DTLB, VTLB and FTLB */
574 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
575 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
576 /* Loongson-3 cores use Config6 to enable the FTLB */
577 config = read_c0_config6();
578 if (flags & FTLB_EN)
579 /* Enable FTLB */
580 write_c0_config6(config & ~MIPS_CONF6_FTLBDIS);
581 else
582 /* Disable FTLB */
583 write_c0_config6(config | MIPS_CONF6_FTLBDIS);
584 break;
585 default:
586 return 1;
587 }
588
589 return 0;
590 }
591
592 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
593 {
594 unsigned int config0;
595 int isa, mt;
596
597 config0 = read_c0_config();
598
599 /*
600 * Look for Standard TLB or Dual VTLB and FTLB
601 */
602 mt = config0 & MIPS_CONF_MT;
603 if (mt == MIPS_CONF_MT_TLB)
604 c->options |= MIPS_CPU_TLB;
605 else if (mt == MIPS_CONF_MT_FTLB)
606 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
607
608 isa = (config0 & MIPS_CONF_AT) >> 13;
609 switch (isa) {
610 case 0:
611 switch ((config0 & MIPS_CONF_AR) >> 10) {
612 case 0:
613 set_isa(c, MIPS_CPU_ISA_M32R1);
614 break;
615 case 1:
616 set_isa(c, MIPS_CPU_ISA_M32R2);
617 break;
618 case 2:
619 set_isa(c, MIPS_CPU_ISA_M32R6);
620 break;
621 default:
622 goto unknown;
623 }
624 break;
625 case 2:
626 switch ((config0 & MIPS_CONF_AR) >> 10) {
627 case 0:
628 set_isa(c, MIPS_CPU_ISA_M64R1);
629 break;
630 case 1:
631 set_isa(c, MIPS_CPU_ISA_M64R2);
632 break;
633 case 2:
634 set_isa(c, MIPS_CPU_ISA_M64R6);
635 break;
636 default:
637 goto unknown;
638 }
639 break;
640 default:
641 goto unknown;
642 }
643
644 return config0 & MIPS_CONF_M;
645
646 unknown:
647 panic(unknown_isa, config0);
648 }
649
650 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
651 {
652 unsigned int config1;
653
654 config1 = read_c0_config1();
655
656 if (config1 & MIPS_CONF1_MD)
657 c->ases |= MIPS_ASE_MDMX;
658 if (config1 & MIPS_CONF1_PC)
659 c->options |= MIPS_CPU_PERF;
660 if (config1 & MIPS_CONF1_WR)
661 c->options |= MIPS_CPU_WATCH;
662 if (config1 & MIPS_CONF1_CA)
663 c->ases |= MIPS_ASE_MIPS16;
664 if (config1 & MIPS_CONF1_EP)
665 c->options |= MIPS_CPU_EJTAG;
666 if (config1 & MIPS_CONF1_FP) {
667 c->options |= MIPS_CPU_FPU;
668 c->options |= MIPS_CPU_32FPR;
669 }
670 if (cpu_has_tlb) {
671 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
672 c->tlbsizevtlb = c->tlbsize;
673 c->tlbsizeftlbsets = 0;
674 }
675
676 return config1 & MIPS_CONF_M;
677 }
678
679 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
680 {
681 unsigned int config2;
682
683 config2 = read_c0_config2();
684
685 if (config2 & MIPS_CONF2_SL)
686 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
687
688 return config2 & MIPS_CONF_M;
689 }
690
691 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
692 {
693 unsigned int config3;
694
695 config3 = read_c0_config3();
696
697 if (config3 & MIPS_CONF3_SM) {
698 c->ases |= MIPS_ASE_SMARTMIPS;
699 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
700 }
701 if (config3 & MIPS_CONF3_RXI)
702 c->options |= MIPS_CPU_RIXI;
703 if (config3 & MIPS_CONF3_CTXTC)
704 c->options |= MIPS_CPU_CTXTC;
705 if (config3 & MIPS_CONF3_DSP)
706 c->ases |= MIPS_ASE_DSP;
707 if (config3 & MIPS_CONF3_DSP2P) {
708 c->ases |= MIPS_ASE_DSP2P;
709 if (cpu_has_mips_r6)
710 c->ases |= MIPS_ASE_DSP3;
711 }
712 if (config3 & MIPS_CONF3_VINT)
713 c->options |= MIPS_CPU_VINT;
714 if (config3 & MIPS_CONF3_VEIC)
715 c->options |= MIPS_CPU_VEIC;
716 if (config3 & MIPS_CONF3_LPA)
717 c->options |= MIPS_CPU_LPA;
718 if (config3 & MIPS_CONF3_MT)
719 c->ases |= MIPS_ASE_MIPSMT;
720 if (config3 & MIPS_CONF3_ULRI)
721 c->options |= MIPS_CPU_ULRI;
722 if (config3 & MIPS_CONF3_ISA)
723 c->options |= MIPS_CPU_MICROMIPS;
724 if (config3 & MIPS_CONF3_VZ)
725 c->ases |= MIPS_ASE_VZ;
726 if (config3 & MIPS_CONF3_SC)
727 c->options |= MIPS_CPU_SEGMENTS;
728 if (config3 & MIPS_CONF3_BI)
729 c->options |= MIPS_CPU_BADINSTR;
730 if (config3 & MIPS_CONF3_BP)
731 c->options |= MIPS_CPU_BADINSTRP;
732 if (config3 & MIPS_CONF3_MSA)
733 c->ases |= MIPS_ASE_MSA;
734 if (config3 & MIPS_CONF3_PW) {
735 c->htw_seq = 0;
736 c->options |= MIPS_CPU_HTW;
737 }
738 if (config3 & MIPS_CONF3_CDMM)
739 c->options |= MIPS_CPU_CDMM;
740 if (config3 & MIPS_CONF3_SP)
741 c->options |= MIPS_CPU_SP;
742
743 return config3 & MIPS_CONF_M;
744 }
745
746 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
747 {
748 unsigned int config4;
749 unsigned int newcf4;
750 unsigned int mmuextdef;
751 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
752 unsigned long asid_mask;
753
754 config4 = read_c0_config4();
755
756 if (cpu_has_tlb) {
757 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
758 c->options |= MIPS_CPU_TLBINV;
759
760 /*
761 * R6 has dropped the MMUExtDef field from config4.
762 * On R6 the fields always describe the FTLB, and only if it is
763 * present according to Config.MT.
764 */
765 if (!cpu_has_mips_r6)
766 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
767 else if (cpu_has_ftlb)
768 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
769 else
770 mmuextdef = 0;
771
772 switch (mmuextdef) {
773 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
774 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
775 c->tlbsizevtlb = c->tlbsize;
776 break;
777 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
778 c->tlbsizevtlb +=
779 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
780 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
781 c->tlbsize = c->tlbsizevtlb;
782 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
783 /* fall through */
784 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
785 if (mips_ftlb_disabled)
786 break;
787 newcf4 = (config4 & ~ftlb_page) |
788 (page_size_ftlb(mmuextdef) <<
789 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
790 write_c0_config4(newcf4);
791 back_to_back_c0_hazard();
792 config4 = read_c0_config4();
793 if (config4 != newcf4) {
794 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
795 PAGE_SIZE, config4);
796 /* Switch FTLB off */
797 set_ftlb_enable(c, 0);
798 mips_ftlb_disabled = 1;
799 break;
800 }
801 c->tlbsizeftlbsets = 1 <<
802 ((config4 & MIPS_CONF4_FTLBSETS) >>
803 MIPS_CONF4_FTLBSETS_SHIFT);
804 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
805 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
806 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
807 mips_has_ftlb_configured = 1;
808 break;
809 }
810 }
811
812 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
813 >> MIPS_CONF4_KSCREXIST_SHIFT;
814
815 asid_mask = MIPS_ENTRYHI_ASID;
816 if (config4 & MIPS_CONF4_AE)
817 asid_mask |= MIPS_ENTRYHI_ASIDX;
818 set_cpu_asid_mask(c, asid_mask);
819
820 /*
821 * Warn if the computed ASID mask doesn't match the mask the kernel
822 * is built for. This may indicate either a serious problem or an
823 * easy optimisation opportunity, but either way should be addressed.
824 */
825 WARN_ON(asid_mask != cpu_asid_mask(c));
826
827 return config4 & MIPS_CONF_M;
828 }
829
830 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
831 {
832 unsigned int config5;
833
834 config5 = read_c0_config5();
835 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
836 write_c0_config5(config5);
837
838 if (config5 & MIPS_CONF5_EVA)
839 c->options |= MIPS_CPU_EVA;
840 if (config5 & MIPS_CONF5_MRP)
841 c->options |= MIPS_CPU_MAAR;
842 if (config5 & MIPS_CONF5_LLB)
843 c->options |= MIPS_CPU_RW_LLB;
844 if (config5 & MIPS_CONF5_MVH)
845 c->options |= MIPS_CPU_MVH;
846 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
847 c->options |= MIPS_CPU_VP;
848 if (config5 & MIPS_CONF5_CA2)
849 c->ases |= MIPS_ASE_MIPS16E2;
850
851 return config5 & MIPS_CONF_M;
852 }
853
854 static void decode_configs(struct cpuinfo_mips *c)
855 {
856 int ok;
857
858 /* MIPS32 or MIPS64 compliant CPU. */
859 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
860 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
861
862 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
863
864 /* Enable FTLB if present and not disabled */
865 set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN);
866
867 ok = decode_config0(c); /* Read Config registers. */
868 BUG_ON(!ok); /* Arch spec violation! */
869 if (ok)
870 ok = decode_config1(c);
871 if (ok)
872 ok = decode_config2(c);
873 if (ok)
874 ok = decode_config3(c);
875 if (ok)
876 ok = decode_config4(c);
877 if (ok)
878 ok = decode_config5(c);
879
880 /* Probe the EBase.WG bit */
881 if (cpu_has_mips_r2_r6) {
882 u64 ebase;
883 unsigned int status;
884
885 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
886 ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
887 : (s32)read_c0_ebase();
888 if (ebase & MIPS_EBASE_WG) {
889 /* WG bit already set, we can avoid the clumsy probe */
890 c->options |= MIPS_CPU_EBASE_WG;
891 } else {
892 /* Its UNDEFINED to change EBase while BEV=0 */
893 status = read_c0_status();
894 write_c0_status(status | ST0_BEV);
895 irq_enable_hazard();
896 /*
897 * On pre-r6 cores, this may well clobber the upper bits
898 * of EBase. This is hard to avoid without potentially
899 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
900 */
901 if (cpu_has_mips64r6)
902 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
903 else
904 write_c0_ebase(ebase | MIPS_EBASE_WG);
905 back_to_back_c0_hazard();
906 /* Restore BEV */
907 write_c0_status(status);
908 if (read_c0_ebase() & MIPS_EBASE_WG) {
909 c->options |= MIPS_CPU_EBASE_WG;
910 write_c0_ebase(ebase);
911 }
912 }
913 }
914
915 /* configure the FTLB write probability */
916 set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB);
917
918 mips_probe_watch_registers(c);
919
920 #ifndef CONFIG_MIPS_CPS
921 if (cpu_has_mips_r2_r6) {
922 unsigned int core;
923
924 core = get_ebase_cpunum();
925 if (cpu_has_mipsmt)
926 core >>= fls(core_nvpes()) - 1;
927 cpu_set_core(c, core);
928 }
929 #endif
930 }
931
932 /*
933 * Probe for certain guest capabilities by writing config bits and reading back.
934 * Finally write back the original value.
935 */
936 #define probe_gc0_config(name, maxconf, bits) \
937 do { \
938 unsigned int tmp; \
939 tmp = read_gc0_##name(); \
940 write_gc0_##name(tmp | (bits)); \
941 back_to_back_c0_hazard(); \
942 maxconf = read_gc0_##name(); \
943 write_gc0_##name(tmp); \
944 } while (0)
945
946 /*
947 * Probe for dynamic guest capabilities by changing certain config bits and
948 * reading back to see if they change. Finally write back the original value.
949 */
950 #define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \
951 do { \
952 maxconf = read_gc0_##name(); \
953 write_gc0_##name(maxconf ^ (bits)); \
954 back_to_back_c0_hazard(); \
955 dynconf = maxconf ^ read_gc0_##name(); \
956 write_gc0_##name(maxconf); \
957 maxconf |= dynconf; \
958 } while (0)
959
960 static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c)
961 {
962 unsigned int config0;
963
964 probe_gc0_config(config, config0, MIPS_CONF_M);
965
966 if (config0 & MIPS_CONF_M)
967 c->guest.conf |= BIT(1);
968 return config0 & MIPS_CONF_M;
969 }
970
971 static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c)
972 {
973 unsigned int config1, config1_dyn;
974
975 probe_gc0_config_dyn(config1, config1, config1_dyn,
976 MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR |
977 MIPS_CONF1_FP);
978
979 if (config1 & MIPS_CONF1_FP)
980 c->guest.options |= MIPS_CPU_FPU;
981 if (config1_dyn & MIPS_CONF1_FP)
982 c->guest.options_dyn |= MIPS_CPU_FPU;
983
984 if (config1 & MIPS_CONF1_WR)
985 c->guest.options |= MIPS_CPU_WATCH;
986 if (config1_dyn & MIPS_CONF1_WR)
987 c->guest.options_dyn |= MIPS_CPU_WATCH;
988
989 if (config1 & MIPS_CONF1_PC)
990 c->guest.options |= MIPS_CPU_PERF;
991 if (config1_dyn & MIPS_CONF1_PC)
992 c->guest.options_dyn |= MIPS_CPU_PERF;
993
994 if (config1 & MIPS_CONF_M)
995 c->guest.conf |= BIT(2);
996 return config1 & MIPS_CONF_M;
997 }
998
999 static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c)
1000 {
1001 unsigned int config2;
1002
1003 probe_gc0_config(config2, config2, MIPS_CONF_M);
1004
1005 if (config2 & MIPS_CONF_M)
1006 c->guest.conf |= BIT(3);
1007 return config2 & MIPS_CONF_M;
1008 }
1009
1010 static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c)
1011 {
1012 unsigned int config3, config3_dyn;
1013
1014 probe_gc0_config_dyn(config3, config3, config3_dyn,
1015 MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI |
1016 MIPS_CONF3_CTXTC);
1017
1018 if (config3 & MIPS_CONF3_CTXTC)
1019 c->guest.options |= MIPS_CPU_CTXTC;
1020 if (config3_dyn & MIPS_CONF3_CTXTC)
1021 c->guest.options_dyn |= MIPS_CPU_CTXTC;
1022
1023 if (config3 & MIPS_CONF3_PW)
1024 c->guest.options |= MIPS_CPU_HTW;
1025
1026 if (config3 & MIPS_CONF3_ULRI)
1027 c->guest.options |= MIPS_CPU_ULRI;
1028
1029 if (config3 & MIPS_CONF3_SC)
1030 c->guest.options |= MIPS_CPU_SEGMENTS;
1031
1032 if (config3 & MIPS_CONF3_BI)
1033 c->guest.options |= MIPS_CPU_BADINSTR;
1034 if (config3 & MIPS_CONF3_BP)
1035 c->guest.options |= MIPS_CPU_BADINSTRP;
1036
1037 if (config3 & MIPS_CONF3_MSA)
1038 c->guest.ases |= MIPS_ASE_MSA;
1039 if (config3_dyn & MIPS_CONF3_MSA)
1040 c->guest.ases_dyn |= MIPS_ASE_MSA;
1041
1042 if (config3 & MIPS_CONF_M)
1043 c->guest.conf |= BIT(4);
1044 return config3 & MIPS_CONF_M;
1045 }
1046
1047 static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c)
1048 {
1049 unsigned int config4;
1050
1051 probe_gc0_config(config4, config4,
1052 MIPS_CONF_M | MIPS_CONF4_KSCREXIST);
1053
1054 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
1055 >> MIPS_CONF4_KSCREXIST_SHIFT;
1056
1057 if (config4 & MIPS_CONF_M)
1058 c->guest.conf |= BIT(5);
1059 return config4 & MIPS_CONF_M;
1060 }
1061
1062 static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
1063 {
1064 unsigned int config5, config5_dyn;
1065
1066 probe_gc0_config_dyn(config5, config5, config5_dyn,
1067 MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP);
1068
1069 if (config5 & MIPS_CONF5_MRP)
1070 c->guest.options |= MIPS_CPU_MAAR;
1071 if (config5_dyn & MIPS_CONF5_MRP)
1072 c->guest.options_dyn |= MIPS_CPU_MAAR;
1073
1074 if (config5 & MIPS_CONF5_LLB)
1075 c->guest.options |= MIPS_CPU_RW_LLB;
1076
1077 if (config5 & MIPS_CONF5_MVH)
1078 c->guest.options |= MIPS_CPU_MVH;
1079
1080 if (config5 & MIPS_CONF_M)
1081 c->guest.conf |= BIT(6);
1082 return config5 & MIPS_CONF_M;
1083 }
1084
1085 static inline void decode_guest_configs(struct cpuinfo_mips *c)
1086 {
1087 unsigned int ok;
1088
1089 ok = decode_guest_config0(c);
1090 if (ok)
1091 ok = decode_guest_config1(c);
1092 if (ok)
1093 ok = decode_guest_config2(c);
1094 if (ok)
1095 ok = decode_guest_config3(c);
1096 if (ok)
1097 ok = decode_guest_config4(c);
1098 if (ok)
1099 decode_guest_config5(c);
1100 }
1101
1102 static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c)
1103 {
1104 unsigned int guestctl0, temp;
1105
1106 guestctl0 = read_c0_guestctl0();
1107
1108 if (guestctl0 & MIPS_GCTL0_G0E)
1109 c->options |= MIPS_CPU_GUESTCTL0EXT;
1110 if (guestctl0 & MIPS_GCTL0_G1)
1111 c->options |= MIPS_CPU_GUESTCTL1;
1112 if (guestctl0 & MIPS_GCTL0_G2)
1113 c->options |= MIPS_CPU_GUESTCTL2;
1114 if (!(guestctl0 & MIPS_GCTL0_RAD)) {
1115 c->options |= MIPS_CPU_GUESTID;
1116
1117 /*
1118 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0
1119 * first, otherwise all data accesses will be fully virtualised
1120 * as if they were performed by guest mode.
1121 */
1122 write_c0_guestctl1(0);
1123 tlbw_use_hazard();
1124
1125 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG);
1126 back_to_back_c0_hazard();
1127 temp = read_c0_guestctl0();
1128
1129 if (temp & MIPS_GCTL0_DRG) {
1130 write_c0_guestctl0(guestctl0);
1131 c->options |= MIPS_CPU_DRG;
1132 }
1133 }
1134 }
1135
1136 static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c)
1137 {
1138 if (cpu_has_guestid) {
1139 /* determine the number of bits of GuestID available */
1140 write_c0_guestctl1(MIPS_GCTL1_ID);
1141 back_to_back_c0_hazard();
1142 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID)
1143 >> MIPS_GCTL1_ID_SHIFT;
1144 write_c0_guestctl1(0);
1145 }
1146 }
1147
1148 static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c)
1149 {
1150 /* determine the number of bits of GTOffset available */
1151 write_c0_gtoffset(0xffffffff);
1152 back_to_back_c0_hazard();
1153 c->gtoffset_mask = read_c0_gtoffset();
1154 write_c0_gtoffset(0);
1155 }
1156
1157 static inline void cpu_probe_vz(struct cpuinfo_mips *c)
1158 {
1159 cpu_probe_guestctl0(c);
1160 if (cpu_has_guestctl1)
1161 cpu_probe_guestctl1(c);
1162
1163 cpu_probe_gtoffset(c);
1164
1165 decode_guest_configs(c);
1166 }
1167
1168 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1169 | MIPS_CPU_COUNTER)
1170
1171 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1172 {
1173 switch (c->processor_id & PRID_IMP_MASK) {
1174 case PRID_IMP_R2000:
1175 c->cputype = CPU_R2000;
1176 __cpu_name[cpu] = "R2000";
1177 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1178 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1179 MIPS_CPU_NOFPUEX;
1180 if (__cpu_has_fpu())
1181 c->options |= MIPS_CPU_FPU;
1182 c->tlbsize = 64;
1183 break;
1184 case PRID_IMP_R3000:
1185 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
1186 if (cpu_has_confreg()) {
1187 c->cputype = CPU_R3081E;
1188 __cpu_name[cpu] = "R3081";
1189 } else {
1190 c->cputype = CPU_R3000A;
1191 __cpu_name[cpu] = "R3000A";
1192 }
1193 } else {
1194 c->cputype = CPU_R3000;
1195 __cpu_name[cpu] = "R3000";
1196 }
1197 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1198 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1199 MIPS_CPU_NOFPUEX;
1200 if (__cpu_has_fpu())
1201 c->options |= MIPS_CPU_FPU;
1202 c->tlbsize = 64;
1203 break;
1204 case PRID_IMP_R4000:
1205 if (read_c0_config() & CONF_SC) {
1206 if ((c->processor_id & PRID_REV_MASK) >=
1207 PRID_REV_R4400) {
1208 c->cputype = CPU_R4400PC;
1209 __cpu_name[cpu] = "R4400PC";
1210 } else {
1211 c->cputype = CPU_R4000PC;
1212 __cpu_name[cpu] = "R4000PC";
1213 }
1214 } else {
1215 int cca = read_c0_config() & CONF_CM_CMASK;
1216 int mc;
1217
1218 /*
1219 * SC and MC versions can't be reliably told apart,
1220 * but only the latter support coherent caching
1221 * modes so assume the firmware has set the KSEG0
1222 * coherency attribute reasonably (if uncached, we
1223 * assume SC).
1224 */
1225 switch (cca) {
1226 case CONF_CM_CACHABLE_CE:
1227 case CONF_CM_CACHABLE_COW:
1228 case CONF_CM_CACHABLE_CUW:
1229 mc = 1;
1230 break;
1231 default:
1232 mc = 0;
1233 break;
1234 }
1235 if ((c->processor_id & PRID_REV_MASK) >=
1236 PRID_REV_R4400) {
1237 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
1238 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
1239 } else {
1240 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
1241 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
1242 }
1243 }
1244
1245 set_isa(c, MIPS_CPU_ISA_III);
1246 c->fpu_msk31 |= FPU_CSR_CONDX;
1247 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1248 MIPS_CPU_WATCH | MIPS_CPU_VCE |
1249 MIPS_CPU_LLSC;
1250 c->tlbsize = 48;
1251 break;
1252 case PRID_IMP_VR41XX:
1253 set_isa(c, MIPS_CPU_ISA_III);
1254 c->fpu_msk31 |= FPU_CSR_CONDX;
1255 c->options = R4K_OPTS;
1256 c->tlbsize = 32;
1257 switch (c->processor_id & 0xf0) {
1258 case PRID_REV_VR4111:
1259 c->cputype = CPU_VR4111;
1260 __cpu_name[cpu] = "NEC VR4111";
1261 break;
1262 case PRID_REV_VR4121:
1263 c->cputype = CPU_VR4121;
1264 __cpu_name[cpu] = "NEC VR4121";
1265 break;
1266 case PRID_REV_VR4122:
1267 if ((c->processor_id & 0xf) < 0x3) {
1268 c->cputype = CPU_VR4122;
1269 __cpu_name[cpu] = "NEC VR4122";
1270 } else {
1271 c->cputype = CPU_VR4181A;
1272 __cpu_name[cpu] = "NEC VR4181A";
1273 }
1274 break;
1275 case PRID_REV_VR4130:
1276 if ((c->processor_id & 0xf) < 0x4) {
1277 c->cputype = CPU_VR4131;
1278 __cpu_name[cpu] = "NEC VR4131";
1279 } else {
1280 c->cputype = CPU_VR4133;
1281 c->options |= MIPS_CPU_LLSC;
1282 __cpu_name[cpu] = "NEC VR4133";
1283 }
1284 break;
1285 default:
1286 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
1287 c->cputype = CPU_VR41XX;
1288 __cpu_name[cpu] = "NEC Vr41xx";
1289 break;
1290 }
1291 break;
1292 case PRID_IMP_R4300:
1293 c->cputype = CPU_R4300;
1294 __cpu_name[cpu] = "R4300";
1295 set_isa(c, MIPS_CPU_ISA_III);
1296 c->fpu_msk31 |= FPU_CSR_CONDX;
1297 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1298 MIPS_CPU_LLSC;
1299 c->tlbsize = 32;
1300 break;
1301 case PRID_IMP_R4600:
1302 c->cputype = CPU_R4600;
1303 __cpu_name[cpu] = "R4600";
1304 set_isa(c, MIPS_CPU_ISA_III);
1305 c->fpu_msk31 |= FPU_CSR_CONDX;
1306 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1307 MIPS_CPU_LLSC;
1308 c->tlbsize = 48;
1309 break;
1310 #if 0
1311 case PRID_IMP_R4650:
1312 /*
1313 * This processor doesn't have an MMU, so it's not
1314 * "real easy" to run Linux on it. It is left purely
1315 * for documentation. Commented out because it shares
1316 * it's c0_prid id number with the TX3900.
1317 */
1318 c->cputype = CPU_R4650;
1319 __cpu_name[cpu] = "R4650";
1320 set_isa(c, MIPS_CPU_ISA_III);
1321 c->fpu_msk31 |= FPU_CSR_CONDX;
1322 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
1323 c->tlbsize = 48;
1324 break;
1325 #endif
1326 case PRID_IMP_TX39:
1327 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1328 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1329
1330 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1331 c->cputype = CPU_TX3927;
1332 __cpu_name[cpu] = "TX3927";
1333 c->tlbsize = 64;
1334 } else {
1335 switch (c->processor_id & PRID_REV_MASK) {
1336 case PRID_REV_TX3912:
1337 c->cputype = CPU_TX3912;
1338 __cpu_name[cpu] = "TX3912";
1339 c->tlbsize = 32;
1340 break;
1341 case PRID_REV_TX3922:
1342 c->cputype = CPU_TX3922;
1343 __cpu_name[cpu] = "TX3922";
1344 c->tlbsize = 64;
1345 break;
1346 }
1347 }
1348 break;
1349 case PRID_IMP_R4700:
1350 c->cputype = CPU_R4700;
1351 __cpu_name[cpu] = "R4700";
1352 set_isa(c, MIPS_CPU_ISA_III);
1353 c->fpu_msk31 |= FPU_CSR_CONDX;
1354 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1355 MIPS_CPU_LLSC;
1356 c->tlbsize = 48;
1357 break;
1358 case PRID_IMP_TX49:
1359 c->cputype = CPU_TX49XX;
1360 __cpu_name[cpu] = "R49XX";
1361 set_isa(c, MIPS_CPU_ISA_III);
1362 c->fpu_msk31 |= FPU_CSR_CONDX;
1363 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1364 if (!(c->processor_id & 0x08))
1365 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1366 c->tlbsize = 48;
1367 break;
1368 case PRID_IMP_R5000:
1369 c->cputype = CPU_R5000;
1370 __cpu_name[cpu] = "R5000";
1371 set_isa(c, MIPS_CPU_ISA_IV);
1372 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1373 MIPS_CPU_LLSC;
1374 c->tlbsize = 48;
1375 break;
1376 case PRID_IMP_R5432:
1377 c->cputype = CPU_R5432;
1378 __cpu_name[cpu] = "R5432";
1379 set_isa(c, MIPS_CPU_ISA_IV);
1380 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1381 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1382 c->tlbsize = 48;
1383 break;
1384 case PRID_IMP_R5500:
1385 c->cputype = CPU_R5500;
1386 __cpu_name[cpu] = "R5500";
1387 set_isa(c, MIPS_CPU_ISA_IV);
1388 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1389 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1390 c->tlbsize = 48;
1391 break;
1392 case PRID_IMP_NEVADA:
1393 c->cputype = CPU_NEVADA;
1394 __cpu_name[cpu] = "Nevada";
1395 set_isa(c, MIPS_CPU_ISA_IV);
1396 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1397 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1398 c->tlbsize = 48;
1399 break;
1400 case PRID_IMP_RM7000:
1401 c->cputype = CPU_RM7000;
1402 __cpu_name[cpu] = "RM7000";
1403 set_isa(c, MIPS_CPU_ISA_IV);
1404 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1405 MIPS_CPU_LLSC;
1406 /*
1407 * Undocumented RM7000: Bit 29 in the info register of
1408 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1409 * entries.
1410 *
1411 * 29 1 => 64 entry JTLB
1412 * 0 => 48 entry JTLB
1413 */
1414 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1415 break;
1416 case PRID_IMP_R8000:
1417 c->cputype = CPU_R8000;
1418 __cpu_name[cpu] = "RM8000";
1419 set_isa(c, MIPS_CPU_ISA_IV);
1420 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
1421 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1422 MIPS_CPU_LLSC;
1423 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
1424 break;
1425 case PRID_IMP_R10000:
1426 c->cputype = CPU_R10000;
1427 __cpu_name[cpu] = "R10000";
1428 set_isa(c, MIPS_CPU_ISA_IV);
1429 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1430 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1431 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1432 MIPS_CPU_LLSC;
1433 c->tlbsize = 64;
1434 break;
1435 case PRID_IMP_R12000:
1436 c->cputype = CPU_R12000;
1437 __cpu_name[cpu] = "R12000";
1438 set_isa(c, MIPS_CPU_ISA_IV);
1439 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1440 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1441 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1442 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1443 c->tlbsize = 64;
1444 break;
1445 case PRID_IMP_R14000:
1446 if (((c->processor_id >> 4) & 0x0f) > 2) {
1447 c->cputype = CPU_R16000;
1448 __cpu_name[cpu] = "R16000";
1449 } else {
1450 c->cputype = CPU_R14000;
1451 __cpu_name[cpu] = "R14000";
1452 }
1453 set_isa(c, MIPS_CPU_ISA_IV);
1454 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1455 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1456 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1457 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1458 c->tlbsize = 64;
1459 break;
1460 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1461 switch (c->processor_id & PRID_REV_MASK) {
1462 case PRID_REV_LOONGSON2E:
1463 c->cputype = CPU_LOONGSON2;
1464 __cpu_name[cpu] = "ICT Loongson-2";
1465 set_elf_platform(cpu, "loongson2e");
1466 set_isa(c, MIPS_CPU_ISA_III);
1467 c->fpu_msk31 |= FPU_CSR_CONDX;
1468 break;
1469 case PRID_REV_LOONGSON2F:
1470 c->cputype = CPU_LOONGSON2;
1471 __cpu_name[cpu] = "ICT Loongson-2";
1472 set_elf_platform(cpu, "loongson2f");
1473 set_isa(c, MIPS_CPU_ISA_III);
1474 c->fpu_msk31 |= FPU_CSR_CONDX;
1475 break;
1476 case PRID_REV_LOONGSON3A_R1:
1477 c->cputype = CPU_LOONGSON3;
1478 __cpu_name[cpu] = "ICT Loongson-3";
1479 set_elf_platform(cpu, "loongson3a");
1480 set_isa(c, MIPS_CPU_ISA_M64R1);
1481 break;
1482 case PRID_REV_LOONGSON3B_R1:
1483 case PRID_REV_LOONGSON3B_R2:
1484 c->cputype = CPU_LOONGSON3;
1485 __cpu_name[cpu] = "ICT Loongson-3";
1486 set_elf_platform(cpu, "loongson3b");
1487 set_isa(c, MIPS_CPU_ISA_M64R1);
1488 break;
1489 }
1490
1491 c->options = R4K_OPTS |
1492 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1493 MIPS_CPU_32FPR;
1494 c->tlbsize = 64;
1495 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1496 break;
1497 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
1498 decode_configs(c);
1499
1500 c->cputype = CPU_LOONGSON1;
1501
1502 switch (c->processor_id & PRID_REV_MASK) {
1503 case PRID_REV_LOONGSON1B:
1504 __cpu_name[cpu] = "Loongson 1B";
1505 break;
1506 }
1507
1508 break;
1509 }
1510 }
1511
1512 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1513 {
1514 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1515 switch (c->processor_id & PRID_IMP_MASK) {
1516 case PRID_IMP_QEMU_GENERIC:
1517 c->writecombine = _CACHE_UNCACHED;
1518 c->cputype = CPU_QEMU_GENERIC;
1519 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1520 break;
1521 case PRID_IMP_4KC:
1522 c->cputype = CPU_4KC;
1523 c->writecombine = _CACHE_UNCACHED;
1524 __cpu_name[cpu] = "MIPS 4Kc";
1525 break;
1526 case PRID_IMP_4KEC:
1527 case PRID_IMP_4KECR2:
1528 c->cputype = CPU_4KEC;
1529 c->writecombine = _CACHE_UNCACHED;
1530 __cpu_name[cpu] = "MIPS 4KEc";
1531 break;
1532 case PRID_IMP_4KSC:
1533 case PRID_IMP_4KSD:
1534 c->cputype = CPU_4KSC;
1535 c->writecombine = _CACHE_UNCACHED;
1536 __cpu_name[cpu] = "MIPS 4KSc";
1537 break;
1538 case PRID_IMP_5KC:
1539 c->cputype = CPU_5KC;
1540 c->writecombine = _CACHE_UNCACHED;
1541 __cpu_name[cpu] = "MIPS 5Kc";
1542 break;
1543 case PRID_IMP_5KE:
1544 c->cputype = CPU_5KE;
1545 c->writecombine = _CACHE_UNCACHED;
1546 __cpu_name[cpu] = "MIPS 5KE";
1547 break;
1548 case PRID_IMP_20KC:
1549 c->cputype = CPU_20KC;
1550 c->writecombine = _CACHE_UNCACHED;
1551 __cpu_name[cpu] = "MIPS 20Kc";
1552 break;
1553 case PRID_IMP_24K:
1554 c->cputype = CPU_24K;
1555 c->writecombine = _CACHE_UNCACHED;
1556 __cpu_name[cpu] = "MIPS 24Kc";
1557 break;
1558 case PRID_IMP_24KE:
1559 c->cputype = CPU_24K;
1560 c->writecombine = _CACHE_UNCACHED;
1561 __cpu_name[cpu] = "MIPS 24KEc";
1562 break;
1563 case PRID_IMP_25KF:
1564 c->cputype = CPU_25KF;
1565 c->writecombine = _CACHE_UNCACHED;
1566 __cpu_name[cpu] = "MIPS 25Kc";
1567 break;
1568 case PRID_IMP_34K:
1569 c->cputype = CPU_34K;
1570 c->writecombine = _CACHE_UNCACHED;
1571 __cpu_name[cpu] = "MIPS 34Kc";
1572 break;
1573 case PRID_IMP_74K:
1574 c->cputype = CPU_74K;
1575 c->writecombine = _CACHE_UNCACHED;
1576 __cpu_name[cpu] = "MIPS 74Kc";
1577 break;
1578 case PRID_IMP_M14KC:
1579 c->cputype = CPU_M14KC;
1580 c->writecombine = _CACHE_UNCACHED;
1581 __cpu_name[cpu] = "MIPS M14Kc";
1582 break;
1583 case PRID_IMP_M14KEC:
1584 c->cputype = CPU_M14KEC;
1585 c->writecombine = _CACHE_UNCACHED;
1586 __cpu_name[cpu] = "MIPS M14KEc";
1587 break;
1588 case PRID_IMP_1004K:
1589 c->cputype = CPU_1004K;
1590 c->writecombine = _CACHE_UNCACHED;
1591 __cpu_name[cpu] = "MIPS 1004Kc";
1592 break;
1593 case PRID_IMP_1074K:
1594 c->cputype = CPU_1074K;
1595 c->writecombine = _CACHE_UNCACHED;
1596 __cpu_name[cpu] = "MIPS 1074Kc";
1597 break;
1598 case PRID_IMP_INTERAPTIV_UP:
1599 c->cputype = CPU_INTERAPTIV;
1600 __cpu_name[cpu] = "MIPS interAptiv";
1601 break;
1602 case PRID_IMP_INTERAPTIV_MP:
1603 c->cputype = CPU_INTERAPTIV;
1604 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1605 break;
1606 case PRID_IMP_PROAPTIV_UP:
1607 c->cputype = CPU_PROAPTIV;
1608 __cpu_name[cpu] = "MIPS proAptiv";
1609 break;
1610 case PRID_IMP_PROAPTIV_MP:
1611 c->cputype = CPU_PROAPTIV;
1612 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1613 break;
1614 case PRID_IMP_P5600:
1615 c->cputype = CPU_P5600;
1616 __cpu_name[cpu] = "MIPS P5600";
1617 break;
1618 case PRID_IMP_P6600:
1619 c->cputype = CPU_P6600;
1620 __cpu_name[cpu] = "MIPS P6600";
1621 break;
1622 case PRID_IMP_I6400:
1623 c->cputype = CPU_I6400;
1624 __cpu_name[cpu] = "MIPS I6400";
1625 break;
1626 case PRID_IMP_I6500:
1627 c->cputype = CPU_I6500;
1628 __cpu_name[cpu] = "MIPS I6500";
1629 break;
1630 case PRID_IMP_M5150:
1631 c->cputype = CPU_M5150;
1632 __cpu_name[cpu] = "MIPS M5150";
1633 break;
1634 case PRID_IMP_M6250:
1635 c->cputype = CPU_M6250;
1636 __cpu_name[cpu] = "MIPS M6250";
1637 break;
1638 }
1639
1640 decode_configs(c);
1641
1642 spram_config();
1643
1644 switch (__get_cpu_type(c->cputype)) {
1645 case CPU_I6500:
1646 c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES;
1647 /* fall-through */
1648 case CPU_I6400:
1649 c->options |= MIPS_CPU_SHARED_FTLB_RAM;
1650 /* fall-through */
1651 default:
1652 break;
1653 }
1654 }
1655
1656 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1657 {
1658 decode_configs(c);
1659 switch (c->processor_id & PRID_IMP_MASK) {
1660 case PRID_IMP_AU1_REV1:
1661 case PRID_IMP_AU1_REV2:
1662 c->cputype = CPU_ALCHEMY;
1663 switch ((c->processor_id >> 24) & 0xff) {
1664 case 0:
1665 __cpu_name[cpu] = "Au1000";
1666 break;
1667 case 1:
1668 __cpu_name[cpu] = "Au1500";
1669 break;
1670 case 2:
1671 __cpu_name[cpu] = "Au1100";
1672 break;
1673 case 3:
1674 __cpu_name[cpu] = "Au1550";
1675 break;
1676 case 4:
1677 __cpu_name[cpu] = "Au1200";
1678 if ((c->processor_id & PRID_REV_MASK) == 2)
1679 __cpu_name[cpu] = "Au1250";
1680 break;
1681 case 5:
1682 __cpu_name[cpu] = "Au1210";
1683 break;
1684 default:
1685 __cpu_name[cpu] = "Au1xxx";
1686 break;
1687 }
1688 break;
1689 }
1690 }
1691
1692 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1693 {
1694 decode_configs(c);
1695
1696 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1697 switch (c->processor_id & PRID_IMP_MASK) {
1698 case PRID_IMP_SB1:
1699 c->cputype = CPU_SB1;
1700 __cpu_name[cpu] = "SiByte SB1";
1701 /* FPU in pass1 is known to have issues. */
1702 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1703 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1704 break;
1705 case PRID_IMP_SB1A:
1706 c->cputype = CPU_SB1A;
1707 __cpu_name[cpu] = "SiByte SB1A";
1708 break;
1709 }
1710 }
1711
1712 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1713 {
1714 decode_configs(c);
1715 switch (c->processor_id & PRID_IMP_MASK) {
1716 case PRID_IMP_SR71000:
1717 c->cputype = CPU_SR71000;
1718 __cpu_name[cpu] = "Sandcraft SR71000";
1719 c->scache.ways = 8;
1720 c->tlbsize = 64;
1721 break;
1722 }
1723 }
1724
1725 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1726 {
1727 decode_configs(c);
1728 switch (c->processor_id & PRID_IMP_MASK) {
1729 case PRID_IMP_PR4450:
1730 c->cputype = CPU_PR4450;
1731 __cpu_name[cpu] = "Philips PR4450";
1732 set_isa(c, MIPS_CPU_ISA_M32R1);
1733 break;
1734 }
1735 }
1736
1737 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1738 {
1739 decode_configs(c);
1740 switch (c->processor_id & PRID_IMP_MASK) {
1741 case PRID_IMP_BMIPS32_REV4:
1742 case PRID_IMP_BMIPS32_REV8:
1743 c->cputype = CPU_BMIPS32;
1744 __cpu_name[cpu] = "Broadcom BMIPS32";
1745 set_elf_platform(cpu, "bmips32");
1746 break;
1747 case PRID_IMP_BMIPS3300:
1748 case PRID_IMP_BMIPS3300_ALT:
1749 case PRID_IMP_BMIPS3300_BUG:
1750 c->cputype = CPU_BMIPS3300;
1751 __cpu_name[cpu] = "Broadcom BMIPS3300";
1752 set_elf_platform(cpu, "bmips3300");
1753 break;
1754 case PRID_IMP_BMIPS43XX: {
1755 int rev = c->processor_id & PRID_REV_MASK;
1756
1757 if (rev >= PRID_REV_BMIPS4380_LO &&
1758 rev <= PRID_REV_BMIPS4380_HI) {
1759 c->cputype = CPU_BMIPS4380;
1760 __cpu_name[cpu] = "Broadcom BMIPS4380";
1761 set_elf_platform(cpu, "bmips4380");
1762 c->options |= MIPS_CPU_RIXI;
1763 } else {
1764 c->cputype = CPU_BMIPS4350;
1765 __cpu_name[cpu] = "Broadcom BMIPS4350";
1766 set_elf_platform(cpu, "bmips4350");
1767 }
1768 break;
1769 }
1770 case PRID_IMP_BMIPS5000:
1771 case PRID_IMP_BMIPS5200:
1772 c->cputype = CPU_BMIPS5000;
1773 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1774 __cpu_name[cpu] = "Broadcom BMIPS5200";
1775 else
1776 __cpu_name[cpu] = "Broadcom BMIPS5000";
1777 set_elf_platform(cpu, "bmips5000");
1778 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
1779 break;
1780 }
1781 }
1782
1783 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1784 {
1785 decode_configs(c);
1786 switch (c->processor_id & PRID_IMP_MASK) {
1787 case PRID_IMP_CAVIUM_CN38XX:
1788 case PRID_IMP_CAVIUM_CN31XX:
1789 case PRID_IMP_CAVIUM_CN30XX:
1790 c->cputype = CPU_CAVIUM_OCTEON;
1791 __cpu_name[cpu] = "Cavium Octeon";
1792 goto platform;
1793 case PRID_IMP_CAVIUM_CN58XX:
1794 case PRID_IMP_CAVIUM_CN56XX:
1795 case PRID_IMP_CAVIUM_CN50XX:
1796 case PRID_IMP_CAVIUM_CN52XX:
1797 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1798 __cpu_name[cpu] = "Cavium Octeon+";
1799 platform:
1800 set_elf_platform(cpu, "octeon");
1801 break;
1802 case PRID_IMP_CAVIUM_CN61XX:
1803 case PRID_IMP_CAVIUM_CN63XX:
1804 case PRID_IMP_CAVIUM_CN66XX:
1805 case PRID_IMP_CAVIUM_CN68XX:
1806 case PRID_IMP_CAVIUM_CNF71XX:
1807 c->cputype = CPU_CAVIUM_OCTEON2;
1808 __cpu_name[cpu] = "Cavium Octeon II";
1809 set_elf_platform(cpu, "octeon2");
1810 break;
1811 case PRID_IMP_CAVIUM_CN70XX:
1812 case PRID_IMP_CAVIUM_CN73XX:
1813 case PRID_IMP_CAVIUM_CNF75XX:
1814 case PRID_IMP_CAVIUM_CN78XX:
1815 c->cputype = CPU_CAVIUM_OCTEON3;
1816 __cpu_name[cpu] = "Cavium Octeon III";
1817 set_elf_platform(cpu, "octeon3");
1818 break;
1819 default:
1820 printk(KERN_INFO "Unknown Octeon chip!\n");
1821 c->cputype = CPU_UNKNOWN;
1822 break;
1823 }
1824 }
1825
1826 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
1827 {
1828 switch (c->processor_id & PRID_IMP_MASK) {
1829 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1830 switch (c->processor_id & PRID_REV_MASK) {
1831 case PRID_REV_LOONGSON3A_R2:
1832 c->cputype = CPU_LOONGSON3;
1833 __cpu_name[cpu] = "ICT Loongson-3";
1834 set_elf_platform(cpu, "loongson3a");
1835 set_isa(c, MIPS_CPU_ISA_M64R2);
1836 break;
1837 case PRID_REV_LOONGSON3A_R3:
1838 c->cputype = CPU_LOONGSON3;
1839 __cpu_name[cpu] = "ICT Loongson-3";
1840 set_elf_platform(cpu, "loongson3a");
1841 set_isa(c, MIPS_CPU_ISA_M64R2);
1842 break;
1843 }
1844
1845 decode_configs(c);
1846 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
1847 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1848 break;
1849 default:
1850 panic("Unknown Loongson Processor ID!");
1851 break;
1852 }
1853 }
1854
1855 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1856 {
1857 decode_configs(c);
1858 /* JZRISC does not implement the CP0 counter. */
1859 c->options &= ~MIPS_CPU_COUNTER;
1860 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1861 switch (c->processor_id & PRID_IMP_MASK) {
1862 case PRID_IMP_JZRISC:
1863 c->cputype = CPU_JZRISC;
1864 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1865 __cpu_name[cpu] = "Ingenic JZRISC";
1866 break;
1867 default:
1868 panic("Unknown Ingenic Processor ID!");
1869 break;
1870 }
1871 }
1872
1873 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1874 {
1875 decode_configs(c);
1876
1877 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1878 c->cputype = CPU_ALCHEMY;
1879 __cpu_name[cpu] = "Au1300";
1880 /* following stuff is not for Alchemy */
1881 return;
1882 }
1883
1884 c->options = (MIPS_CPU_TLB |
1885 MIPS_CPU_4KEX |
1886 MIPS_CPU_COUNTER |
1887 MIPS_CPU_DIVEC |
1888 MIPS_CPU_WATCH |
1889 MIPS_CPU_EJTAG |
1890 MIPS_CPU_LLSC);
1891
1892 switch (c->processor_id & PRID_IMP_MASK) {
1893 case PRID_IMP_NETLOGIC_XLP2XX:
1894 case PRID_IMP_NETLOGIC_XLP9XX:
1895 case PRID_IMP_NETLOGIC_XLP5XX:
1896 c->cputype = CPU_XLP;
1897 __cpu_name[cpu] = "Broadcom XLPII";
1898 break;
1899
1900 case PRID_IMP_NETLOGIC_XLP8XX:
1901 case PRID_IMP_NETLOGIC_XLP3XX:
1902 c->cputype = CPU_XLP;
1903 __cpu_name[cpu] = "Netlogic XLP";
1904 break;
1905
1906 case PRID_IMP_NETLOGIC_XLR732:
1907 case PRID_IMP_NETLOGIC_XLR716:
1908 case PRID_IMP_NETLOGIC_XLR532:
1909 case PRID_IMP_NETLOGIC_XLR308:
1910 case PRID_IMP_NETLOGIC_XLR532C:
1911 case PRID_IMP_NETLOGIC_XLR516C:
1912 case PRID_IMP_NETLOGIC_XLR508C:
1913 case PRID_IMP_NETLOGIC_XLR308C:
1914 c->cputype = CPU_XLR;
1915 __cpu_name[cpu] = "Netlogic XLR";
1916 break;
1917
1918 case PRID_IMP_NETLOGIC_XLS608:
1919 case PRID_IMP_NETLOGIC_XLS408:
1920 case PRID_IMP_NETLOGIC_XLS404:
1921 case PRID_IMP_NETLOGIC_XLS208:
1922 case PRID_IMP_NETLOGIC_XLS204:
1923 case PRID_IMP_NETLOGIC_XLS108:
1924 case PRID_IMP_NETLOGIC_XLS104:
1925 case PRID_IMP_NETLOGIC_XLS616B:
1926 case PRID_IMP_NETLOGIC_XLS608B:
1927 case PRID_IMP_NETLOGIC_XLS416B:
1928 case PRID_IMP_NETLOGIC_XLS412B:
1929 case PRID_IMP_NETLOGIC_XLS408B:
1930 case PRID_IMP_NETLOGIC_XLS404B:
1931 c->cputype = CPU_XLR;
1932 __cpu_name[cpu] = "Netlogic XLS";
1933 break;
1934
1935 default:
1936 pr_info("Unknown Netlogic chip id [%02x]!\n",
1937 c->processor_id);
1938 c->cputype = CPU_XLR;
1939 break;
1940 }
1941
1942 if (c->cputype == CPU_XLP) {
1943 set_isa(c, MIPS_CPU_ISA_M64R2);
1944 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1945 /* This will be updated again after all threads are woken up */
1946 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1947 } else {
1948 set_isa(c, MIPS_CPU_ISA_M64R1);
1949 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1950 }
1951 c->kscratch_mask = 0xf;
1952 }
1953
1954 #ifdef CONFIG_64BIT
1955 /* For use by uaccess.h */
1956 u64 __ua_limit;
1957 EXPORT_SYMBOL(__ua_limit);
1958 #endif
1959
1960 const char *__cpu_name[NR_CPUS];
1961 const char *__elf_platform;
1962
1963 void cpu_probe(void)
1964 {
1965 struct cpuinfo_mips *c = &current_cpu_data;
1966 unsigned int cpu = smp_processor_id();
1967
1968 /*
1969 * Set a default elf platform, cpu probe may later
1970 * overwrite it with a more precise value
1971 */
1972 set_elf_platform(cpu, "mips");
1973
1974 c->processor_id = PRID_IMP_UNKNOWN;
1975 c->fpu_id = FPIR_IMP_NONE;
1976 c->cputype = CPU_UNKNOWN;
1977 c->writecombine = _CACHE_UNCACHED;
1978
1979 c->fpu_csr31 = FPU_CSR_RN;
1980 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1981
1982 c->processor_id = read_c0_prid();
1983 switch (c->processor_id & PRID_COMP_MASK) {
1984 case PRID_COMP_LEGACY:
1985 cpu_probe_legacy(c, cpu);
1986 break;
1987 case PRID_COMP_MIPS:
1988 cpu_probe_mips(c, cpu);
1989 break;
1990 case PRID_COMP_ALCHEMY:
1991 cpu_probe_alchemy(c, cpu);
1992 break;
1993 case PRID_COMP_SIBYTE:
1994 cpu_probe_sibyte(c, cpu);
1995 break;
1996 case PRID_COMP_BROADCOM:
1997 cpu_probe_broadcom(c, cpu);
1998 break;
1999 case PRID_COMP_SANDCRAFT:
2000 cpu_probe_sandcraft(c, cpu);
2001 break;
2002 case PRID_COMP_NXP:
2003 cpu_probe_nxp(c, cpu);
2004 break;
2005 case PRID_COMP_CAVIUM:
2006 cpu_probe_cavium(c, cpu);
2007 break;
2008 case PRID_COMP_LOONGSON:
2009 cpu_probe_loongson(c, cpu);
2010 break;
2011 case PRID_COMP_INGENIC_D0:
2012 case PRID_COMP_INGENIC_D1:
2013 case PRID_COMP_INGENIC_E1:
2014 cpu_probe_ingenic(c, cpu);
2015 break;
2016 case PRID_COMP_NETLOGIC:
2017 cpu_probe_netlogic(c, cpu);
2018 break;
2019 }
2020
2021 BUG_ON(!__cpu_name[cpu]);
2022 BUG_ON(c->cputype == CPU_UNKNOWN);
2023
2024 /*
2025 * Platform code can force the cpu type to optimize code
2026 * generation. In that case be sure the cpu type is correctly
2027 * manually setup otherwise it could trigger some nasty bugs.
2028 */
2029 BUG_ON(current_cpu_type() != c->cputype);
2030
2031 if (cpu_has_rixi) {
2032 /* Enable the RIXI exceptions */
2033 set_c0_pagegrain(PG_IEC);
2034 back_to_back_c0_hazard();
2035 /* Verify the IEC bit is set */
2036 if (read_c0_pagegrain() & PG_IEC)
2037 c->options |= MIPS_CPU_RIXIEX;
2038 }
2039
2040 if (mips_fpu_disabled)
2041 c->options &= ~MIPS_CPU_FPU;
2042
2043 if (mips_dsp_disabled)
2044 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
2045
2046 if (mips_htw_disabled) {
2047 c->options &= ~MIPS_CPU_HTW;
2048 write_c0_pwctl(read_c0_pwctl() &
2049 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
2050 }
2051
2052 if (c->options & MIPS_CPU_FPU)
2053 cpu_set_fpu_opts(c);
2054 else
2055 cpu_set_nofpu_opts(c);
2056
2057 if (cpu_has_bp_ghist)
2058 write_c0_r10k_diag(read_c0_r10k_diag() |
2059 R10K_DIAG_E_GHIST);
2060
2061 if (cpu_has_mips_r2_r6) {
2062 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
2063 /* R2 has Performance Counter Interrupt indicator */
2064 c->options |= MIPS_CPU_PCI;
2065 }
2066 else
2067 c->srsets = 1;
2068
2069 if (cpu_has_mips_r6)
2070 elf_hwcap |= HWCAP_MIPS_R6;
2071
2072 if (cpu_has_msa) {
2073 c->msa_id = cpu_get_msa_id();
2074 WARN(c->msa_id & MSA_IR_WRPF,
2075 "Vector register partitioning unimplemented!");
2076 elf_hwcap |= HWCAP_MIPS_MSA;
2077 }
2078
2079 if (cpu_has_vz)
2080 cpu_probe_vz(c);
2081
2082 cpu_probe_vmbits(c);
2083
2084 #ifdef CONFIG_64BIT
2085 if (cpu == 0)
2086 __ua_limit = ~((1ull << cpu_vmbits) - 1);
2087 #endif
2088 }
2089
2090 void cpu_report(void)
2091 {
2092 struct cpuinfo_mips *c = &current_cpu_data;
2093
2094 pr_info("CPU%d revision is: %08x (%s)\n",
2095 smp_processor_id(), c->processor_id, cpu_name_string());
2096 if (c->options & MIPS_CPU_FPU)
2097 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
2098 if (cpu_has_msa)
2099 pr_info("MSA revision is: %08x\n", c->msa_id);
2100 }
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