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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
[mirror_ubuntu-zesty-kernel.git] / arch / mips / kernel / cpu-probe.c
1 /*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
20
21 #include <asm/bugs.h>
22 #include <asm/cpu.h>
23 #include <asm/fpu.h>
24 #include <asm/mipsregs.h>
25 #include <asm/watch.h>
26 #include <asm/elf.h>
27 #include <asm/spram.h>
28 #include <asm/uaccess.h>
29
30 /*
31 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
32 * the implementation of the "wait" feature differs between CPU families. This
33 * points to the function that implements CPU specific wait.
34 * The wait instruction stops the pipeline and reduces the power consumption of
35 * the CPU very much.
36 */
37 void (*cpu_wait)(void);
38 EXPORT_SYMBOL(cpu_wait);
39
40 static void r3081_wait(void)
41 {
42 unsigned long cfg = read_c0_conf();
43 write_c0_conf(cfg | R30XX_CONF_HALT);
44 }
45
46 static void r39xx_wait(void)
47 {
48 local_irq_disable();
49 if (!need_resched())
50 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
51 local_irq_enable();
52 }
53
54 extern void r4k_wait(void);
55
56 /*
57 * This variant is preferable as it allows testing need_resched and going to
58 * sleep depending on the outcome atomically. Unfortunately the "It is
59 * implementation-dependent whether the pipeline restarts when a non-enabled
60 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
61 * using this version a gamble.
62 */
63 void r4k_wait_irqoff(void)
64 {
65 local_irq_disable();
66 if (!need_resched())
67 __asm__(" .set push \n"
68 " .set mips3 \n"
69 " wait \n"
70 " .set pop \n");
71 local_irq_enable();
72 __asm__(" .globl __pastwait \n"
73 "__pastwait: \n");
74 }
75
76 /*
77 * The RM7000 variant has to handle erratum 38. The workaround is to not
78 * have any pending stores when the WAIT instruction is executed.
79 */
80 static void rm7k_wait_irqoff(void)
81 {
82 local_irq_disable();
83 if (!need_resched())
84 __asm__(
85 " .set push \n"
86 " .set mips3 \n"
87 " .set noat \n"
88 " mfc0 $1, $12 \n"
89 " sync \n"
90 " mtc0 $1, $12 # stalls until W stage \n"
91 " wait \n"
92 " mtc0 $1, $12 # stalls until W stage \n"
93 " .set pop \n");
94 local_irq_enable();
95 }
96
97 /*
98 * The Au1xxx wait is available only if using 32khz counter or
99 * external timer source, but specifically not CP0 Counter.
100 * alchemy/common/time.c may override cpu_wait!
101 */
102 static void au1k_wait(void)
103 {
104 __asm__(" .set mips3 \n"
105 " cache 0x14, 0(%0) \n"
106 " cache 0x14, 32(%0) \n"
107 " sync \n"
108 " nop \n"
109 " wait \n"
110 " nop \n"
111 " nop \n"
112 " nop \n"
113 " nop \n"
114 " .set mips0 \n"
115 : : "r" (au1k_wait));
116 }
117
118 static int __initdata nowait;
119
120 static int __init wait_disable(char *s)
121 {
122 nowait = 1;
123
124 return 1;
125 }
126
127 __setup("nowait", wait_disable);
128
129 static int __cpuinitdata mips_fpu_disabled;
130
131 static int __init fpu_disable(char *s)
132 {
133 cpu_data[0].options &= ~MIPS_CPU_FPU;
134 mips_fpu_disabled = 1;
135
136 return 1;
137 }
138
139 __setup("nofpu", fpu_disable);
140
141 int __cpuinitdata mips_dsp_disabled;
142
143 static int __init dsp_disable(char *s)
144 {
145 cpu_data[0].ases &= ~MIPS_ASE_DSP;
146 mips_dsp_disabled = 1;
147
148 return 1;
149 }
150
151 __setup("nodsp", dsp_disable);
152
153 void __init check_wait(void)
154 {
155 struct cpuinfo_mips *c = &current_cpu_data;
156
157 if (nowait) {
158 printk("Wait instruction disabled.\n");
159 return;
160 }
161
162 switch (c->cputype) {
163 case CPU_R3081:
164 case CPU_R3081E:
165 cpu_wait = r3081_wait;
166 break;
167 case CPU_TX3927:
168 cpu_wait = r39xx_wait;
169 break;
170 case CPU_R4200:
171 /* case CPU_R4300: */
172 case CPU_R4600:
173 case CPU_R4640:
174 case CPU_R4650:
175 case CPU_R4700:
176 case CPU_R5000:
177 case CPU_R5500:
178 case CPU_NEVADA:
179 case CPU_4KC:
180 case CPU_4KEC:
181 case CPU_4KSC:
182 case CPU_5KC:
183 case CPU_25KF:
184 case CPU_PR4450:
185 case CPU_BMIPS3300:
186 case CPU_BMIPS4350:
187 case CPU_BMIPS4380:
188 case CPU_BMIPS5000:
189 case CPU_CAVIUM_OCTEON:
190 case CPU_CAVIUM_OCTEON_PLUS:
191 case CPU_CAVIUM_OCTEON2:
192 case CPU_JZRISC:
193 case CPU_LOONGSON1:
194 case CPU_XLR:
195 case CPU_XLP:
196 cpu_wait = r4k_wait;
197 break;
198
199 case CPU_RM7000:
200 cpu_wait = rm7k_wait_irqoff;
201 break;
202
203 case CPU_M14KC:
204 case CPU_24K:
205 case CPU_34K:
206 case CPU_1004K:
207 cpu_wait = r4k_wait;
208 if (read_c0_config7() & MIPS_CONF7_WII)
209 cpu_wait = r4k_wait_irqoff;
210 break;
211
212 case CPU_74K:
213 cpu_wait = r4k_wait;
214 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
215 cpu_wait = r4k_wait_irqoff;
216 break;
217
218 case CPU_TX49XX:
219 cpu_wait = r4k_wait_irqoff;
220 break;
221 case CPU_ALCHEMY:
222 cpu_wait = au1k_wait;
223 break;
224 case CPU_20KC:
225 /*
226 * WAIT on Rev1.0 has E1, E2, E3 and E16.
227 * WAIT on Rev2.0 and Rev3.0 has E16.
228 * Rev3.1 WAIT is nop, why bother
229 */
230 if ((c->processor_id & 0xff) <= 0x64)
231 break;
232
233 /*
234 * Another rev is incremeting c0_count at a reduced clock
235 * rate while in WAIT mode. So we basically have the choice
236 * between using the cp0 timer as clocksource or avoiding
237 * the WAIT instruction. Until more details are known,
238 * disable the use of WAIT for 20Kc entirely.
239 cpu_wait = r4k_wait;
240 */
241 break;
242 case CPU_RM9000:
243 if ((c->processor_id & 0x00ff) >= 0x40)
244 cpu_wait = r4k_wait;
245 break;
246 default:
247 break;
248 }
249 }
250
251 static inline void check_errata(void)
252 {
253 struct cpuinfo_mips *c = &current_cpu_data;
254
255 switch (c->cputype) {
256 case CPU_34K:
257 /*
258 * Erratum "RPS May Cause Incorrect Instruction Execution"
259 * This code only handles VPE0, any SMP/SMTC/RTOS code
260 * making use of VPE1 will be responsable for that VPE.
261 */
262 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
263 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
264 break;
265 default:
266 break;
267 }
268 }
269
270 void __init check_bugs32(void)
271 {
272 check_errata();
273 }
274
275 /*
276 * Probe whether cpu has config register by trying to play with
277 * alternate cache bit and see whether it matters.
278 * It's used by cpu_probe to distinguish between R3000A and R3081.
279 */
280 static inline int cpu_has_confreg(void)
281 {
282 #ifdef CONFIG_CPU_R3000
283 extern unsigned long r3k_cache_size(unsigned long);
284 unsigned long size1, size2;
285 unsigned long cfg = read_c0_conf();
286
287 size1 = r3k_cache_size(ST0_ISC);
288 write_c0_conf(cfg ^ R30XX_CONF_AC);
289 size2 = r3k_cache_size(ST0_ISC);
290 write_c0_conf(cfg);
291 return size1 != size2;
292 #else
293 return 0;
294 #endif
295 }
296
297 static inline void set_elf_platform(int cpu, const char *plat)
298 {
299 if (cpu == 0)
300 __elf_platform = plat;
301 }
302
303 /*
304 * Get the FPU Implementation/Revision.
305 */
306 static inline unsigned long cpu_get_fpu_id(void)
307 {
308 unsigned long tmp, fpu_id;
309
310 tmp = read_c0_status();
311 __enable_fpu();
312 fpu_id = read_32bit_cp1_register(CP1_REVISION);
313 write_c0_status(tmp);
314 return fpu_id;
315 }
316
317 /*
318 * Check the CPU has an FPU the official way.
319 */
320 static inline int __cpu_has_fpu(void)
321 {
322 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
323 }
324
325 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
326 {
327 #ifdef __NEED_VMBITS_PROBE
328 write_c0_entryhi(0x3fffffffffffe000ULL);
329 back_to_back_c0_hazard();
330 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
331 #endif
332 }
333
334 static char unknown_isa[] __cpuinitdata = KERN_ERR \
335 "Unsupported ISA type, c0.config0: %d.";
336
337 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
338 {
339 unsigned int config0;
340 int isa;
341
342 config0 = read_c0_config();
343
344 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
345 c->options |= MIPS_CPU_TLB;
346 isa = (config0 & MIPS_CONF_AT) >> 13;
347 switch (isa) {
348 case 0:
349 switch ((config0 & MIPS_CONF_AR) >> 10) {
350 case 0:
351 c->isa_level = MIPS_CPU_ISA_M32R1;
352 break;
353 case 1:
354 c->isa_level = MIPS_CPU_ISA_M32R2;
355 break;
356 default:
357 goto unknown;
358 }
359 break;
360 case 2:
361 switch ((config0 & MIPS_CONF_AR) >> 10) {
362 case 0:
363 c->isa_level = MIPS_CPU_ISA_M64R1;
364 break;
365 case 1:
366 c->isa_level = MIPS_CPU_ISA_M64R2;
367 break;
368 default:
369 goto unknown;
370 }
371 break;
372 default:
373 goto unknown;
374 }
375
376 return config0 & MIPS_CONF_M;
377
378 unknown:
379 panic(unknown_isa, config0);
380 }
381
382 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
383 {
384 unsigned int config1;
385
386 config1 = read_c0_config1();
387
388 if (config1 & MIPS_CONF1_MD)
389 c->ases |= MIPS_ASE_MDMX;
390 if (config1 & MIPS_CONF1_WR)
391 c->options |= MIPS_CPU_WATCH;
392 if (config1 & MIPS_CONF1_CA)
393 c->ases |= MIPS_ASE_MIPS16;
394 if (config1 & MIPS_CONF1_EP)
395 c->options |= MIPS_CPU_EJTAG;
396 if (config1 & MIPS_CONF1_FP) {
397 c->options |= MIPS_CPU_FPU;
398 c->options |= MIPS_CPU_32FPR;
399 }
400 if (cpu_has_tlb)
401 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
402
403 return config1 & MIPS_CONF_M;
404 }
405
406 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
407 {
408 unsigned int config2;
409
410 config2 = read_c0_config2();
411
412 if (config2 & MIPS_CONF2_SL)
413 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
414
415 return config2 & MIPS_CONF_M;
416 }
417
418 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
419 {
420 unsigned int config3;
421
422 config3 = read_c0_config3();
423
424 if (config3 & MIPS_CONF3_SM) {
425 c->ases |= MIPS_ASE_SMARTMIPS;
426 c->options |= MIPS_CPU_RIXI;
427 }
428 if (config3 & MIPS_CONF3_RXI)
429 c->options |= MIPS_CPU_RIXI;
430 if (config3 & MIPS_CONF3_DSP)
431 c->ases |= MIPS_ASE_DSP;
432 if (config3 & MIPS_CONF3_VINT)
433 c->options |= MIPS_CPU_VINT;
434 if (config3 & MIPS_CONF3_VEIC)
435 c->options |= MIPS_CPU_VEIC;
436 if (config3 & MIPS_CONF3_MT)
437 c->ases |= MIPS_ASE_MIPSMT;
438 if (config3 & MIPS_CONF3_ULRI)
439 c->options |= MIPS_CPU_ULRI;
440
441 return config3 & MIPS_CONF_M;
442 }
443
444 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
445 {
446 unsigned int config4;
447
448 config4 = read_c0_config4();
449
450 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
451 && cpu_has_tlb)
452 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
453
454 c->kscratch_mask = (config4 >> 16) & 0xff;
455
456 return config4 & MIPS_CONF_M;
457 }
458
459 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
460 {
461 int ok;
462
463 /* MIPS32 or MIPS64 compliant CPU. */
464 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
465 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
466
467 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
468
469 ok = decode_config0(c); /* Read Config registers. */
470 BUG_ON(!ok); /* Arch spec violation! */
471 if (ok)
472 ok = decode_config1(c);
473 if (ok)
474 ok = decode_config2(c);
475 if (ok)
476 ok = decode_config3(c);
477 if (ok)
478 ok = decode_config4(c);
479
480 mips_probe_watch_registers(c);
481
482 if (cpu_has_mips_r2)
483 c->core = read_c0_ebase() & 0x3ff;
484 }
485
486 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
487 | MIPS_CPU_COUNTER)
488
489 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
490 {
491 switch (c->processor_id & 0xff00) {
492 case PRID_IMP_R2000:
493 c->cputype = CPU_R2000;
494 __cpu_name[cpu] = "R2000";
495 c->isa_level = MIPS_CPU_ISA_I;
496 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
497 MIPS_CPU_NOFPUEX;
498 if (__cpu_has_fpu())
499 c->options |= MIPS_CPU_FPU;
500 c->tlbsize = 64;
501 break;
502 case PRID_IMP_R3000:
503 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
504 if (cpu_has_confreg()) {
505 c->cputype = CPU_R3081E;
506 __cpu_name[cpu] = "R3081";
507 } else {
508 c->cputype = CPU_R3000A;
509 __cpu_name[cpu] = "R3000A";
510 }
511 break;
512 } else {
513 c->cputype = CPU_R3000;
514 __cpu_name[cpu] = "R3000";
515 }
516 c->isa_level = MIPS_CPU_ISA_I;
517 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
518 MIPS_CPU_NOFPUEX;
519 if (__cpu_has_fpu())
520 c->options |= MIPS_CPU_FPU;
521 c->tlbsize = 64;
522 break;
523 case PRID_IMP_R4000:
524 if (read_c0_config() & CONF_SC) {
525 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
526 c->cputype = CPU_R4400PC;
527 __cpu_name[cpu] = "R4400PC";
528 } else {
529 c->cputype = CPU_R4000PC;
530 __cpu_name[cpu] = "R4000PC";
531 }
532 } else {
533 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
534 c->cputype = CPU_R4400SC;
535 __cpu_name[cpu] = "R4400SC";
536 } else {
537 c->cputype = CPU_R4000SC;
538 __cpu_name[cpu] = "R4000SC";
539 }
540 }
541
542 c->isa_level = MIPS_CPU_ISA_III;
543 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
544 MIPS_CPU_WATCH | MIPS_CPU_VCE |
545 MIPS_CPU_LLSC;
546 c->tlbsize = 48;
547 break;
548 case PRID_IMP_VR41XX:
549 switch (c->processor_id & 0xf0) {
550 case PRID_REV_VR4111:
551 c->cputype = CPU_VR4111;
552 __cpu_name[cpu] = "NEC VR4111";
553 break;
554 case PRID_REV_VR4121:
555 c->cputype = CPU_VR4121;
556 __cpu_name[cpu] = "NEC VR4121";
557 break;
558 case PRID_REV_VR4122:
559 if ((c->processor_id & 0xf) < 0x3) {
560 c->cputype = CPU_VR4122;
561 __cpu_name[cpu] = "NEC VR4122";
562 } else {
563 c->cputype = CPU_VR4181A;
564 __cpu_name[cpu] = "NEC VR4181A";
565 }
566 break;
567 case PRID_REV_VR4130:
568 if ((c->processor_id & 0xf) < 0x4) {
569 c->cputype = CPU_VR4131;
570 __cpu_name[cpu] = "NEC VR4131";
571 } else {
572 c->cputype = CPU_VR4133;
573 __cpu_name[cpu] = "NEC VR4133";
574 }
575 break;
576 default:
577 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
578 c->cputype = CPU_VR41XX;
579 __cpu_name[cpu] = "NEC Vr41xx";
580 break;
581 }
582 c->isa_level = MIPS_CPU_ISA_III;
583 c->options = R4K_OPTS;
584 c->tlbsize = 32;
585 break;
586 case PRID_IMP_R4300:
587 c->cputype = CPU_R4300;
588 __cpu_name[cpu] = "R4300";
589 c->isa_level = MIPS_CPU_ISA_III;
590 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
591 MIPS_CPU_LLSC;
592 c->tlbsize = 32;
593 break;
594 case PRID_IMP_R4600:
595 c->cputype = CPU_R4600;
596 __cpu_name[cpu] = "R4600";
597 c->isa_level = MIPS_CPU_ISA_III;
598 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
599 MIPS_CPU_LLSC;
600 c->tlbsize = 48;
601 break;
602 #if 0
603 case PRID_IMP_R4650:
604 /*
605 * This processor doesn't have an MMU, so it's not
606 * "real easy" to run Linux on it. It is left purely
607 * for documentation. Commented out because it shares
608 * it's c0_prid id number with the TX3900.
609 */
610 c->cputype = CPU_R4650;
611 __cpu_name[cpu] = "R4650";
612 c->isa_level = MIPS_CPU_ISA_III;
613 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
614 c->tlbsize = 48;
615 break;
616 #endif
617 case PRID_IMP_TX39:
618 c->isa_level = MIPS_CPU_ISA_I;
619 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
620
621 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
622 c->cputype = CPU_TX3927;
623 __cpu_name[cpu] = "TX3927";
624 c->tlbsize = 64;
625 } else {
626 switch (c->processor_id & 0xff) {
627 case PRID_REV_TX3912:
628 c->cputype = CPU_TX3912;
629 __cpu_name[cpu] = "TX3912";
630 c->tlbsize = 32;
631 break;
632 case PRID_REV_TX3922:
633 c->cputype = CPU_TX3922;
634 __cpu_name[cpu] = "TX3922";
635 c->tlbsize = 64;
636 break;
637 }
638 }
639 break;
640 case PRID_IMP_R4700:
641 c->cputype = CPU_R4700;
642 __cpu_name[cpu] = "R4700";
643 c->isa_level = MIPS_CPU_ISA_III;
644 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
645 MIPS_CPU_LLSC;
646 c->tlbsize = 48;
647 break;
648 case PRID_IMP_TX49:
649 c->cputype = CPU_TX49XX;
650 __cpu_name[cpu] = "R49XX";
651 c->isa_level = MIPS_CPU_ISA_III;
652 c->options = R4K_OPTS | MIPS_CPU_LLSC;
653 if (!(c->processor_id & 0x08))
654 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
655 c->tlbsize = 48;
656 break;
657 case PRID_IMP_R5000:
658 c->cputype = CPU_R5000;
659 __cpu_name[cpu] = "R5000";
660 c->isa_level = MIPS_CPU_ISA_IV;
661 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
662 MIPS_CPU_LLSC;
663 c->tlbsize = 48;
664 break;
665 case PRID_IMP_R5432:
666 c->cputype = CPU_R5432;
667 __cpu_name[cpu] = "R5432";
668 c->isa_level = MIPS_CPU_ISA_IV;
669 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
670 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
671 c->tlbsize = 48;
672 break;
673 case PRID_IMP_R5500:
674 c->cputype = CPU_R5500;
675 __cpu_name[cpu] = "R5500";
676 c->isa_level = MIPS_CPU_ISA_IV;
677 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
678 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
679 c->tlbsize = 48;
680 break;
681 case PRID_IMP_NEVADA:
682 c->cputype = CPU_NEVADA;
683 __cpu_name[cpu] = "Nevada";
684 c->isa_level = MIPS_CPU_ISA_IV;
685 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
686 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
687 c->tlbsize = 48;
688 break;
689 case PRID_IMP_R6000:
690 c->cputype = CPU_R6000;
691 __cpu_name[cpu] = "R6000";
692 c->isa_level = MIPS_CPU_ISA_II;
693 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
694 MIPS_CPU_LLSC;
695 c->tlbsize = 32;
696 break;
697 case PRID_IMP_R6000A:
698 c->cputype = CPU_R6000A;
699 __cpu_name[cpu] = "R6000A";
700 c->isa_level = MIPS_CPU_ISA_II;
701 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
702 MIPS_CPU_LLSC;
703 c->tlbsize = 32;
704 break;
705 case PRID_IMP_RM7000:
706 c->cputype = CPU_RM7000;
707 __cpu_name[cpu] = "RM7000";
708 c->isa_level = MIPS_CPU_ISA_IV;
709 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
710 MIPS_CPU_LLSC;
711 /*
712 * Undocumented RM7000: Bit 29 in the info register of
713 * the RM7000 v2.0 indicates if the TLB has 48 or 64
714 * entries.
715 *
716 * 29 1 => 64 entry JTLB
717 * 0 => 48 entry JTLB
718 */
719 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
720 break;
721 case PRID_IMP_RM9000:
722 c->cputype = CPU_RM9000;
723 __cpu_name[cpu] = "RM9000";
724 c->isa_level = MIPS_CPU_ISA_IV;
725 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
726 MIPS_CPU_LLSC;
727 /*
728 * Bit 29 in the info register of the RM9000
729 * indicates if the TLB has 48 or 64 entries.
730 *
731 * 29 1 => 64 entry JTLB
732 * 0 => 48 entry JTLB
733 */
734 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
735 break;
736 case PRID_IMP_R8000:
737 c->cputype = CPU_R8000;
738 __cpu_name[cpu] = "RM8000";
739 c->isa_level = MIPS_CPU_ISA_IV;
740 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
741 MIPS_CPU_FPU | MIPS_CPU_32FPR |
742 MIPS_CPU_LLSC;
743 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
744 break;
745 case PRID_IMP_R10000:
746 c->cputype = CPU_R10000;
747 __cpu_name[cpu] = "R10000";
748 c->isa_level = MIPS_CPU_ISA_IV;
749 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
750 MIPS_CPU_FPU | MIPS_CPU_32FPR |
751 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
752 MIPS_CPU_LLSC;
753 c->tlbsize = 64;
754 break;
755 case PRID_IMP_R12000:
756 c->cputype = CPU_R12000;
757 __cpu_name[cpu] = "R12000";
758 c->isa_level = MIPS_CPU_ISA_IV;
759 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
760 MIPS_CPU_FPU | MIPS_CPU_32FPR |
761 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
762 MIPS_CPU_LLSC;
763 c->tlbsize = 64;
764 break;
765 case PRID_IMP_R14000:
766 c->cputype = CPU_R14000;
767 __cpu_name[cpu] = "R14000";
768 c->isa_level = MIPS_CPU_ISA_IV;
769 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
770 MIPS_CPU_FPU | MIPS_CPU_32FPR |
771 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
772 MIPS_CPU_LLSC;
773 c->tlbsize = 64;
774 break;
775 case PRID_IMP_LOONGSON2:
776 c->cputype = CPU_LOONGSON2;
777 __cpu_name[cpu] = "ICT Loongson-2";
778
779 switch (c->processor_id & PRID_REV_MASK) {
780 case PRID_REV_LOONGSON2E:
781 set_elf_platform(cpu, "loongson2e");
782 break;
783 case PRID_REV_LOONGSON2F:
784 set_elf_platform(cpu, "loongson2f");
785 break;
786 }
787
788 c->isa_level = MIPS_CPU_ISA_III;
789 c->options = R4K_OPTS |
790 MIPS_CPU_FPU | MIPS_CPU_LLSC |
791 MIPS_CPU_32FPR;
792 c->tlbsize = 64;
793 break;
794 case PRID_IMP_LOONGSON1:
795 decode_configs(c);
796
797 c->cputype = CPU_LOONGSON1;
798
799 switch (c->processor_id & PRID_REV_MASK) {
800 case PRID_REV_LOONGSON1B:
801 __cpu_name[cpu] = "Loongson 1B";
802 break;
803 }
804
805 break;
806 }
807 }
808
809 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
810 {
811 decode_configs(c);
812 switch (c->processor_id & 0xff00) {
813 case PRID_IMP_4KC:
814 c->cputype = CPU_4KC;
815 __cpu_name[cpu] = "MIPS 4Kc";
816 break;
817 case PRID_IMP_4KEC:
818 case PRID_IMP_4KECR2:
819 c->cputype = CPU_4KEC;
820 __cpu_name[cpu] = "MIPS 4KEc";
821 break;
822 case PRID_IMP_4KSC:
823 case PRID_IMP_4KSD:
824 c->cputype = CPU_4KSC;
825 __cpu_name[cpu] = "MIPS 4KSc";
826 break;
827 case PRID_IMP_5KC:
828 c->cputype = CPU_5KC;
829 __cpu_name[cpu] = "MIPS 5Kc";
830 break;
831 case PRID_IMP_5KE:
832 c->cputype = CPU_5KE;
833 __cpu_name[cpu] = "MIPS 5KE";
834 break;
835 case PRID_IMP_20KC:
836 c->cputype = CPU_20KC;
837 __cpu_name[cpu] = "MIPS 20Kc";
838 break;
839 case PRID_IMP_24K:
840 case PRID_IMP_24KE:
841 c->cputype = CPU_24K;
842 __cpu_name[cpu] = "MIPS 24Kc";
843 break;
844 case PRID_IMP_25KF:
845 c->cputype = CPU_25KF;
846 __cpu_name[cpu] = "MIPS 25Kc";
847 break;
848 case PRID_IMP_34K:
849 c->cputype = CPU_34K;
850 __cpu_name[cpu] = "MIPS 34Kc";
851 break;
852 case PRID_IMP_74K:
853 c->cputype = CPU_74K;
854 __cpu_name[cpu] = "MIPS 74Kc";
855 break;
856 case PRID_IMP_M14KC:
857 c->cputype = CPU_M14KC;
858 __cpu_name[cpu] = "MIPS M14Kc";
859 break;
860 case PRID_IMP_1004K:
861 c->cputype = CPU_1004K;
862 __cpu_name[cpu] = "MIPS 1004Kc";
863 break;
864 case PRID_IMP_1074K:
865 c->cputype = CPU_74K;
866 __cpu_name[cpu] = "MIPS 1074Kc";
867 break;
868 }
869
870 spram_config();
871 }
872
873 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
874 {
875 decode_configs(c);
876 switch (c->processor_id & 0xff00) {
877 case PRID_IMP_AU1_REV1:
878 case PRID_IMP_AU1_REV2:
879 c->cputype = CPU_ALCHEMY;
880 switch ((c->processor_id >> 24) & 0xff) {
881 case 0:
882 __cpu_name[cpu] = "Au1000";
883 break;
884 case 1:
885 __cpu_name[cpu] = "Au1500";
886 break;
887 case 2:
888 __cpu_name[cpu] = "Au1100";
889 break;
890 case 3:
891 __cpu_name[cpu] = "Au1550";
892 break;
893 case 4:
894 __cpu_name[cpu] = "Au1200";
895 if ((c->processor_id & 0xff) == 2)
896 __cpu_name[cpu] = "Au1250";
897 break;
898 case 5:
899 __cpu_name[cpu] = "Au1210";
900 break;
901 default:
902 __cpu_name[cpu] = "Au1xxx";
903 break;
904 }
905 break;
906 }
907 }
908
909 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
910 {
911 decode_configs(c);
912
913 switch (c->processor_id & 0xff00) {
914 case PRID_IMP_SB1:
915 c->cputype = CPU_SB1;
916 __cpu_name[cpu] = "SiByte SB1";
917 /* FPU in pass1 is known to have issues. */
918 if ((c->processor_id & 0xff) < 0x02)
919 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
920 break;
921 case PRID_IMP_SB1A:
922 c->cputype = CPU_SB1A;
923 __cpu_name[cpu] = "SiByte SB1A";
924 break;
925 }
926 }
927
928 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
929 {
930 decode_configs(c);
931 switch (c->processor_id & 0xff00) {
932 case PRID_IMP_SR71000:
933 c->cputype = CPU_SR71000;
934 __cpu_name[cpu] = "Sandcraft SR71000";
935 c->scache.ways = 8;
936 c->tlbsize = 64;
937 break;
938 }
939 }
940
941 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
942 {
943 decode_configs(c);
944 switch (c->processor_id & 0xff00) {
945 case PRID_IMP_PR4450:
946 c->cputype = CPU_PR4450;
947 __cpu_name[cpu] = "Philips PR4450";
948 c->isa_level = MIPS_CPU_ISA_M32R1;
949 break;
950 }
951 }
952
953 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
954 {
955 decode_configs(c);
956 switch (c->processor_id & 0xff00) {
957 case PRID_IMP_BMIPS32_REV4:
958 case PRID_IMP_BMIPS32_REV8:
959 c->cputype = CPU_BMIPS32;
960 __cpu_name[cpu] = "Broadcom BMIPS32";
961 set_elf_platform(cpu, "bmips32");
962 break;
963 case PRID_IMP_BMIPS3300:
964 case PRID_IMP_BMIPS3300_ALT:
965 case PRID_IMP_BMIPS3300_BUG:
966 c->cputype = CPU_BMIPS3300;
967 __cpu_name[cpu] = "Broadcom BMIPS3300";
968 set_elf_platform(cpu, "bmips3300");
969 break;
970 case PRID_IMP_BMIPS43XX: {
971 int rev = c->processor_id & 0xff;
972
973 if (rev >= PRID_REV_BMIPS4380_LO &&
974 rev <= PRID_REV_BMIPS4380_HI) {
975 c->cputype = CPU_BMIPS4380;
976 __cpu_name[cpu] = "Broadcom BMIPS4380";
977 set_elf_platform(cpu, "bmips4380");
978 } else {
979 c->cputype = CPU_BMIPS4350;
980 __cpu_name[cpu] = "Broadcom BMIPS4350";
981 set_elf_platform(cpu, "bmips4350");
982 }
983 break;
984 }
985 case PRID_IMP_BMIPS5000:
986 c->cputype = CPU_BMIPS5000;
987 __cpu_name[cpu] = "Broadcom BMIPS5000";
988 set_elf_platform(cpu, "bmips5000");
989 c->options |= MIPS_CPU_ULRI;
990 break;
991 }
992 }
993
994 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
995 {
996 decode_configs(c);
997 switch (c->processor_id & 0xff00) {
998 case PRID_IMP_CAVIUM_CN38XX:
999 case PRID_IMP_CAVIUM_CN31XX:
1000 case PRID_IMP_CAVIUM_CN30XX:
1001 c->cputype = CPU_CAVIUM_OCTEON;
1002 __cpu_name[cpu] = "Cavium Octeon";
1003 goto platform;
1004 case PRID_IMP_CAVIUM_CN58XX:
1005 case PRID_IMP_CAVIUM_CN56XX:
1006 case PRID_IMP_CAVIUM_CN50XX:
1007 case PRID_IMP_CAVIUM_CN52XX:
1008 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1009 __cpu_name[cpu] = "Cavium Octeon+";
1010 platform:
1011 set_elf_platform(cpu, "octeon");
1012 break;
1013 case PRID_IMP_CAVIUM_CN61XX:
1014 case PRID_IMP_CAVIUM_CN63XX:
1015 case PRID_IMP_CAVIUM_CN66XX:
1016 case PRID_IMP_CAVIUM_CN68XX:
1017 c->cputype = CPU_CAVIUM_OCTEON2;
1018 __cpu_name[cpu] = "Cavium Octeon II";
1019 set_elf_platform(cpu, "octeon2");
1020 break;
1021 default:
1022 printk(KERN_INFO "Unknown Octeon chip!\n");
1023 c->cputype = CPU_UNKNOWN;
1024 break;
1025 }
1026 }
1027
1028 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1029 {
1030 decode_configs(c);
1031 /* JZRISC does not implement the CP0 counter. */
1032 c->options &= ~MIPS_CPU_COUNTER;
1033 switch (c->processor_id & 0xff00) {
1034 case PRID_IMP_JZRISC:
1035 c->cputype = CPU_JZRISC;
1036 __cpu_name[cpu] = "Ingenic JZRISC";
1037 break;
1038 default:
1039 panic("Unknown Ingenic Processor ID!");
1040 break;
1041 }
1042 }
1043
1044 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1045 {
1046 decode_configs(c);
1047
1048 if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) {
1049 c->cputype = CPU_ALCHEMY;
1050 __cpu_name[cpu] = "Au1300";
1051 /* following stuff is not for Alchemy */
1052 return;
1053 }
1054
1055 c->options = (MIPS_CPU_TLB |
1056 MIPS_CPU_4KEX |
1057 MIPS_CPU_COUNTER |
1058 MIPS_CPU_DIVEC |
1059 MIPS_CPU_WATCH |
1060 MIPS_CPU_EJTAG |
1061 MIPS_CPU_LLSC);
1062
1063 switch (c->processor_id & 0xff00) {
1064 case PRID_IMP_NETLOGIC_XLP8XX:
1065 case PRID_IMP_NETLOGIC_XLP3XX:
1066 c->cputype = CPU_XLP;
1067 __cpu_name[cpu] = "Netlogic XLP";
1068 break;
1069
1070 case PRID_IMP_NETLOGIC_XLR732:
1071 case PRID_IMP_NETLOGIC_XLR716:
1072 case PRID_IMP_NETLOGIC_XLR532:
1073 case PRID_IMP_NETLOGIC_XLR308:
1074 case PRID_IMP_NETLOGIC_XLR532C:
1075 case PRID_IMP_NETLOGIC_XLR516C:
1076 case PRID_IMP_NETLOGIC_XLR508C:
1077 case PRID_IMP_NETLOGIC_XLR308C:
1078 c->cputype = CPU_XLR;
1079 __cpu_name[cpu] = "Netlogic XLR";
1080 break;
1081
1082 case PRID_IMP_NETLOGIC_XLS608:
1083 case PRID_IMP_NETLOGIC_XLS408:
1084 case PRID_IMP_NETLOGIC_XLS404:
1085 case PRID_IMP_NETLOGIC_XLS208:
1086 case PRID_IMP_NETLOGIC_XLS204:
1087 case PRID_IMP_NETLOGIC_XLS108:
1088 case PRID_IMP_NETLOGIC_XLS104:
1089 case PRID_IMP_NETLOGIC_XLS616B:
1090 case PRID_IMP_NETLOGIC_XLS608B:
1091 case PRID_IMP_NETLOGIC_XLS416B:
1092 case PRID_IMP_NETLOGIC_XLS412B:
1093 case PRID_IMP_NETLOGIC_XLS408B:
1094 case PRID_IMP_NETLOGIC_XLS404B:
1095 c->cputype = CPU_XLR;
1096 __cpu_name[cpu] = "Netlogic XLS";
1097 break;
1098
1099 default:
1100 pr_info("Unknown Netlogic chip id [%02x]!\n",
1101 c->processor_id);
1102 c->cputype = CPU_XLR;
1103 break;
1104 }
1105
1106 if (c->cputype == CPU_XLP) {
1107 c->isa_level = MIPS_CPU_ISA_M64R2;
1108 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1109 /* This will be updated again after all threads are woken up */
1110 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1111 } else {
1112 c->isa_level = MIPS_CPU_ISA_M64R1;
1113 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1114 }
1115 }
1116
1117 #ifdef CONFIG_64BIT
1118 /* For use by uaccess.h */
1119 u64 __ua_limit;
1120 EXPORT_SYMBOL(__ua_limit);
1121 #endif
1122
1123 const char *__cpu_name[NR_CPUS];
1124 const char *__elf_platform;
1125
1126 __cpuinit void cpu_probe(void)
1127 {
1128 struct cpuinfo_mips *c = &current_cpu_data;
1129 unsigned int cpu = smp_processor_id();
1130
1131 c->processor_id = PRID_IMP_UNKNOWN;
1132 c->fpu_id = FPIR_IMP_NONE;
1133 c->cputype = CPU_UNKNOWN;
1134
1135 c->processor_id = read_c0_prid();
1136 switch (c->processor_id & 0xff0000) {
1137 case PRID_COMP_LEGACY:
1138 cpu_probe_legacy(c, cpu);
1139 break;
1140 case PRID_COMP_MIPS:
1141 cpu_probe_mips(c, cpu);
1142 break;
1143 case PRID_COMP_ALCHEMY:
1144 cpu_probe_alchemy(c, cpu);
1145 break;
1146 case PRID_COMP_SIBYTE:
1147 cpu_probe_sibyte(c, cpu);
1148 break;
1149 case PRID_COMP_BROADCOM:
1150 cpu_probe_broadcom(c, cpu);
1151 break;
1152 case PRID_COMP_SANDCRAFT:
1153 cpu_probe_sandcraft(c, cpu);
1154 break;
1155 case PRID_COMP_NXP:
1156 cpu_probe_nxp(c, cpu);
1157 break;
1158 case PRID_COMP_CAVIUM:
1159 cpu_probe_cavium(c, cpu);
1160 break;
1161 case PRID_COMP_INGENIC:
1162 cpu_probe_ingenic(c, cpu);
1163 break;
1164 case PRID_COMP_NETLOGIC:
1165 cpu_probe_netlogic(c, cpu);
1166 break;
1167 }
1168
1169 BUG_ON(!__cpu_name[cpu]);
1170 BUG_ON(c->cputype == CPU_UNKNOWN);
1171
1172 /*
1173 * Platform code can force the cpu type to optimize code
1174 * generation. In that case be sure the cpu type is correctly
1175 * manually setup otherwise it could trigger some nasty bugs.
1176 */
1177 BUG_ON(current_cpu_type() != c->cputype);
1178
1179 if (mips_fpu_disabled)
1180 c->options &= ~MIPS_CPU_FPU;
1181
1182 if (mips_dsp_disabled)
1183 c->ases &= ~MIPS_ASE_DSP;
1184
1185 if (c->options & MIPS_CPU_FPU) {
1186 c->fpu_id = cpu_get_fpu_id();
1187
1188 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1189 c->isa_level == MIPS_CPU_ISA_M32R2 ||
1190 c->isa_level == MIPS_CPU_ISA_M64R1 ||
1191 c->isa_level == MIPS_CPU_ISA_M64R2) {
1192 if (c->fpu_id & MIPS_FPIR_3D)
1193 c->ases |= MIPS_ASE_MIPS3D;
1194 }
1195 }
1196
1197 if (cpu_has_mips_r2)
1198 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1199 else
1200 c->srsets = 1;
1201
1202 cpu_probe_vmbits(c);
1203
1204 #ifdef CONFIG_64BIT
1205 if (cpu == 0)
1206 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1207 #endif
1208 }
1209
1210 __cpuinit void cpu_report(void)
1211 {
1212 struct cpuinfo_mips *c = &current_cpu_data;
1213
1214 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1215 c->processor_id, cpu_name_string());
1216 if (c->options & MIPS_CPU_FPU)
1217 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1218 }
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