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Merge branch 'modsplit-Oct31_2011' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-hirsute-kernel.git] / arch / mips / kernel / cpu-probe.c
1 /*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004 MIPS Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
20
21 #include <asm/bugs.h>
22 #include <asm/cpu.h>
23 #include <asm/fpu.h>
24 #include <asm/mipsregs.h>
25 #include <asm/system.h>
26 #include <asm/watch.h>
27 #include <asm/elf.h>
28 #include <asm/spram.h>
29 #include <asm/uaccess.h>
30
31 /*
32 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
33 * the implementation of the "wait" feature differs between CPU families. This
34 * points to the function that implements CPU specific wait.
35 * The wait instruction stops the pipeline and reduces the power consumption of
36 * the CPU very much.
37 */
38 void (*cpu_wait)(void);
39 EXPORT_SYMBOL(cpu_wait);
40
41 static void r3081_wait(void)
42 {
43 unsigned long cfg = read_c0_conf();
44 write_c0_conf(cfg | R30XX_CONF_HALT);
45 }
46
47 static void r39xx_wait(void)
48 {
49 local_irq_disable();
50 if (!need_resched())
51 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
52 local_irq_enable();
53 }
54
55 extern void r4k_wait(void);
56
57 /*
58 * This variant is preferable as it allows testing need_resched and going to
59 * sleep depending on the outcome atomically. Unfortunately the "It is
60 * implementation-dependent whether the pipeline restarts when a non-enabled
61 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
62 * using this version a gamble.
63 */
64 void r4k_wait_irqoff(void)
65 {
66 local_irq_disable();
67 if (!need_resched())
68 __asm__(" .set push \n"
69 " .set mips3 \n"
70 " wait \n"
71 " .set pop \n");
72 local_irq_enable();
73 __asm__(" .globl __pastwait \n"
74 "__pastwait: \n");
75 }
76
77 /*
78 * The RM7000 variant has to handle erratum 38. The workaround is to not
79 * have any pending stores when the WAIT instruction is executed.
80 */
81 static void rm7k_wait_irqoff(void)
82 {
83 local_irq_disable();
84 if (!need_resched())
85 __asm__(
86 " .set push \n"
87 " .set mips3 \n"
88 " .set noat \n"
89 " mfc0 $1, $12 \n"
90 " sync \n"
91 " mtc0 $1, $12 # stalls until W stage \n"
92 " wait \n"
93 " mtc0 $1, $12 # stalls until W stage \n"
94 " .set pop \n");
95 local_irq_enable();
96 }
97
98 /*
99 * The Au1xxx wait is available only if using 32khz counter or
100 * external timer source, but specifically not CP0 Counter.
101 * alchemy/common/time.c may override cpu_wait!
102 */
103 static void au1k_wait(void)
104 {
105 __asm__(" .set mips3 \n"
106 " cache 0x14, 0(%0) \n"
107 " cache 0x14, 32(%0) \n"
108 " sync \n"
109 " nop \n"
110 " wait \n"
111 " nop \n"
112 " nop \n"
113 " nop \n"
114 " nop \n"
115 " .set mips0 \n"
116 : : "r" (au1k_wait));
117 }
118
119 static int __initdata nowait;
120
121 static int __init wait_disable(char *s)
122 {
123 nowait = 1;
124
125 return 1;
126 }
127
128 __setup("nowait", wait_disable);
129
130 static int __cpuinitdata mips_fpu_disabled;
131
132 static int __init fpu_disable(char *s)
133 {
134 cpu_data[0].options &= ~MIPS_CPU_FPU;
135 mips_fpu_disabled = 1;
136
137 return 1;
138 }
139
140 __setup("nofpu", fpu_disable);
141
142 int __cpuinitdata mips_dsp_disabled;
143
144 static int __init dsp_disable(char *s)
145 {
146 cpu_data[0].ases &= ~MIPS_ASE_DSP;
147 mips_dsp_disabled = 1;
148
149 return 1;
150 }
151
152 __setup("nodsp", dsp_disable);
153
154 void __init check_wait(void)
155 {
156 struct cpuinfo_mips *c = &current_cpu_data;
157
158 if (nowait) {
159 printk("Wait instruction disabled.\n");
160 return;
161 }
162
163 switch (c->cputype) {
164 case CPU_R3081:
165 case CPU_R3081E:
166 cpu_wait = r3081_wait;
167 break;
168 case CPU_TX3927:
169 cpu_wait = r39xx_wait;
170 break;
171 case CPU_R4200:
172 /* case CPU_R4300: */
173 case CPU_R4600:
174 case CPU_R4640:
175 case CPU_R4650:
176 case CPU_R4700:
177 case CPU_R5000:
178 case CPU_R5500:
179 case CPU_NEVADA:
180 case CPU_4KC:
181 case CPU_4KEC:
182 case CPU_4KSC:
183 case CPU_5KC:
184 case CPU_25KF:
185 case CPU_PR4450:
186 case CPU_BMIPS3300:
187 case CPU_BMIPS4350:
188 case CPU_BMIPS4380:
189 case CPU_BMIPS5000:
190 case CPU_CAVIUM_OCTEON:
191 case CPU_CAVIUM_OCTEON_PLUS:
192 case CPU_CAVIUM_OCTEON2:
193 case CPU_JZRISC:
194 cpu_wait = r4k_wait;
195 break;
196
197 case CPU_RM7000:
198 cpu_wait = rm7k_wait_irqoff;
199 break;
200
201 case CPU_24K:
202 case CPU_34K:
203 case CPU_1004K:
204 cpu_wait = r4k_wait;
205 if (read_c0_config7() & MIPS_CONF7_WII)
206 cpu_wait = r4k_wait_irqoff;
207 break;
208
209 case CPU_74K:
210 cpu_wait = r4k_wait;
211 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
212 cpu_wait = r4k_wait_irqoff;
213 break;
214
215 case CPU_TX49XX:
216 cpu_wait = r4k_wait_irqoff;
217 break;
218 case CPU_ALCHEMY:
219 cpu_wait = au1k_wait;
220 break;
221 case CPU_20KC:
222 /*
223 * WAIT on Rev1.0 has E1, E2, E3 and E16.
224 * WAIT on Rev2.0 and Rev3.0 has E16.
225 * Rev3.1 WAIT is nop, why bother
226 */
227 if ((c->processor_id & 0xff) <= 0x64)
228 break;
229
230 /*
231 * Another rev is incremeting c0_count at a reduced clock
232 * rate while in WAIT mode. So we basically have the choice
233 * between using the cp0 timer as clocksource or avoiding
234 * the WAIT instruction. Until more details are known,
235 * disable the use of WAIT for 20Kc entirely.
236 cpu_wait = r4k_wait;
237 */
238 break;
239 case CPU_RM9000:
240 if ((c->processor_id & 0x00ff) >= 0x40)
241 cpu_wait = r4k_wait;
242 break;
243 default:
244 break;
245 }
246 }
247
248 static inline void check_errata(void)
249 {
250 struct cpuinfo_mips *c = &current_cpu_data;
251
252 switch (c->cputype) {
253 case CPU_34K:
254 /*
255 * Erratum "RPS May Cause Incorrect Instruction Execution"
256 * This code only handles VPE0, any SMP/SMTC/RTOS code
257 * making use of VPE1 will be responsable for that VPE.
258 */
259 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
260 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
261 break;
262 default:
263 break;
264 }
265 }
266
267 void __init check_bugs32(void)
268 {
269 check_errata();
270 }
271
272 /*
273 * Probe whether cpu has config register by trying to play with
274 * alternate cache bit and see whether it matters.
275 * It's used by cpu_probe to distinguish between R3000A and R3081.
276 */
277 static inline int cpu_has_confreg(void)
278 {
279 #ifdef CONFIG_CPU_R3000
280 extern unsigned long r3k_cache_size(unsigned long);
281 unsigned long size1, size2;
282 unsigned long cfg = read_c0_conf();
283
284 size1 = r3k_cache_size(ST0_ISC);
285 write_c0_conf(cfg ^ R30XX_CONF_AC);
286 size2 = r3k_cache_size(ST0_ISC);
287 write_c0_conf(cfg);
288 return size1 != size2;
289 #else
290 return 0;
291 #endif
292 }
293
294 static inline void set_elf_platform(int cpu, const char *plat)
295 {
296 if (cpu == 0)
297 __elf_platform = plat;
298 }
299
300 /*
301 * Get the FPU Implementation/Revision.
302 */
303 static inline unsigned long cpu_get_fpu_id(void)
304 {
305 unsigned long tmp, fpu_id;
306
307 tmp = read_c0_status();
308 __enable_fpu();
309 fpu_id = read_32bit_cp1_register(CP1_REVISION);
310 write_c0_status(tmp);
311 return fpu_id;
312 }
313
314 /*
315 * Check the CPU has an FPU the official way.
316 */
317 static inline int __cpu_has_fpu(void)
318 {
319 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
320 }
321
322 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
323 {
324 #ifdef __NEED_VMBITS_PROBE
325 write_c0_entryhi(0x3fffffffffffe000ULL);
326 back_to_back_c0_hazard();
327 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
328 #endif
329 }
330
331 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
332 | MIPS_CPU_COUNTER)
333
334 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
335 {
336 switch (c->processor_id & 0xff00) {
337 case PRID_IMP_R2000:
338 c->cputype = CPU_R2000;
339 __cpu_name[cpu] = "R2000";
340 c->isa_level = MIPS_CPU_ISA_I;
341 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
342 MIPS_CPU_NOFPUEX;
343 if (__cpu_has_fpu())
344 c->options |= MIPS_CPU_FPU;
345 c->tlbsize = 64;
346 break;
347 case PRID_IMP_R3000:
348 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
349 if (cpu_has_confreg()) {
350 c->cputype = CPU_R3081E;
351 __cpu_name[cpu] = "R3081";
352 } else {
353 c->cputype = CPU_R3000A;
354 __cpu_name[cpu] = "R3000A";
355 }
356 break;
357 } else {
358 c->cputype = CPU_R3000;
359 __cpu_name[cpu] = "R3000";
360 }
361 c->isa_level = MIPS_CPU_ISA_I;
362 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
363 MIPS_CPU_NOFPUEX;
364 if (__cpu_has_fpu())
365 c->options |= MIPS_CPU_FPU;
366 c->tlbsize = 64;
367 break;
368 case PRID_IMP_R4000:
369 if (read_c0_config() & CONF_SC) {
370 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
371 c->cputype = CPU_R4400PC;
372 __cpu_name[cpu] = "R4400PC";
373 } else {
374 c->cputype = CPU_R4000PC;
375 __cpu_name[cpu] = "R4000PC";
376 }
377 } else {
378 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
379 c->cputype = CPU_R4400SC;
380 __cpu_name[cpu] = "R4400SC";
381 } else {
382 c->cputype = CPU_R4000SC;
383 __cpu_name[cpu] = "R4000SC";
384 }
385 }
386
387 c->isa_level = MIPS_CPU_ISA_III;
388 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
389 MIPS_CPU_WATCH | MIPS_CPU_VCE |
390 MIPS_CPU_LLSC;
391 c->tlbsize = 48;
392 break;
393 case PRID_IMP_VR41XX:
394 switch (c->processor_id & 0xf0) {
395 case PRID_REV_VR4111:
396 c->cputype = CPU_VR4111;
397 __cpu_name[cpu] = "NEC VR4111";
398 break;
399 case PRID_REV_VR4121:
400 c->cputype = CPU_VR4121;
401 __cpu_name[cpu] = "NEC VR4121";
402 break;
403 case PRID_REV_VR4122:
404 if ((c->processor_id & 0xf) < 0x3) {
405 c->cputype = CPU_VR4122;
406 __cpu_name[cpu] = "NEC VR4122";
407 } else {
408 c->cputype = CPU_VR4181A;
409 __cpu_name[cpu] = "NEC VR4181A";
410 }
411 break;
412 case PRID_REV_VR4130:
413 if ((c->processor_id & 0xf) < 0x4) {
414 c->cputype = CPU_VR4131;
415 __cpu_name[cpu] = "NEC VR4131";
416 } else {
417 c->cputype = CPU_VR4133;
418 __cpu_name[cpu] = "NEC VR4133";
419 }
420 break;
421 default:
422 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
423 c->cputype = CPU_VR41XX;
424 __cpu_name[cpu] = "NEC Vr41xx";
425 break;
426 }
427 c->isa_level = MIPS_CPU_ISA_III;
428 c->options = R4K_OPTS;
429 c->tlbsize = 32;
430 break;
431 case PRID_IMP_R4300:
432 c->cputype = CPU_R4300;
433 __cpu_name[cpu] = "R4300";
434 c->isa_level = MIPS_CPU_ISA_III;
435 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
436 MIPS_CPU_LLSC;
437 c->tlbsize = 32;
438 break;
439 case PRID_IMP_R4600:
440 c->cputype = CPU_R4600;
441 __cpu_name[cpu] = "R4600";
442 c->isa_level = MIPS_CPU_ISA_III;
443 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
444 MIPS_CPU_LLSC;
445 c->tlbsize = 48;
446 break;
447 #if 0
448 case PRID_IMP_R4650:
449 /*
450 * This processor doesn't have an MMU, so it's not
451 * "real easy" to run Linux on it. It is left purely
452 * for documentation. Commented out because it shares
453 * it's c0_prid id number with the TX3900.
454 */
455 c->cputype = CPU_R4650;
456 __cpu_name[cpu] = "R4650";
457 c->isa_level = MIPS_CPU_ISA_III;
458 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
459 c->tlbsize = 48;
460 break;
461 #endif
462 case PRID_IMP_TX39:
463 c->isa_level = MIPS_CPU_ISA_I;
464 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
465
466 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
467 c->cputype = CPU_TX3927;
468 __cpu_name[cpu] = "TX3927";
469 c->tlbsize = 64;
470 } else {
471 switch (c->processor_id & 0xff) {
472 case PRID_REV_TX3912:
473 c->cputype = CPU_TX3912;
474 __cpu_name[cpu] = "TX3912";
475 c->tlbsize = 32;
476 break;
477 case PRID_REV_TX3922:
478 c->cputype = CPU_TX3922;
479 __cpu_name[cpu] = "TX3922";
480 c->tlbsize = 64;
481 break;
482 }
483 }
484 break;
485 case PRID_IMP_R4700:
486 c->cputype = CPU_R4700;
487 __cpu_name[cpu] = "R4700";
488 c->isa_level = MIPS_CPU_ISA_III;
489 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
490 MIPS_CPU_LLSC;
491 c->tlbsize = 48;
492 break;
493 case PRID_IMP_TX49:
494 c->cputype = CPU_TX49XX;
495 __cpu_name[cpu] = "R49XX";
496 c->isa_level = MIPS_CPU_ISA_III;
497 c->options = R4K_OPTS | MIPS_CPU_LLSC;
498 if (!(c->processor_id & 0x08))
499 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
500 c->tlbsize = 48;
501 break;
502 case PRID_IMP_R5000:
503 c->cputype = CPU_R5000;
504 __cpu_name[cpu] = "R5000";
505 c->isa_level = MIPS_CPU_ISA_IV;
506 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
507 MIPS_CPU_LLSC;
508 c->tlbsize = 48;
509 break;
510 case PRID_IMP_R5432:
511 c->cputype = CPU_R5432;
512 __cpu_name[cpu] = "R5432";
513 c->isa_level = MIPS_CPU_ISA_IV;
514 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
515 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
516 c->tlbsize = 48;
517 break;
518 case PRID_IMP_R5500:
519 c->cputype = CPU_R5500;
520 __cpu_name[cpu] = "R5500";
521 c->isa_level = MIPS_CPU_ISA_IV;
522 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
523 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
524 c->tlbsize = 48;
525 break;
526 case PRID_IMP_NEVADA:
527 c->cputype = CPU_NEVADA;
528 __cpu_name[cpu] = "Nevada";
529 c->isa_level = MIPS_CPU_ISA_IV;
530 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
531 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
532 c->tlbsize = 48;
533 break;
534 case PRID_IMP_R6000:
535 c->cputype = CPU_R6000;
536 __cpu_name[cpu] = "R6000";
537 c->isa_level = MIPS_CPU_ISA_II;
538 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
539 MIPS_CPU_LLSC;
540 c->tlbsize = 32;
541 break;
542 case PRID_IMP_R6000A:
543 c->cputype = CPU_R6000A;
544 __cpu_name[cpu] = "R6000A";
545 c->isa_level = MIPS_CPU_ISA_II;
546 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
547 MIPS_CPU_LLSC;
548 c->tlbsize = 32;
549 break;
550 case PRID_IMP_RM7000:
551 c->cputype = CPU_RM7000;
552 __cpu_name[cpu] = "RM7000";
553 c->isa_level = MIPS_CPU_ISA_IV;
554 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
555 MIPS_CPU_LLSC;
556 /*
557 * Undocumented RM7000: Bit 29 in the info register of
558 * the RM7000 v2.0 indicates if the TLB has 48 or 64
559 * entries.
560 *
561 * 29 1 => 64 entry JTLB
562 * 0 => 48 entry JTLB
563 */
564 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
565 break;
566 case PRID_IMP_RM9000:
567 c->cputype = CPU_RM9000;
568 __cpu_name[cpu] = "RM9000";
569 c->isa_level = MIPS_CPU_ISA_IV;
570 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
571 MIPS_CPU_LLSC;
572 /*
573 * Bit 29 in the info register of the RM9000
574 * indicates if the TLB has 48 or 64 entries.
575 *
576 * 29 1 => 64 entry JTLB
577 * 0 => 48 entry JTLB
578 */
579 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
580 break;
581 case PRID_IMP_R8000:
582 c->cputype = CPU_R8000;
583 __cpu_name[cpu] = "RM8000";
584 c->isa_level = MIPS_CPU_ISA_IV;
585 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
586 MIPS_CPU_FPU | MIPS_CPU_32FPR |
587 MIPS_CPU_LLSC;
588 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
589 break;
590 case PRID_IMP_R10000:
591 c->cputype = CPU_R10000;
592 __cpu_name[cpu] = "R10000";
593 c->isa_level = MIPS_CPU_ISA_IV;
594 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
595 MIPS_CPU_FPU | MIPS_CPU_32FPR |
596 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
597 MIPS_CPU_LLSC;
598 c->tlbsize = 64;
599 break;
600 case PRID_IMP_R12000:
601 c->cputype = CPU_R12000;
602 __cpu_name[cpu] = "R12000";
603 c->isa_level = MIPS_CPU_ISA_IV;
604 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
605 MIPS_CPU_FPU | MIPS_CPU_32FPR |
606 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
607 MIPS_CPU_LLSC;
608 c->tlbsize = 64;
609 break;
610 case PRID_IMP_R14000:
611 c->cputype = CPU_R14000;
612 __cpu_name[cpu] = "R14000";
613 c->isa_level = MIPS_CPU_ISA_IV;
614 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
615 MIPS_CPU_FPU | MIPS_CPU_32FPR |
616 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
617 MIPS_CPU_LLSC;
618 c->tlbsize = 64;
619 break;
620 case PRID_IMP_LOONGSON2:
621 c->cputype = CPU_LOONGSON2;
622 __cpu_name[cpu] = "ICT Loongson-2";
623
624 switch (c->processor_id & PRID_REV_MASK) {
625 case PRID_REV_LOONGSON2E:
626 set_elf_platform(cpu, "loongson2e");
627 break;
628 case PRID_REV_LOONGSON2F:
629 set_elf_platform(cpu, "loongson2f");
630 break;
631 }
632
633 c->isa_level = MIPS_CPU_ISA_III;
634 c->options = R4K_OPTS |
635 MIPS_CPU_FPU | MIPS_CPU_LLSC |
636 MIPS_CPU_32FPR;
637 c->tlbsize = 64;
638 break;
639 }
640 }
641
642 static char unknown_isa[] __cpuinitdata = KERN_ERR \
643 "Unsupported ISA type, c0.config0: %d.";
644
645 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
646 {
647 unsigned int config0;
648 int isa;
649
650 config0 = read_c0_config();
651
652 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
653 c->options |= MIPS_CPU_TLB;
654 isa = (config0 & MIPS_CONF_AT) >> 13;
655 switch (isa) {
656 case 0:
657 switch ((config0 & MIPS_CONF_AR) >> 10) {
658 case 0:
659 c->isa_level = MIPS_CPU_ISA_M32R1;
660 break;
661 case 1:
662 c->isa_level = MIPS_CPU_ISA_M32R2;
663 break;
664 default:
665 goto unknown;
666 }
667 break;
668 case 2:
669 switch ((config0 & MIPS_CONF_AR) >> 10) {
670 case 0:
671 c->isa_level = MIPS_CPU_ISA_M64R1;
672 break;
673 case 1:
674 c->isa_level = MIPS_CPU_ISA_M64R2;
675 break;
676 default:
677 goto unknown;
678 }
679 break;
680 default:
681 goto unknown;
682 }
683
684 return config0 & MIPS_CONF_M;
685
686 unknown:
687 panic(unknown_isa, config0);
688 }
689
690 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
691 {
692 unsigned int config1;
693
694 config1 = read_c0_config1();
695
696 if (config1 & MIPS_CONF1_MD)
697 c->ases |= MIPS_ASE_MDMX;
698 if (config1 & MIPS_CONF1_WR)
699 c->options |= MIPS_CPU_WATCH;
700 if (config1 & MIPS_CONF1_CA)
701 c->ases |= MIPS_ASE_MIPS16;
702 if (config1 & MIPS_CONF1_EP)
703 c->options |= MIPS_CPU_EJTAG;
704 if (config1 & MIPS_CONF1_FP) {
705 c->options |= MIPS_CPU_FPU;
706 c->options |= MIPS_CPU_32FPR;
707 }
708 if (cpu_has_tlb)
709 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
710
711 return config1 & MIPS_CONF_M;
712 }
713
714 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
715 {
716 unsigned int config2;
717
718 config2 = read_c0_config2();
719
720 if (config2 & MIPS_CONF2_SL)
721 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
722
723 return config2 & MIPS_CONF_M;
724 }
725
726 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
727 {
728 unsigned int config3;
729
730 config3 = read_c0_config3();
731
732 if (config3 & MIPS_CONF3_SM)
733 c->ases |= MIPS_ASE_SMARTMIPS;
734 if (config3 & MIPS_CONF3_DSP)
735 c->ases |= MIPS_ASE_DSP;
736 if (config3 & MIPS_CONF3_VINT)
737 c->options |= MIPS_CPU_VINT;
738 if (config3 & MIPS_CONF3_VEIC)
739 c->options |= MIPS_CPU_VEIC;
740 if (config3 & MIPS_CONF3_MT)
741 c->ases |= MIPS_ASE_MIPSMT;
742 if (config3 & MIPS_CONF3_ULRI)
743 c->options |= MIPS_CPU_ULRI;
744
745 return config3 & MIPS_CONF_M;
746 }
747
748 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
749 {
750 unsigned int config4;
751
752 config4 = read_c0_config4();
753
754 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
755 && cpu_has_tlb)
756 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
757
758 c->kscratch_mask = (config4 >> 16) & 0xff;
759
760 return config4 & MIPS_CONF_M;
761 }
762
763 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
764 {
765 int ok;
766
767 /* MIPS32 or MIPS64 compliant CPU. */
768 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
769 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
770
771 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
772
773 ok = decode_config0(c); /* Read Config registers. */
774 BUG_ON(!ok); /* Arch spec violation! */
775 if (ok)
776 ok = decode_config1(c);
777 if (ok)
778 ok = decode_config2(c);
779 if (ok)
780 ok = decode_config3(c);
781 if (ok)
782 ok = decode_config4(c);
783
784 mips_probe_watch_registers(c);
785
786 if (cpu_has_mips_r2)
787 c->core = read_c0_ebase() & 0x3ff;
788 }
789
790 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
791 {
792 decode_configs(c);
793 switch (c->processor_id & 0xff00) {
794 case PRID_IMP_4KC:
795 c->cputype = CPU_4KC;
796 __cpu_name[cpu] = "MIPS 4Kc";
797 break;
798 case PRID_IMP_4KEC:
799 case PRID_IMP_4KECR2:
800 c->cputype = CPU_4KEC;
801 __cpu_name[cpu] = "MIPS 4KEc";
802 break;
803 case PRID_IMP_4KSC:
804 case PRID_IMP_4KSD:
805 c->cputype = CPU_4KSC;
806 __cpu_name[cpu] = "MIPS 4KSc";
807 break;
808 case PRID_IMP_5KC:
809 c->cputype = CPU_5KC;
810 __cpu_name[cpu] = "MIPS 5Kc";
811 break;
812 case PRID_IMP_20KC:
813 c->cputype = CPU_20KC;
814 __cpu_name[cpu] = "MIPS 20Kc";
815 break;
816 case PRID_IMP_24K:
817 case PRID_IMP_24KE:
818 c->cputype = CPU_24K;
819 __cpu_name[cpu] = "MIPS 24Kc";
820 break;
821 case PRID_IMP_25KF:
822 c->cputype = CPU_25KF;
823 __cpu_name[cpu] = "MIPS 25Kc";
824 break;
825 case PRID_IMP_34K:
826 c->cputype = CPU_34K;
827 __cpu_name[cpu] = "MIPS 34Kc";
828 break;
829 case PRID_IMP_74K:
830 c->cputype = CPU_74K;
831 __cpu_name[cpu] = "MIPS 74Kc";
832 break;
833 case PRID_IMP_1004K:
834 c->cputype = CPU_1004K;
835 __cpu_name[cpu] = "MIPS 1004Kc";
836 break;
837 }
838
839 spram_config();
840 }
841
842 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
843 {
844 decode_configs(c);
845 switch (c->processor_id & 0xff00) {
846 case PRID_IMP_AU1_REV1:
847 case PRID_IMP_AU1_REV2:
848 c->cputype = CPU_ALCHEMY;
849 switch ((c->processor_id >> 24) & 0xff) {
850 case 0:
851 __cpu_name[cpu] = "Au1000";
852 break;
853 case 1:
854 __cpu_name[cpu] = "Au1500";
855 break;
856 case 2:
857 __cpu_name[cpu] = "Au1100";
858 break;
859 case 3:
860 __cpu_name[cpu] = "Au1550";
861 break;
862 case 4:
863 __cpu_name[cpu] = "Au1200";
864 if ((c->processor_id & 0xff) == 2)
865 __cpu_name[cpu] = "Au1250";
866 break;
867 case 5:
868 __cpu_name[cpu] = "Au1210";
869 break;
870 default:
871 __cpu_name[cpu] = "Au1xxx";
872 break;
873 }
874 break;
875 }
876 }
877
878 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
879 {
880 decode_configs(c);
881
882 switch (c->processor_id & 0xff00) {
883 case PRID_IMP_SB1:
884 c->cputype = CPU_SB1;
885 __cpu_name[cpu] = "SiByte SB1";
886 /* FPU in pass1 is known to have issues. */
887 if ((c->processor_id & 0xff) < 0x02)
888 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
889 break;
890 case PRID_IMP_SB1A:
891 c->cputype = CPU_SB1A;
892 __cpu_name[cpu] = "SiByte SB1A";
893 break;
894 }
895 }
896
897 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
898 {
899 decode_configs(c);
900 switch (c->processor_id & 0xff00) {
901 case PRID_IMP_SR71000:
902 c->cputype = CPU_SR71000;
903 __cpu_name[cpu] = "Sandcraft SR71000";
904 c->scache.ways = 8;
905 c->tlbsize = 64;
906 break;
907 }
908 }
909
910 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
911 {
912 decode_configs(c);
913 switch (c->processor_id & 0xff00) {
914 case PRID_IMP_PR4450:
915 c->cputype = CPU_PR4450;
916 __cpu_name[cpu] = "Philips PR4450";
917 c->isa_level = MIPS_CPU_ISA_M32R1;
918 break;
919 }
920 }
921
922 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
923 {
924 decode_configs(c);
925 switch (c->processor_id & 0xff00) {
926 case PRID_IMP_BMIPS32_REV4:
927 case PRID_IMP_BMIPS32_REV8:
928 c->cputype = CPU_BMIPS32;
929 __cpu_name[cpu] = "Broadcom BMIPS32";
930 set_elf_platform(cpu, "bmips32");
931 break;
932 case PRID_IMP_BMIPS3300:
933 case PRID_IMP_BMIPS3300_ALT:
934 case PRID_IMP_BMIPS3300_BUG:
935 c->cputype = CPU_BMIPS3300;
936 __cpu_name[cpu] = "Broadcom BMIPS3300";
937 set_elf_platform(cpu, "bmips3300");
938 break;
939 case PRID_IMP_BMIPS43XX: {
940 int rev = c->processor_id & 0xff;
941
942 if (rev >= PRID_REV_BMIPS4380_LO &&
943 rev <= PRID_REV_BMIPS4380_HI) {
944 c->cputype = CPU_BMIPS4380;
945 __cpu_name[cpu] = "Broadcom BMIPS4380";
946 set_elf_platform(cpu, "bmips4380");
947 } else {
948 c->cputype = CPU_BMIPS4350;
949 __cpu_name[cpu] = "Broadcom BMIPS4350";
950 set_elf_platform(cpu, "bmips4350");
951 }
952 break;
953 }
954 case PRID_IMP_BMIPS5000:
955 c->cputype = CPU_BMIPS5000;
956 __cpu_name[cpu] = "Broadcom BMIPS5000";
957 set_elf_platform(cpu, "bmips5000");
958 c->options |= MIPS_CPU_ULRI;
959 break;
960 }
961 }
962
963 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
964 {
965 decode_configs(c);
966 switch (c->processor_id & 0xff00) {
967 case PRID_IMP_CAVIUM_CN38XX:
968 case PRID_IMP_CAVIUM_CN31XX:
969 case PRID_IMP_CAVIUM_CN30XX:
970 c->cputype = CPU_CAVIUM_OCTEON;
971 __cpu_name[cpu] = "Cavium Octeon";
972 goto platform;
973 case PRID_IMP_CAVIUM_CN58XX:
974 case PRID_IMP_CAVIUM_CN56XX:
975 case PRID_IMP_CAVIUM_CN50XX:
976 case PRID_IMP_CAVIUM_CN52XX:
977 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
978 __cpu_name[cpu] = "Cavium Octeon+";
979 platform:
980 set_elf_platform(cpu, "octeon");
981 break;
982 case PRID_IMP_CAVIUM_CN61XX:
983 case PRID_IMP_CAVIUM_CN63XX:
984 case PRID_IMP_CAVIUM_CN66XX:
985 case PRID_IMP_CAVIUM_CN68XX:
986 c->cputype = CPU_CAVIUM_OCTEON2;
987 __cpu_name[cpu] = "Cavium Octeon II";
988 set_elf_platform(cpu, "octeon2");
989 break;
990 default:
991 printk(KERN_INFO "Unknown Octeon chip!\n");
992 c->cputype = CPU_UNKNOWN;
993 break;
994 }
995 }
996
997 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
998 {
999 decode_configs(c);
1000 /* JZRISC does not implement the CP0 counter. */
1001 c->options &= ~MIPS_CPU_COUNTER;
1002 switch (c->processor_id & 0xff00) {
1003 case PRID_IMP_JZRISC:
1004 c->cputype = CPU_JZRISC;
1005 __cpu_name[cpu] = "Ingenic JZRISC";
1006 break;
1007 default:
1008 panic("Unknown Ingenic Processor ID!");
1009 break;
1010 }
1011 }
1012
1013 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1014 {
1015 decode_configs(c);
1016
1017 c->options = (MIPS_CPU_TLB |
1018 MIPS_CPU_4KEX |
1019 MIPS_CPU_COUNTER |
1020 MIPS_CPU_DIVEC |
1021 MIPS_CPU_WATCH |
1022 MIPS_CPU_EJTAG |
1023 MIPS_CPU_LLSC);
1024
1025 switch (c->processor_id & 0xff00) {
1026 case PRID_IMP_NETLOGIC_XLR732:
1027 case PRID_IMP_NETLOGIC_XLR716:
1028 case PRID_IMP_NETLOGIC_XLR532:
1029 case PRID_IMP_NETLOGIC_XLR308:
1030 case PRID_IMP_NETLOGIC_XLR532C:
1031 case PRID_IMP_NETLOGIC_XLR516C:
1032 case PRID_IMP_NETLOGIC_XLR508C:
1033 case PRID_IMP_NETLOGIC_XLR308C:
1034 c->cputype = CPU_XLR;
1035 __cpu_name[cpu] = "Netlogic XLR";
1036 break;
1037
1038 case PRID_IMP_NETLOGIC_XLS608:
1039 case PRID_IMP_NETLOGIC_XLS408:
1040 case PRID_IMP_NETLOGIC_XLS404:
1041 case PRID_IMP_NETLOGIC_XLS208:
1042 case PRID_IMP_NETLOGIC_XLS204:
1043 case PRID_IMP_NETLOGIC_XLS108:
1044 case PRID_IMP_NETLOGIC_XLS104:
1045 case PRID_IMP_NETLOGIC_XLS616B:
1046 case PRID_IMP_NETLOGIC_XLS608B:
1047 case PRID_IMP_NETLOGIC_XLS416B:
1048 case PRID_IMP_NETLOGIC_XLS412B:
1049 case PRID_IMP_NETLOGIC_XLS408B:
1050 case PRID_IMP_NETLOGIC_XLS404B:
1051 c->cputype = CPU_XLR;
1052 __cpu_name[cpu] = "Netlogic XLS";
1053 break;
1054
1055 default:
1056 printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n",
1057 c->processor_id);
1058 c->cputype = CPU_XLR;
1059 break;
1060 }
1061
1062 c->isa_level = MIPS_CPU_ISA_M64R1;
1063 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1064 }
1065
1066 #ifdef CONFIG_64BIT
1067 /* For use by uaccess.h */
1068 u64 __ua_limit;
1069 EXPORT_SYMBOL(__ua_limit);
1070 #endif
1071
1072 const char *__cpu_name[NR_CPUS];
1073 const char *__elf_platform;
1074
1075 __cpuinit void cpu_probe(void)
1076 {
1077 struct cpuinfo_mips *c = &current_cpu_data;
1078 unsigned int cpu = smp_processor_id();
1079
1080 c->processor_id = PRID_IMP_UNKNOWN;
1081 c->fpu_id = FPIR_IMP_NONE;
1082 c->cputype = CPU_UNKNOWN;
1083
1084 c->processor_id = read_c0_prid();
1085 switch (c->processor_id & 0xff0000) {
1086 case PRID_COMP_LEGACY:
1087 cpu_probe_legacy(c, cpu);
1088 break;
1089 case PRID_COMP_MIPS:
1090 cpu_probe_mips(c, cpu);
1091 break;
1092 case PRID_COMP_ALCHEMY:
1093 cpu_probe_alchemy(c, cpu);
1094 break;
1095 case PRID_COMP_SIBYTE:
1096 cpu_probe_sibyte(c, cpu);
1097 break;
1098 case PRID_COMP_BROADCOM:
1099 cpu_probe_broadcom(c, cpu);
1100 break;
1101 case PRID_COMP_SANDCRAFT:
1102 cpu_probe_sandcraft(c, cpu);
1103 break;
1104 case PRID_COMP_NXP:
1105 cpu_probe_nxp(c, cpu);
1106 break;
1107 case PRID_COMP_CAVIUM:
1108 cpu_probe_cavium(c, cpu);
1109 break;
1110 case PRID_COMP_INGENIC:
1111 cpu_probe_ingenic(c, cpu);
1112 break;
1113 case PRID_COMP_NETLOGIC:
1114 cpu_probe_netlogic(c, cpu);
1115 break;
1116 }
1117
1118 BUG_ON(!__cpu_name[cpu]);
1119 BUG_ON(c->cputype == CPU_UNKNOWN);
1120
1121 /*
1122 * Platform code can force the cpu type to optimize code
1123 * generation. In that case be sure the cpu type is correctly
1124 * manually setup otherwise it could trigger some nasty bugs.
1125 */
1126 BUG_ON(current_cpu_type() != c->cputype);
1127
1128 if (mips_fpu_disabled)
1129 c->options &= ~MIPS_CPU_FPU;
1130
1131 if (mips_dsp_disabled)
1132 c->ases &= ~MIPS_ASE_DSP;
1133
1134 if (c->options & MIPS_CPU_FPU) {
1135 c->fpu_id = cpu_get_fpu_id();
1136
1137 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1138 c->isa_level == MIPS_CPU_ISA_M32R2 ||
1139 c->isa_level == MIPS_CPU_ISA_M64R1 ||
1140 c->isa_level == MIPS_CPU_ISA_M64R2) {
1141 if (c->fpu_id & MIPS_FPIR_3D)
1142 c->ases |= MIPS_ASE_MIPS3D;
1143 }
1144 }
1145
1146 if (cpu_has_mips_r2)
1147 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1148 else
1149 c->srsets = 1;
1150
1151 cpu_probe_vmbits(c);
1152
1153 #ifdef CONFIG_64BIT
1154 if (cpu == 0)
1155 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1156 #endif
1157 }
1158
1159 __cpuinit void cpu_report(void)
1160 {
1161 struct cpuinfo_mips *c = &current_cpu_data;
1162
1163 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1164 c->processor_id, cpu_name_string());
1165 if (c->options & MIPS_CPU_FPU)
1166 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1167 }
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