]>
git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blob - arch/mips/kernel/cpu-probe.c
2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004 MIPS Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/stddef.h>
22 #include <asm/mipsregs.h>
23 #include <asm/system.h>
26 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
27 * the implementation of the "wait" feature differs between CPU families. This
28 * points to the function that implements CPU specific wait.
29 * The wait instruction stops the pipeline and reduces the power consumption of
32 void (*cpu_wait
)(void) = NULL
;
34 static void r3081_wait(void)
36 unsigned long cfg
= read_c0_conf();
37 write_c0_conf(cfg
| R30XX_CONF_HALT
);
40 static void r39xx_wait(void)
44 write_c0_conf(read_c0_conf() | TX39_CONF_HALT
);
49 * There is a race when WAIT instruction executed with interrupt
51 * But it is implementation-dependent wheter the pipelie restarts when
52 * a non-enabled interrupt is requested.
54 static void r4k_wait(void)
56 __asm__(" .set mips3 \n"
62 * This variant is preferable as it allows testing need_resched and going to
63 * sleep depending on the outcome atomically. Unfortunately the "It is
64 * implementation-dependent whether the pipeline restarts when a non-enabled
65 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
66 * using this version a gamble.
68 static void r4k_wait_irqoff(void)
72 __asm__(" .set mips3 \n"
79 * The RM7000 variant has to handle erratum 38. The workaround is to not
80 * have any pending stores when the WAIT instruction is executed.
82 static void rm7k_wait_irqoff(void)
92 " mtc0 $1, $12 # stalls until W stage \n"
94 " mtc0 $1, $12 # stalls until W stage \n"
99 /* The Au1xxx wait is available only if using 32khz counter or
100 * external timer source, but specifically not CP0 Counter. */
103 static void au1k_wait(void)
105 /* using the wait instruction makes CP0 counter unusable */
106 __asm__(" .set mips3 \n"
107 " cache 0x14, 0(%0) \n"
108 " cache 0x14, 32(%0) \n"
117 : : "r" (au1k_wait
));
120 static int __initdata nowait
= 0;
122 static int __init
wait_disable(char *s
)
129 __setup("nowait", wait_disable
);
131 static inline void check_wait(void)
133 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
136 printk("Wait instruction disabled.\n");
140 switch (c
->cputype
) {
143 cpu_wait
= r3081_wait
;
146 cpu_wait
= r39xx_wait
;
149 /* case CPU_R4300: */
166 cpu_wait
= rm7k_wait_irqoff
;
172 if (read_c0_config7() & MIPS_CONF7_WII
)
173 cpu_wait
= r4k_wait_irqoff
;
178 if ((c
->processor_id
& 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
179 cpu_wait
= r4k_wait_irqoff
;
183 cpu_wait
= r4k_wait_irqoff
;
191 cpu_wait
= au1k_wait
;
195 * WAIT on Rev1.0 has E1, E2, E3 and E16.
196 * WAIT on Rev2.0 and Rev3.0 has E16.
197 * Rev3.1 WAIT is nop, why bother
199 if ((c
->processor_id
& 0xff) <= 0x64)
205 if ((c
->processor_id
& 0x00ff) >= 0x40)
213 static inline void check_errata(void)
215 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
217 switch (c
->cputype
) {
220 * Erratum "RPS May Cause Incorrect Instruction Execution"
221 * This code only handles VPE0, any SMP/SMTC/RTOS code
222 * making use of VPE1 will be responsable for that VPE.
224 if ((c
->processor_id
& PRID_REV_MASK
) <= PRID_REV_34K_V1_0_2
)
225 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS
);
232 void __init
check_bugs32(void)
239 * Probe whether cpu has config register by trying to play with
240 * alternate cache bit and see whether it matters.
241 * It's used by cpu_probe to distinguish between R3000A and R3081.
243 static inline int cpu_has_confreg(void)
245 #ifdef CONFIG_CPU_R3000
246 extern unsigned long r3k_cache_size(unsigned long);
247 unsigned long size1
, size2
;
248 unsigned long cfg
= read_c0_conf();
250 size1
= r3k_cache_size(ST0_ISC
);
251 write_c0_conf(cfg
^ R30XX_CONF_AC
);
252 size2
= r3k_cache_size(ST0_ISC
);
254 return size1
!= size2
;
261 * Get the FPU Implementation/Revision.
263 static inline unsigned long cpu_get_fpu_id(void)
265 unsigned long tmp
, fpu_id
;
267 tmp
= read_c0_status();
269 fpu_id
= read_32bit_cp1_register(CP1_REVISION
);
270 write_c0_status(tmp
);
275 * Check the CPU has an FPU the official way.
277 static inline int __cpu_has_fpu(void)
279 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE
);
282 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
285 static inline void cpu_probe_legacy(struct cpuinfo_mips
*c
)
287 switch (c
->processor_id
& 0xff00) {
289 c
->cputype
= CPU_R2000
;
290 c
->isa_level
= MIPS_CPU_ISA_I
;
291 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_3K_CACHE
|
294 c
->options
|= MIPS_CPU_FPU
;
298 if ((c
->processor_id
& 0xff) == PRID_REV_R3000A
)
299 if (cpu_has_confreg())
300 c
->cputype
= CPU_R3081E
;
302 c
->cputype
= CPU_R3000A
;
304 c
->cputype
= CPU_R3000
;
305 c
->isa_level
= MIPS_CPU_ISA_I
;
306 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_3K_CACHE
|
309 c
->options
|= MIPS_CPU_FPU
;
313 if (read_c0_config() & CONF_SC
) {
314 if ((c
->processor_id
& 0xff) >= PRID_REV_R4400
)
315 c
->cputype
= CPU_R4400PC
;
317 c
->cputype
= CPU_R4000PC
;
319 if ((c
->processor_id
& 0xff) >= PRID_REV_R4400
)
320 c
->cputype
= CPU_R4400SC
;
322 c
->cputype
= CPU_R4000SC
;
325 c
->isa_level
= MIPS_CPU_ISA_III
;
326 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
327 MIPS_CPU_WATCH
| MIPS_CPU_VCE
|
331 case PRID_IMP_VR41XX
:
332 switch (c
->processor_id
& 0xf0) {
333 case PRID_REV_VR4111
:
334 c
->cputype
= CPU_VR4111
;
336 case PRID_REV_VR4121
:
337 c
->cputype
= CPU_VR4121
;
339 case PRID_REV_VR4122
:
340 if ((c
->processor_id
& 0xf) < 0x3)
341 c
->cputype
= CPU_VR4122
;
343 c
->cputype
= CPU_VR4181A
;
345 case PRID_REV_VR4130
:
346 if ((c
->processor_id
& 0xf) < 0x4)
347 c
->cputype
= CPU_VR4131
;
349 c
->cputype
= CPU_VR4133
;
352 printk(KERN_INFO
"Unexpected CPU of NEC VR4100 series\n");
353 c
->cputype
= CPU_VR41XX
;
356 c
->isa_level
= MIPS_CPU_ISA_III
;
357 c
->options
= R4K_OPTS
;
361 c
->cputype
= CPU_R4300
;
362 c
->isa_level
= MIPS_CPU_ISA_III
;
363 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
368 c
->cputype
= CPU_R4600
;
369 c
->isa_level
= MIPS_CPU_ISA_III
;
370 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
377 * This processor doesn't have an MMU, so it's not
378 * "real easy" to run Linux on it. It is left purely
379 * for documentation. Commented out because it shares
380 * it's c0_prid id number with the TX3900.
382 c
->cputype
= CPU_R4650
;
383 c
->isa_level
= MIPS_CPU_ISA_III
;
384 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_LLSC
;
389 c
->isa_level
= MIPS_CPU_ISA_I
;
390 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_TX39_CACHE
;
392 if ((c
->processor_id
& 0xf0) == (PRID_REV_TX3927
& 0xf0)) {
393 c
->cputype
= CPU_TX3927
;
396 switch (c
->processor_id
& 0xff) {
397 case PRID_REV_TX3912
:
398 c
->cputype
= CPU_TX3912
;
401 case PRID_REV_TX3922
:
402 c
->cputype
= CPU_TX3922
;
406 c
->cputype
= CPU_UNKNOWN
;
412 c
->cputype
= CPU_R4700
;
413 c
->isa_level
= MIPS_CPU_ISA_III
;
414 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
419 c
->cputype
= CPU_TX49XX
;
420 c
->isa_level
= MIPS_CPU_ISA_III
;
421 c
->options
= R4K_OPTS
| MIPS_CPU_LLSC
;
422 if (!(c
->processor_id
& 0x08))
423 c
->options
|= MIPS_CPU_FPU
| MIPS_CPU_32FPR
;
427 c
->cputype
= CPU_R5000
;
428 c
->isa_level
= MIPS_CPU_ISA_IV
;
429 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
434 c
->cputype
= CPU_R5432
;
435 c
->isa_level
= MIPS_CPU_ISA_IV
;
436 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
437 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
441 c
->cputype
= CPU_R5500
;
442 c
->isa_level
= MIPS_CPU_ISA_IV
;
443 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
444 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
447 case PRID_IMP_NEVADA
:
448 c
->cputype
= CPU_NEVADA
;
449 c
->isa_level
= MIPS_CPU_ISA_IV
;
450 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
451 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
;
455 c
->cputype
= CPU_R6000
;
456 c
->isa_level
= MIPS_CPU_ISA_II
;
457 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
461 case PRID_IMP_R6000A
:
462 c
->cputype
= CPU_R6000A
;
463 c
->isa_level
= MIPS_CPU_ISA_II
;
464 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
468 case PRID_IMP_RM7000
:
469 c
->cputype
= CPU_RM7000
;
470 c
->isa_level
= MIPS_CPU_ISA_IV
;
471 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
474 * Undocumented RM7000: Bit 29 in the info register of
475 * the RM7000 v2.0 indicates if the TLB has 48 or 64
478 * 29 1 => 64 entry JTLB
481 c
->tlbsize
= (read_c0_info() & (1 << 29)) ? 64 : 48;
483 case PRID_IMP_RM9000
:
484 c
->cputype
= CPU_RM9000
;
485 c
->isa_level
= MIPS_CPU_ISA_IV
;
486 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
489 * Bit 29 in the info register of the RM9000
490 * indicates if the TLB has 48 or 64 entries.
492 * 29 1 => 64 entry JTLB
495 c
->tlbsize
= (read_c0_info() & (1 << 29)) ? 64 : 48;
498 c
->cputype
= CPU_R8000
;
499 c
->isa_level
= MIPS_CPU_ISA_IV
;
500 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4KEX
|
501 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
503 c
->tlbsize
= 384; /* has weird TLB: 3-way x 128 */
505 case PRID_IMP_R10000
:
506 c
->cputype
= CPU_R10000
;
507 c
->isa_level
= MIPS_CPU_ISA_IV
;
508 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
509 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
510 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
514 case PRID_IMP_R12000
:
515 c
->cputype
= CPU_R12000
;
516 c
->isa_level
= MIPS_CPU_ISA_IV
;
517 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
518 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
519 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
523 case PRID_IMP_R14000
:
524 c
->cputype
= CPU_R14000
;
525 c
->isa_level
= MIPS_CPU_ISA_IV
;
526 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
527 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
528 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
532 case PRID_IMP_LOONGSON2
:
533 c
->cputype
= CPU_LOONGSON2
;
534 c
->isa_level
= MIPS_CPU_ISA_III
;
535 c
->options
= R4K_OPTS
|
536 MIPS_CPU_FPU
| MIPS_CPU_LLSC
|
543 static char unknown_isa
[] __initdata
= KERN_ERR \
544 "Unsupported ISA type, c0.config0: %d.";
546 static inline unsigned int decode_config0(struct cpuinfo_mips
*c
)
548 unsigned int config0
;
551 config0
= read_c0_config();
553 if (((config0
& MIPS_CONF_MT
) >> 7) == 1)
554 c
->options
|= MIPS_CPU_TLB
;
555 isa
= (config0
& MIPS_CONF_AT
) >> 13;
558 switch ((config0
& MIPS_CONF_AR
) >> 10) {
560 c
->isa_level
= MIPS_CPU_ISA_M32R1
;
563 c
->isa_level
= MIPS_CPU_ISA_M32R2
;
570 switch ((config0
& MIPS_CONF_AR
) >> 10) {
572 c
->isa_level
= MIPS_CPU_ISA_M64R1
;
575 c
->isa_level
= MIPS_CPU_ISA_M64R2
;
585 return config0
& MIPS_CONF_M
;
588 panic(unknown_isa
, config0
);
591 static inline unsigned int decode_config1(struct cpuinfo_mips
*c
)
593 unsigned int config1
;
595 config1
= read_c0_config1();
597 if (config1
& MIPS_CONF1_MD
)
598 c
->ases
|= MIPS_ASE_MDMX
;
599 if (config1
& MIPS_CONF1_WR
)
600 c
->options
|= MIPS_CPU_WATCH
;
601 if (config1
& MIPS_CONF1_CA
)
602 c
->ases
|= MIPS_ASE_MIPS16
;
603 if (config1
& MIPS_CONF1_EP
)
604 c
->options
|= MIPS_CPU_EJTAG
;
605 if (config1
& MIPS_CONF1_FP
) {
606 c
->options
|= MIPS_CPU_FPU
;
607 c
->options
|= MIPS_CPU_32FPR
;
610 c
->tlbsize
= ((config1
& MIPS_CONF1_TLBS
) >> 25) + 1;
612 return config1
& MIPS_CONF_M
;
615 static inline unsigned int decode_config2(struct cpuinfo_mips
*c
)
617 unsigned int config2
;
619 config2
= read_c0_config2();
621 if (config2
& MIPS_CONF2_SL
)
622 c
->scache
.flags
&= ~MIPS_CACHE_NOT_PRESENT
;
624 return config2
& MIPS_CONF_M
;
627 static inline unsigned int decode_config3(struct cpuinfo_mips
*c
)
629 unsigned int config3
;
631 config3
= read_c0_config3();
633 if (config3
& MIPS_CONF3_SM
)
634 c
->ases
|= MIPS_ASE_SMARTMIPS
;
635 if (config3
& MIPS_CONF3_DSP
)
636 c
->ases
|= MIPS_ASE_DSP
;
637 if (config3
& MIPS_CONF3_VINT
)
638 c
->options
|= MIPS_CPU_VINT
;
639 if (config3
& MIPS_CONF3_VEIC
)
640 c
->options
|= MIPS_CPU_VEIC
;
641 if (config3
& MIPS_CONF3_MT
)
642 c
->ases
|= MIPS_ASE_MIPSMT
;
643 if (config3
& MIPS_CONF3_ULRI
)
644 c
->options
|= MIPS_CPU_ULRI
;
646 return config3
& MIPS_CONF_M
;
649 static void __init
decode_configs(struct cpuinfo_mips
*c
)
651 /* MIPS32 or MIPS64 compliant CPU. */
652 c
->options
= MIPS_CPU_4KEX
| MIPS_CPU_4K_CACHE
| MIPS_CPU_COUNTER
|
653 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
| MIPS_CPU_MCHECK
;
655 c
->scache
.flags
= MIPS_CACHE_NOT_PRESENT
;
657 /* Read Config registers. */
658 if (!decode_config0(c
))
659 return; /* actually worth a panic() */
660 if (!decode_config1(c
))
662 if (!decode_config2(c
))
664 if (!decode_config3(c
))
668 static inline void cpu_probe_mips(struct cpuinfo_mips
*c
)
671 switch (c
->processor_id
& 0xff00) {
673 c
->cputype
= CPU_4KC
;
676 c
->cputype
= CPU_4KEC
;
678 case PRID_IMP_4KECR2
:
679 c
->cputype
= CPU_4KEC
;
683 c
->cputype
= CPU_4KSC
;
686 c
->cputype
= CPU_5KC
;
689 c
->cputype
= CPU_20KC
;
693 c
->cputype
= CPU_24K
;
696 c
->cputype
= CPU_25KF
;
699 c
->cputype
= CPU_34K
;
702 c
->cputype
= CPU_74K
;
707 static inline void cpu_probe_alchemy(struct cpuinfo_mips
*c
)
710 switch (c
->processor_id
& 0xff00) {
711 case PRID_IMP_AU1_REV1
:
712 case PRID_IMP_AU1_REV2
:
713 switch ((c
->processor_id
>> 24) & 0xff) {
715 c
->cputype
= CPU_AU1000
;
718 c
->cputype
= CPU_AU1500
;
721 c
->cputype
= CPU_AU1100
;
724 c
->cputype
= CPU_AU1550
;
727 c
->cputype
= CPU_AU1200
;
730 panic("Unknown Au Core!");
737 static inline void cpu_probe_sibyte(struct cpuinfo_mips
*c
)
742 * For historical reasons the SB1 comes with it's own variant of
743 * cache code which eventually will be folded into c-r4k.c. Until
744 * then we pretend it's got it's own cache architecture.
746 c
->options
&= ~MIPS_CPU_4K_CACHE
;
747 c
->options
|= MIPS_CPU_SB1_CACHE
;
749 switch (c
->processor_id
& 0xff00) {
751 c
->cputype
= CPU_SB1
;
752 /* FPU in pass1 is known to have issues. */
753 if ((c
->processor_id
& 0xff) < 0x02)
754 c
->options
&= ~(MIPS_CPU_FPU
| MIPS_CPU_32FPR
);
757 c
->cputype
= CPU_SB1A
;
762 static inline void cpu_probe_sandcraft(struct cpuinfo_mips
*c
)
765 switch (c
->processor_id
& 0xff00) {
766 case PRID_IMP_SR71000
:
767 c
->cputype
= CPU_SR71000
;
774 static inline void cpu_probe_philips(struct cpuinfo_mips
*c
)
777 switch (c
->processor_id
& 0xff00) {
778 case PRID_IMP_PR4450
:
779 c
->cputype
= CPU_PR4450
;
780 c
->isa_level
= MIPS_CPU_ISA_M32R1
;
783 panic("Unknown Philips Core!"); /* REVISIT: die? */
789 __init
void cpu_probe(void)
791 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
793 c
->processor_id
= PRID_IMP_UNKNOWN
;
794 c
->fpu_id
= FPIR_IMP_NONE
;
795 c
->cputype
= CPU_UNKNOWN
;
797 c
->processor_id
= read_c0_prid();
798 switch (c
->processor_id
& 0xff0000) {
799 case PRID_COMP_LEGACY
:
805 case PRID_COMP_ALCHEMY
:
806 cpu_probe_alchemy(c
);
808 case PRID_COMP_SIBYTE
:
811 case PRID_COMP_SANDCRAFT
:
812 cpu_probe_sandcraft(c
);
814 case PRID_COMP_PHILIPS
:
815 cpu_probe_philips(c
);
818 c
->cputype
= CPU_UNKNOWN
;
820 if (c
->options
& MIPS_CPU_FPU
) {
821 c
->fpu_id
= cpu_get_fpu_id();
823 if (c
->isa_level
== MIPS_CPU_ISA_M32R1
||
824 c
->isa_level
== MIPS_CPU_ISA_M32R2
||
825 c
->isa_level
== MIPS_CPU_ISA_M64R1
||
826 c
->isa_level
== MIPS_CPU_ISA_M64R2
) {
827 if (c
->fpu_id
& MIPS_FPIR_3D
)
828 c
->ases
|= MIPS_ASE_MIPS3D
;
833 __init
void cpu_report(void)
835 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
837 printk("CPU revision is: %08x\n", c
->processor_id
);
838 if (c
->options
& MIPS_CPU_FPU
)
839 printk("FPU revision is: %08x\n", c
->fpu_id
);