arch/mips/kernel/genex.S

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
   7  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   8  * Copyright (C) 2001 MIPS Technologies, Inc.
   9  * Copyright (C) 2002 Maciej W. Rozycki
  10  */
  11 #include <linux/init.h>
  12
  13 #include <asm/asm.h>
  14 #include <asm/asmmacro.h>
  15 #include <asm/cacheops.h>
  16 #include <asm/irqflags.h>
  17 #include <asm/regdef.h>
  18 #include <asm/fpregdef.h>
  19 #include <asm/mipsregs.h>
  20 #include <asm/stackframe.h>
  21 #include <asm/war.h>
  22
  23 #define PANIC_PIC(msg)                                  \
  24                 .set push;                              \
  25                 .set    reorder;                        \
  26                 PTR_LA  a0,8f;                          \
  27                 .set    noat;                           \
  28                 PTR_LA  AT, panic;                      \
  29                 jr      AT;                             \
  30 9:              b       9b;                             \
  31                 .set    pop;                            \
  32                 TEXT(msg)
  33
  34         __INIT
  35
  36 NESTED(except_vec0_generic, 0, sp)
  37         PANIC_PIC("Exception vector 0 called")
  38         END(except_vec0_generic)
  39
  40 NESTED(except_vec1_generic, 0, sp)
  41         PANIC_PIC("Exception vector 1 called")
  42         END(except_vec1_generic)
  43
  44 /*
  45  * General exception vector for all other CPUs.
  46  *
  47  * Be careful when changing this, it has to be at most 128 bytes
  48  * to fit into space reserved for the exception handler.
  49  */
  50 NESTED(except_vec3_generic, 0, sp)
  51         .set    push
  52         .set    noat
  53 #if R5432_CP0_INTERRUPT_WAR
  54         mfc0    k0, CP0_INDEX
  55 #endif
  56         mfc0    k1, CP0_CAUSE
  57         andi    k1, k1, 0x7c
  58 #ifdef CONFIG_64BIT
  59         dsll    k1, k1, 1
  60 #endif
  61         PTR_L   k0, exception_handlers(k1)
  62         jr      k0
  63         .set    pop
  64         END(except_vec3_generic)
  65
  66 /*
  67  * General exception handler for CPUs with virtual coherency exception.
  68  *
  69  * Be careful when changing this, it has to be at most 256 (as a special
  70  * exception) bytes to fit into space reserved for the exception handler.
  71  */
  72 NESTED(except_vec3_r4000, 0, sp)
  73         .set    push
  74         .set    mips3
  75         .set    noat
  76         mfc0    k1, CP0_CAUSE
  77         li      k0, 31<<2
  78         andi    k1, k1, 0x7c
  79         .set    push
  80         .set    noreorder
  81         .set    nomacro
  82         beq     k1, k0, handle_vced
  83          li     k0, 14<<2
  84         beq     k1, k0, handle_vcei
  85 #ifdef CONFIG_64BIT
  86          dsll   k1, k1, 1
  87 #endif
  88         .set    pop
  89         PTR_L   k0, exception_handlers(k1)
  90         jr      k0
  91
  92         /*
  93          * Big shit, we now may have two dirty primary cache lines for the same
  94          * physical address.  We can safely invalidate the line pointed to by
  95          * c0_badvaddr because after return from this exception handler the
  96          * load / store will be re-executed.
  97          */
  98 handle_vced:
  99         MFC0    k0, CP0_BADVADDR
 100         li      k1, -4                                  # Is this ...
 101         and     k0, k1                                  # ... really needed?
 102         mtc0    zero, CP0_TAGLO
 103         cache   Index_Store_Tag_D, (k0)
 104         cache   Hit_Writeback_Inv_SD, (k0)
 105 #ifdef CONFIG_PROC_FS
 106         PTR_LA  k0, vced_count
 107         lw      k1, (k0)
 108         addiu   k1, 1
 109         sw      k1, (k0)
 110 #endif
 111         eret
 112
 113 handle_vcei:
 114         MFC0    k0, CP0_BADVADDR
 115         cache   Hit_Writeback_Inv_SD, (k0)              # also cleans pi
 116 #ifdef CONFIG_PROC_FS
 117         PTR_LA  k0, vcei_count
 118         lw      k1, (k0)
 119         addiu   k1, 1
 120         sw      k1, (k0)
 121 #endif
 122         eret
 123         .set    pop
 124         END(except_vec3_r4000)
 125
 126         __FINIT
 127
 128         .align  5
 129 NESTED(handle_int, PT_SIZE, sp)
 130         SAVE_ALL
 131         CLI
 132         TRACE_IRQS_OFF
 133
 134         PTR_LA  ra, ret_from_irq
 135         move    a0, sp
 136         j       plat_irq_dispatch
 137         END(handle_int)
 138
 139         __INIT
 140
 141 /*
 142  * Special interrupt vector for MIPS64 ISA & embedded MIPS processors.
 143  * This is a dedicated interrupt exception vector which reduces the
 144  * interrupt processing overhead.  The jump instruction will be replaced
 145  * at the initialization time.
 146  *
 147  * Be careful when changing this, it has to be at most 128 bytes
 148  * to fit into space reserved for the exception handler.
 149  */
 150 NESTED(except_vec4, 0, sp)
 151 1:      j       1b                      /* Dummy, will be replaced */
 152         END(except_vec4)
 153
 154 /*
 155  * EJTAG debug exception handler.
 156  * The EJTAG debug exception entry point is 0xbfc00480, which
 157  * normally is in the boot PROM, so the boot PROM must do a
 158  * unconditional jump to this vector.
 159  */
 160 NESTED(except_vec_ejtag_debug, 0, sp)
 161         j       ejtag_debug_handler
 162         END(except_vec_ejtag_debug)
 163
 164         __FINIT
 165
 166 /*
 167  * Vectored interrupt handler.
 168  * This prototype is copied to ebase + n*IntCtl.VS and patched
 169  * to invoke the handler
 170  */
 171 NESTED(except_vec_vi, 0, sp)
 172         SAVE_SOME
 173         SAVE_AT
 174         .set    push
 175         .set    noreorder
 176 #ifdef CONFIG_MIPS_MT_SMTC
 177         /*
 178          * To keep from blindly blocking *all* interrupts
 179          * during service by SMTC kernel, we also want to
 180          * pass the IM value to be cleared.
 181          */
 182 EXPORT(except_vec_vi_mori)
 183         ori     a0, $0, 0
 184 #endif /* CONFIG_MIPS_MT_SMTC */
 185 EXPORT(except_vec_vi_lui)
 186         lui     v0, 0           /* Patched */
 187         j       except_vec_vi_handler
 188 EXPORT(except_vec_vi_ori)
 189          ori    v0, 0           /* Patched */
 190         .set    pop
 191         END(except_vec_vi)
 192 EXPORT(except_vec_vi_end)
 193
 194 /*
 195  * Common Vectored Interrupt code
 196  * Complete the register saves and invoke the handler which is passed in $v0
 197  */
 198 NESTED(except_vec_vi_handler, 0, sp)
 199         SAVE_TEMP
 200         SAVE_STATIC
 201 #ifdef CONFIG_MIPS_MT_SMTC
 202         /*
 203          * SMTC has an interesting problem that interrupts are level-triggered,
 204          * and the CLI macro will clear EXL, potentially causing a duplicate
 205          * interrupt service invocation. So we need to clear the associated
 206          * IM bit of Status prior to doing CLI, and restore it after the
 207          * service routine has been invoked - we must assume that the
 208          * service routine will have cleared the state, and any active
 209          * level represents a new or otherwised unserviced event...
 210          */
 211         mfc0    t1, CP0_STATUS
 212         and     t0, a0, t1
 213         mfc0    t2, CP0_TCCONTEXT
 214         or      t0, t0, t2
 215         mtc0    t0, CP0_TCCONTEXT
 216         xor     t1, t1, t0
 217         mtc0    t1, CP0_STATUS
 218         _ehb
 219 #endif /* CONFIG_MIPS_MT_SMTC */
 220         CLI
 221         TRACE_IRQS_OFF
 222         move    a0, sp
 223         jalr    v0
 224         j       ret_from_irq
 225         END(except_vec_vi_handler)
 226
 227 /*
 228  * EJTAG debug exception handler.
 229  */
 230 NESTED(ejtag_debug_handler, PT_SIZE, sp)
 231         .set    push
 232         .set    noat
 233         MTC0    k0, CP0_DESAVE
 234         mfc0    k0, CP0_DEBUG
 235
 236         sll     k0, k0, 30      # Check for SDBBP.
 237         bgez    k0, ejtag_return
 238
 239         PTR_LA  k0, ejtag_debug_buffer
 240         LONG_S  k1, 0(k0)
 241         SAVE_ALL
 242         move    a0, sp
 243         jal     ejtag_exception_handler
 244         RESTORE_ALL
 245         PTR_LA  k0, ejtag_debug_buffer
 246         LONG_L  k1, 0(k0)
 247
 248 ejtag_return:
 249         MFC0    k0, CP0_DESAVE
 250         .set    mips32
 251         deret
 252         .set pop
 253         END(ejtag_debug_handler)
 254
 255 /*
 256  * This buffer is reserved for the use of the EJTAG debug
 257  * handler.
 258  */
 259         .data
 260 EXPORT(ejtag_debug_buffer)
 261         .fill   LONGSIZE
 262         .previous
 263
 264         __INIT
 265
 266 /*
 267  * NMI debug exception handler for MIPS reference boards.
 268  * The NMI debug exception entry point is 0xbfc00000, which
 269  * normally is in the boot PROM, so the boot PROM must do a
 270  * unconditional jump to this vector.
 271  */
 272 NESTED(except_vec_nmi, 0, sp)
 273         j       nmi_handler
 274         END(except_vec_nmi)
 275
 276         __FINIT
 277
 278 NESTED(nmi_handler, PT_SIZE, sp)
 279         .set    push
 280         .set    noat
 281         SAVE_ALL
 282         move    a0, sp
 283         jal     nmi_exception_handler
 284         RESTORE_ALL
 285         .set    mips3
 286         eret
 287         .set    pop
 288         END(nmi_handler)
 289
 290         .macro  __build_clear_none
 291         .endm
 292
 293         .macro  __build_clear_sti
 294         TRACE_IRQS_ON
 295         STI
 296         .endm
 297
 298         .macro  __build_clear_cli
 299         CLI
 300         TRACE_IRQS_OFF
 301         .endm
 302
 303         .macro  __build_clear_fpe
 304         cfc1    a1, fcr31
 305         li      a2, ~(0x3f << 12)
 306         and     a2, a1
 307         ctc1    a2, fcr31
 308         TRACE_IRQS_ON
 309         STI
 310         .endm
 311
 312         .macro  __build_clear_ade
 313         MFC0    t0, CP0_BADVADDR
 314         PTR_S   t0, PT_BVADDR(sp)
 315         KMODE
 316         .endm
 317
 318         .macro  __BUILD_silent exception
 319         .endm
 320
 321         /* Gas tries to parse the PRINT argument as a string containing
 322            string escapes and emits bogus warnings if it believes to
 323            recognize an unknown escape code.  So make the arguments
 324            start with an n and gas will believe \n is ok ...  */
 325         .macro  __BUILD_verbose nexception
 326         LONG_L  a1, PT_EPC(sp)
 327 #ifdef CONFIG_32BIT
 328         PRINT("Got \nexception at %08lx\012")
 329 #endif
 330 #ifdef CONFIG_64BIT
 331         PRINT("Got \nexception at %016lx\012")
 332 #endif
 333         .endm
 334
 335         .macro  __BUILD_count exception
 336         LONG_L  t0,exception_count_\exception
 337         LONG_ADDIU t0, 1
 338         LONG_S  t0,exception_count_\exception
 339         .comm   exception_count\exception, 8, 8
 340         .endm
 341
 342         .macro  __BUILD_HANDLER exception handler clear verbose ext
 343         .align  5
 344         NESTED(handle_\exception, PT_SIZE, sp)
 345         .set    noat
 346         SAVE_ALL
 347         FEXPORT(handle_\exception\ext)
 348         __BUILD_clear_\clear
 349         .set    at
 350         __BUILD_\verbose \exception
 351         move    a0, sp
 352         jal     do_\handler
 353         j       ret_from_exception
 354         END(handle_\exception)
 355         .endm
 356
 357         .macro  BUILD_HANDLER exception handler clear verbose
 358         __BUILD_HANDLER \exception \handler \clear \verbose _int
 359         .endm
 360
 361         BUILD_HANDLER adel ade ade silent               /* #4  */
 362         BUILD_HANDLER ades ade ade silent               /* #5  */
 363         BUILD_HANDLER ibe be cli silent                 /* #6  */
 364         BUILD_HANDLER dbe be cli silent                 /* #7  */
 365         BUILD_HANDLER bp bp sti silent                  /* #9  */
 366         BUILD_HANDLER ri ri sti silent                  /* #10 */
 367         BUILD_HANDLER cpu cpu sti silent                /* #11 */
 368         BUILD_HANDLER ov ov sti silent                  /* #12 */
 369         BUILD_HANDLER tr tr sti silent                  /* #13 */
 370         BUILD_HANDLER fpe fpe fpe silent                /* #15 */
 371         BUILD_HANDLER mdmx mdmx sti silent              /* #22 */
 372         BUILD_HANDLER watch watch sti verbose           /* #23 */
 373         BUILD_HANDLER mcheck mcheck cli verbose         /* #24 */
 374         BUILD_HANDLER mt mt sti silent                  /* #25 */
 375         BUILD_HANDLER dsp dsp sti silent                /* #26 */
 376         BUILD_HANDLER reserved reserved sti verbose     /* others */
 377
 378 #ifdef CONFIG_64BIT
 379 /* A temporary overflow handler used by check_daddi(). */
 380
 381         __INIT
 382
 383         BUILD_HANDLER  daddi_ov daddi_ov none silent    /* #12 */
 384 #endif