2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 * Copyright (C) 2002, 2007 Maciej W. Rozycki
9 * Copyright (C) 2001, 2012 MIPS Technologies, Inc. All rights reserved.
11 #include <linux/init.h>
14 #include <asm/asmmacro.h>
15 #include <asm/cacheops.h>
16 #include <asm/irqflags.h>
17 #include <asm/regdef.h>
18 #include <asm/fpregdef.h>
19 #include <asm/mipsregs.h>
20 #include <asm/stackframe.h>
22 #include <asm/thread_info.h>
27 * General exception vector for all other CPUs.
29 * Be careful when changing this, it has to be at most 128 bytes
30 * to fit into space reserved for the exception handler.
32 NESTED(except_vec3_generic, 0, sp)
35 #if R5432_CP0_INTERRUPT_WAR
43 PTR_L k0, exception_handlers(k1)
46 END(except_vec3_generic)
49 * General exception handler for CPUs with virtual coherency exception.
51 * Be careful when changing this, it has to be at most 256 (as a special
52 * exception) bytes to fit into space reserved for the exception handler.
54 NESTED(except_vec3_r4000, 0, sp)
64 beq k1, k0, handle_vced
66 beq k1, k0, handle_vcei
71 PTR_L k0, exception_handlers(k1)
75 * Big shit, we now may have two dirty primary cache lines for the same
76 * physical address. We can safely invalidate the line pointed to by
77 * c0_badvaddr because after return from this exception handler the
78 * load / store will be re-executed.
82 li k1, -4 # Is this ...
83 and k0, k1 # ... really needed?
85 cache Index_Store_Tag_D, (k0)
86 cache Hit_Writeback_Inv_SD, (k0)
97 cache Hit_Writeback_Inv_SD, (k0) # also cleans pi
106 END(except_vec3_r4000)
110 .align 5 /* 32 byte rollback region */
114 /* start of rollback region */
115 LONG_L t0, TI_FLAGS($28)
117 andi t0, _TIF_NEED_RESCHED
122 #ifdef CONFIG_CPU_MICROMIPS
128 .set MIPS_ISA_ARCH_LEVEL_RAW
130 /* end of rollback region (the region size must be power of two) */
137 .macro BUILD_ROLLBACK_PROLOGUE handler
138 FEXPORT(rollback_\handler)
142 PTR_LA k1, __r4k_wait
143 ori k0, 0x1f /* 32 byte rollback region */
151 BUILD_ROLLBACK_PROLOGUE handle_int
152 NESTED(handle_int, PT_SIZE, sp)
153 #ifdef CONFIG_TRACE_IRQFLAGS
155 * Check to see if the interrupted code has just disabled
156 * interrupts and ignore this interrupt for now if so.
158 * local_irq_disable() disables interrupts and then calls
159 * trace_hardirqs_off() to track the state. If an interrupt is taken
160 * after interrupts are disabled but before the state is updated
161 * it will appear to restore_all that it is incorrectly returning with
162 * interrupts disabled
167 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
188 LONG_L s0, TI_REGS($28)
189 LONG_S sp, TI_REGS($28)
192 * SAVE_ALL ensures we are using a valid kernel stack for the thread.
193 * Check if we are already using the IRQ stack.
195 move s1, sp # Preserve the sp
197 /* Get IRQ stack for this CPU */
198 ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG
199 #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
200 lui k1, %hi(irq_stack)
202 lui k1, %highest(irq_stack)
203 daddiu k1, %higher(irq_stack)
205 daddiu k1, %hi(irq_stack)
208 LONG_SRL k0, SMP_CPUID_PTRSHIFT
210 LONG_L t0, %lo(irq_stack)(k1)
212 # Check if already on IRQ stack
213 PTR_LI t1, ~(_THREAD_SIZE-1)
217 /* Switch to IRQ stack */
218 li t1, _IRQ_STACK_SIZE
222 jal plat_irq_dispatch
228 #ifdef CONFIG_CPU_MICROMIPS
236 * Special interrupt vector for MIPS64 ISA & embedded MIPS processors.
237 * This is a dedicated interrupt exception vector which reduces the
238 * interrupt processing overhead. The jump instruction will be replaced
239 * at the initialization time.
241 * Be careful when changing this, it has to be at most 128 bytes
242 * to fit into space reserved for the exception handler.
244 NESTED(except_vec4, 0, sp)
245 1: j 1b /* Dummy, will be replaced */
249 * EJTAG debug exception handler.
250 * The EJTAG debug exception entry point is 0xbfc00480, which
251 * normally is in the boot PROM, so the boot PROM must do an
252 * unconditional jump to this vector.
254 NESTED(except_vec_ejtag_debug, 0, sp)
255 j ejtag_debug_handler
256 #ifdef CONFIG_CPU_MICROMIPS
259 END(except_vec_ejtag_debug)
264 * Vectored interrupt handler.
265 * This prototype is copied to ebase + n*IntCtl.VS and patched
266 * to invoke the handler
268 BUILD_ROLLBACK_PROLOGUE except_vec_vi
269 NESTED(except_vec_vi, 0, sp)
274 PTR_LA v1, except_vec_vi_handler
275 FEXPORT(except_vec_vi_lui)
276 lui v0, 0 /* Patched */
278 FEXPORT(except_vec_vi_ori)
279 ori v0, 0 /* Patched */
282 EXPORT(except_vec_vi_end)
285 * Common Vectored Interrupt code
286 * Complete the register saves and invoke the handler which is passed in $v0
288 NESTED(except_vec_vi_handler, 0, sp)
292 #ifdef CONFIG_TRACE_IRQFLAGS
298 LONG_L s0, TI_REGS($28)
299 LONG_S sp, TI_REGS($28)
302 * SAVE_ALL ensures we are using a valid kernel stack for the thread.
303 * Check if we are already using the IRQ stack.
305 move s1, sp # Preserve the sp
307 /* Get IRQ stack for this CPU */
308 ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG
309 #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
310 lui k1, %hi(irq_stack)
312 lui k1, %highest(irq_stack)
313 daddiu k1, %higher(irq_stack)
315 daddiu k1, %hi(irq_stack)
318 LONG_SRL k0, SMP_CPUID_PTRSHIFT
320 LONG_L t0, %lo(irq_stack)(k1)
322 # Check if already on IRQ stack
323 PTR_LI t1, ~(_THREAD_SIZE-1)
327 /* Switch to IRQ stack */
328 li t1, _IRQ_STACK_SIZE
338 END(except_vec_vi_handler)
341 * EJTAG debug exception handler.
343 NESTED(ejtag_debug_handler, PT_SIZE, sp)
349 sll k0, k0, 30 # Check for SDBBP.
350 bgez k0, ejtag_return
352 PTR_LA k0, ejtag_debug_buffer
356 jal ejtag_exception_handler
358 PTR_LA k0, ejtag_debug_buffer
366 END(ejtag_debug_handler)
369 * This buffer is reserved for the use of the EJTAG debug
373 EXPORT(ejtag_debug_buffer)
380 * NMI debug exception handler for MIPS reference boards.
381 * The NMI debug exception entry point is 0xbfc00000, which
382 * normally is in the boot PROM, so the boot PROM must do a
383 * unconditional jump to this vector.
385 NESTED(except_vec_nmi, 0, sp)
387 #ifdef CONFIG_CPU_MICROMIPS
394 NESTED(nmi_handler, PT_SIZE, sp)
398 * Clear ERL - restore segment mapping
399 * Clear BEV - required for page fault exception handler to work
403 li k1, ~(ST0_BEV | ST0_ERL)
409 jal nmi_exception_handler
410 /* nmi_exception_handler never returns */
414 .macro __build_clear_none
417 .macro __build_clear_sti
422 .macro __build_clear_cli
427 .macro __build_clear_fpe
429 /* gas fails to assemble cfc1 for some archs (octeon).*/ \
438 .macro __build_clear_msa_fpe
444 .macro __build_clear_ade
445 MFC0 t0, CP0_BADVADDR
446 PTR_S t0, PT_BVADDR(sp)
450 .macro __BUILD_silent exception
453 /* Gas tries to parse the PRINT argument as a string containing
454 string escapes and emits bogus warnings if it believes to
455 recognize an unknown escape code. So make the arguments
456 start with an n and gas will believe \n is ok ... */
457 .macro __BUILD_verbose nexception
458 LONG_L a1, PT_EPC(sp)
460 PRINT("Got \nexception at %08lx\012")
463 PRINT("Got \nexception at %016lx\012")
467 .macro __BUILD_count exception
468 LONG_L t0,exception_count_\exception
470 LONG_S t0,exception_count_\exception
471 .comm exception_count\exception, 8, 8
474 .macro __BUILD_HANDLER exception handler clear verbose ext
476 NESTED(handle_\exception, PT_SIZE, sp)
479 FEXPORT(handle_\exception\ext)
482 __BUILD_\verbose \exception
484 PTR_LA ra, ret_from_exception
486 END(handle_\exception)
489 .macro BUILD_HANDLER exception handler clear verbose
490 __BUILD_HANDLER \exception \handler \clear \verbose _int
493 BUILD_HANDLER adel ade ade silent /* #4 */
494 BUILD_HANDLER ades ade ade silent /* #5 */
495 BUILD_HANDLER ibe be cli silent /* #6 */
496 BUILD_HANDLER dbe be cli silent /* #7 */
497 BUILD_HANDLER bp bp sti silent /* #9 */
498 BUILD_HANDLER ri ri sti silent /* #10 */
499 BUILD_HANDLER cpu cpu sti silent /* #11 */
500 BUILD_HANDLER ov ov sti silent /* #12 */
501 BUILD_HANDLER tr tr sti silent /* #13 */
502 BUILD_HANDLER msa_fpe msa_fpe msa_fpe silent /* #14 */
503 BUILD_HANDLER fpe fpe fpe silent /* #15 */
504 BUILD_HANDLER ftlb ftlb none silent /* #16 */
505 BUILD_HANDLER msa msa sti silent /* #21 */
506 BUILD_HANDLER mdmx mdmx sti silent /* #22 */
507 #ifdef CONFIG_HARDWARE_WATCHPOINTS
509 * For watch, interrupts will be enabled after the watch
510 * registers are read.
512 BUILD_HANDLER watch watch cli silent /* #23 */
514 BUILD_HANDLER watch watch sti verbose /* #23 */
516 BUILD_HANDLER mcheck mcheck cli verbose /* #24 */
517 BUILD_HANDLER mt mt sti silent /* #25 */
518 BUILD_HANDLER dsp dsp sti silent /* #26 */
519 BUILD_HANDLER reserved reserved sti verbose /* others */
522 LEAF(handle_ri_rdhwr_vivt)
526 /* check if TLB contains a entry for EPC */
528 andi k1, MIPS_ENTRYHI_ASID | MIPS_ENTRYHI_ASIDX
530 PTR_SRL k0, _PAGE_SHIFT + 1
531 PTR_SLL k0, _PAGE_SHIFT + 1
539 bltz k1, handle_ri /* slow path */
541 END(handle_ri_rdhwr_vivt)
543 LEAF(handle_ri_rdhwr)
547 /* MIPS32: 0x7c03e83b: rdhwr v1,$29 */
548 /* microMIPS: 0x007d6b3c: rdhwr v1,$29 */
550 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS64_R2)
573 bne k0, k1, handle_ri /* if not ours */
576 /* The insn is rdhwr. No need to check CAUSE.BD here. */
577 get_saved_sp /* k1 := current_thread_info */
580 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
582 xori k1, _THREAD_MASK
583 LONG_L v1, TI_TP_VALUE(k1)
588 #ifndef CONFIG_CPU_DADDI_WORKAROUNDS
589 LONG_ADDIU k0, 4 /* stall on $k0 */
596 /* I hope three instructions between MTC0 and ERET are enough... */
598 xori k1, _THREAD_MASK
599 LONG_L v1, TI_TP_VALUE(k1)
608 /* A temporary overflow handler used by check_daddi(). */
612 BUILD_HANDLER daddi_ov daddi_ov none silent /* #12 */