arch/mips/kernel/head.S

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995 Waldorf Electronics
   7  * Written by Ralf Baechle and Andreas Busse
   8  * Copyright (C) 1994 - 99, 2003, 06 Ralf Baechle
   9  * Copyright (C) 1996 Paul M. Antoine
  10  * Modified for DECStation and hence R3000 support by Paul M. Antoine
  11  * Further modifications by David S. Miller and Harald Koerfgen
  12  * Copyright (C) 1999 Silicon Graphics, Inc.
  13  * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  14  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  15  */
  16 #include <linux/init.h>
  17 #include <linux/threads.h>
  18
  19 #include <asm/addrspace.h>
  20 #include <asm/asm.h>
  21 #include <asm/asmmacro.h>
  22 #include <asm/irqflags.h>
  23 #include <asm/regdef.h>
  24 #include <asm/pgtable-bits.h>
  25 #include <asm/mipsregs.h>
  26 #include <asm/stackframe.h>
  27
  28 #include <kernel-entry-init.h>
  29
  30         /*
  31          * For the moment disable interrupts, mark the kernel mode and
  32          * set ST0_KX so that the CPU does not spit fire when using
  33          * 64-bit addresses.  A full initialization of the CPU's status
  34          * register is done later in per_cpu_trap_init().
  35          */
  36         .macro  setup_c0_status set clr
  37         .set    push
  38 #ifdef CONFIG_MIPS_MT_SMTC
  39         /*
  40          * For SMTC, we need to set privilege and disable interrupts only for
  41          * the current TC, using the TCStatus register.
  42          */
  43         mfc0    t0, CP0_TCSTATUS
  44         /* Fortunately CU 0 is in the same place in both registers */
  45         /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
  46         li      t1, ST0_CU0 | 0x08001c00
  47         or      t0, t1
  48         /* Clear TKSU, leave IXMT */
  49         xori    t0, 0x00001800
  50         mtc0    t0, CP0_TCSTATUS
  51         _ehb
  52         /* We need to leave the global IE bit set, but clear EXL...*/
  53         mfc0    t0, CP0_STATUS
  54         or      t0, ST0_CU0 | ST0_EXL | ST0_ERL | \set | \clr
  55         xor     t0, ST0_EXL | ST0_ERL | \clr
  56         mtc0    t0, CP0_STATUS
  57 #else
  58         mfc0    t0, CP0_STATUS
  59         or      t0, ST0_CU0|\set|0x1f|\clr
  60         xor     t0, 0x1f|\clr
  61         mtc0    t0, CP0_STATUS
  62         .set    noreorder
  63         sll     zero,3                          # ehb
  64 #endif
  65         .set    pop
  66         .endm
  67
  68         .macro  setup_c0_status_pri
  69 #ifdef CONFIG_64BIT
  70         setup_c0_status ST0_KX 0
  71 #else
  72         setup_c0_status 0 0
  73 #endif
  74         .endm
  75
  76         .macro  setup_c0_status_sec
  77 #ifdef CONFIG_64BIT
  78         setup_c0_status ST0_KX ST0_BEV
  79 #else
  80         setup_c0_status 0 ST0_BEV
  81 #endif
  82         .endm
  83
  84 #ifndef CONFIG_NO_EXCEPT_FILL
  85         /*
  86          * Reserved space for exception handlers.
  87          * Necessary for machines which link their kernels at KSEG0.
  88          */
  89         .fill   0x400
  90 #endif
  91
  92 EXPORT(_stext)
  93
  94 #ifdef CONFIG_BOOT_RAW
  95         /*
  96          * Give us a fighting chance of running if execution beings at the
  97          * kernel load address.  This is needed because this platform does
  98          * not have a ELF loader yet.
  99          */
 100 FEXPORT(__kernel_entry)
 101         j       kernel_entry
 102 #endif
 103
 104         __REF
 105
 106 NESTED(kernel_entry, 16, sp)                    # kernel entry point
 107
 108         kernel_entry_setup                      # cpu specific setup
 109
 110         setup_c0_status_pri
 111
 112         /* We might not get launched at the address the kernel is linked to,
 113            so we jump there.  */
 114         PTR_LA  t0, 0f
 115         jr      t0
 116 0:
 117
 118 #ifdef CONFIG_MIPS_MT_SMTC
 119         /*
 120          * In SMTC kernel, "CLI" is thread-specific, in TCStatus.
 121          * We still need to enable interrupts globally in Status,
 122          * and clear EXL/ERL.
 123          *
 124          * TCContext is used to track interrupt levels under
 125          * service in SMTC kernel. Clear for boot TC before
 126          * allowing any interrupts.
 127          */
 128         mtc0    zero, CP0_TCCONTEXT
 129
 130         mfc0    t0, CP0_STATUS
 131         ori     t0, t0, 0xff1f
 132         xori    t0, t0, 0x001e
 133         mtc0    t0, CP0_STATUS
 134 #endif /* CONFIG_MIPS_MT_SMTC */
 135
 136         PTR_LA          t0, __bss_start         # clear .bss
 137         LONG_S          zero, (t0)
 138         PTR_LA          t1, __bss_stop - LONGSIZE
 139 1:
 140         PTR_ADDIU       t0, LONGSIZE
 141         LONG_S          zero, (t0)
 142         bne             t0, t1, 1b
 143
 144         LONG_S          a0, fw_arg0             # firmware arguments
 145         LONG_S          a1, fw_arg1
 146         LONG_S          a2, fw_arg2
 147         LONG_S          a3, fw_arg3
 148
 149         MTC0            zero, CP0_CONTEXT       # clear context register
 150         PTR_LA          $28, init_thread_union
 151         /* Set the SP after an empty pt_regs.  */
 152         PTR_LI          sp, _THREAD_SIZE - 32 - PT_SIZE
 153         PTR_ADDU        sp, $28
 154         back_to_back_c0_hazard
 155         set_saved_sp    sp, t0, t1
 156         PTR_SUBU        sp, 4 * SZREG           # init stack pointer
 157
 158         j               start_kernel
 159         END(kernel_entry)
 160
 161 #ifdef CONFIG_SMP
 162 /*
 163  * SMP slave cpus entry point.  Board specific code for bootstrap calls this
 164  * function after setting up the stack and gp registers.
 165  */
 166 NESTED(smp_bootstrap, 16, sp)
 167 #ifdef CONFIG_MIPS_MT_SMTC
 168         /*
 169          * Read-modify-writes of Status must be atomic, and this
 170          * is one case where CLI is invoked without EXL being
 171          * necessarily set. The CLI and setup_c0_status will
 172          * in fact be redundant for all but the first TC of
 173          * each VPE being booted.
 174          */
 175         DMT     10      # dmt t2 /* t0, t1 are used by CLI and setup_c0_status() */
 176         jal     mips_ihb
 177 #endif /* CONFIG_MIPS_MT_SMTC */
 178         smp_slave_setup
 179         setup_c0_status_sec
 180 #ifdef CONFIG_MIPS_MT_SMTC
 181         andi    t2, t2, VPECONTROL_TE
 182         beqz    t2, 2f
 183         EMT             # emt
 184 2:
 185 #endif /* CONFIG_MIPS_MT_SMTC */
 186         j       start_secondary
 187         END(smp_bootstrap)
 188 #endif /* CONFIG_SMP */