arch/mips/kernel/i8259.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Code to handle x86 style IRQs plus some generic interrupt stuff.
   7  *
   8  * Copyright (C) 1992 Linus Torvalds
   9  * Copyright (C) 1994 - 2000 Ralf Baechle
  10  */
  11 #include <linux/delay.h>
  12 #include <linux/init.h>
  13 #include <linux/ioport.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/kernel.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/sysdev.h>
  18 #include <linux/irq.h>
  19
  20 #include <asm/i8259.h>
  21 #include <asm/io.h>
  22
  23 /*
  24  * This is the 'legacy' 8259A Programmable Interrupt Controller,
  25  * present in the majority of PC/AT boxes.
  26  * plus some generic x86 specific things if generic specifics makes
  27  * any sense at all.
  28  * this file should become arch/i386/kernel/irq.c when the old irq.c
  29  * moves to arch independent land
  30  */
  31
  32 static int i8259A_auto_eoi = -1;
  33 DEFINE_RAW_SPINLOCK(i8259A_lock);
  34 static void disable_8259A_irq(unsigned int irq);
  35 static void enable_8259A_irq(unsigned int irq);
  36 static void mask_and_ack_8259A(unsigned int irq);
  37 static void init_8259A(int auto_eoi);
  38
  39 static struct irq_chip i8259A_chip = {
  40         .name           = "XT-PIC",
  41         .mask           = disable_8259A_irq,
  42         .disable        = disable_8259A_irq,
  43         .unmask         = enable_8259A_irq,
  44         .mask_ack       = mask_and_ack_8259A,
  45 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
  46         .set_affinity   = plat_set_irq_affinity,
  47 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
  48 };
  49
  50 /*
  51  * 8259A PIC functions to handle ISA devices:
  52  */
  53
  54 /*
  55  * This contains the irq mask for both 8259A irq controllers,
  56  */
  57 static unsigned int cached_irq_mask = 0xffff;
  58
  59 #define cached_master_mask      (cached_irq_mask)
  60 #define cached_slave_mask       (cached_irq_mask >> 8)
  61
  62 static void disable_8259A_irq(unsigned int irq)
  63 {
  64         unsigned int mask;
  65         unsigned long flags;
  66
  67         irq -= I8259A_IRQ_BASE;
  68         mask = 1 << irq;
  69         raw_spin_lock_irqsave(&i8259A_lock, flags);
  70         cached_irq_mask |= mask;
  71         if (irq & 8)
  72                 outb(cached_slave_mask, PIC_SLAVE_IMR);
  73         else
  74                 outb(cached_master_mask, PIC_MASTER_IMR);
  75         raw_spin_unlock_irqrestore(&i8259A_lock, flags);
  76 }
  77
  78 static void enable_8259A_irq(unsigned int irq)
  79 {
  80         unsigned int mask;
  81         unsigned long flags;
  82
  83         irq -= I8259A_IRQ_BASE;
  84         mask = ~(1 << irq);
  85         raw_spin_lock_irqsave(&i8259A_lock, flags);
  86         cached_irq_mask &= mask;
  87         if (irq & 8)
  88                 outb(cached_slave_mask, PIC_SLAVE_IMR);
  89         else
  90                 outb(cached_master_mask, PIC_MASTER_IMR);
  91         raw_spin_unlock_irqrestore(&i8259A_lock, flags);
  92 }
  93
  94 int i8259A_irq_pending(unsigned int irq)
  95 {
  96         unsigned int mask;
  97         unsigned long flags;
  98         int ret;
  99
 100         irq -= I8259A_IRQ_BASE;
 101         mask = 1 << irq;
 102         raw_spin_lock_irqsave(&i8259A_lock, flags);
 103         if (irq < 8)
 104                 ret = inb(PIC_MASTER_CMD) & mask;
 105         else
 106                 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
 107         raw_spin_unlock_irqrestore(&i8259A_lock, flags);
 108
 109         return ret;
 110 }
 111
 112 void make_8259A_irq(unsigned int irq)
 113 {
 114         disable_irq_nosync(irq);
 115         set_irq_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
 116         enable_irq(irq);
 117 }
 118
 119 /*
 120  * This function assumes to be called rarely. Switching between
 121  * 8259A registers is slow.
 122  * This has to be protected by the irq controller spinlock
 123  * before being called.
 124  */
 125 static inline int i8259A_irq_real(unsigned int irq)
 126 {
 127         int value;
 128         int irqmask = 1 << irq;
 129
 130         if (irq < 8) {
 131                 outb(0x0B, PIC_MASTER_CMD);     /* ISR register */
 132                 value = inb(PIC_MASTER_CMD) & irqmask;
 133                 outb(0x0A, PIC_MASTER_CMD);     /* back to the IRR register */
 134                 return value;
 135         }
 136         outb(0x0B, PIC_SLAVE_CMD);      /* ISR register */
 137         value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
 138         outb(0x0A, PIC_SLAVE_CMD);      /* back to the IRR register */
 139         return value;
 140 }
 141
 142 /*
 143  * Careful! The 8259A is a fragile beast, it pretty
 144  * much _has_ to be done exactly like this (mask it
 145  * first, _then_ send the EOI, and the order of EOI
 146  * to the two 8259s is important!
 147  */
 148 static void mask_and_ack_8259A(unsigned int irq)
 149 {
 150         unsigned int irqmask;
 151         unsigned long flags;
 152
 153         irq -= I8259A_IRQ_BASE;
 154         irqmask = 1 << irq;
 155         raw_spin_lock_irqsave(&i8259A_lock, flags);
 156         /*
 157          * Lightweight spurious IRQ detection. We do not want
 158          * to overdo spurious IRQ handling - it's usually a sign
 159          * of hardware problems, so we only do the checks we can
 160          * do without slowing down good hardware unnecessarily.
 161          *
 162          * Note that IRQ7 and IRQ15 (the two spurious IRQs
 163          * usually resulting from the 8259A-1|2 PICs) occur
 164          * even if the IRQ is masked in the 8259A. Thus we
 165          * can check spurious 8259A IRQs without doing the
 166          * quite slow i8259A_irq_real() call for every IRQ.
 167          * This does not cover 100% of spurious interrupts,
 168          * but should be enough to warn the user that there
 169          * is something bad going on ...
 170          */
 171         if (cached_irq_mask & irqmask)
 172                 goto spurious_8259A_irq;
 173         cached_irq_mask |= irqmask;
 174
 175 handle_real_irq:
 176         if (irq & 8) {
 177                 inb(PIC_SLAVE_IMR);     /* DUMMY - (do we need this?) */
 178                 outb(cached_slave_mask, PIC_SLAVE_IMR);
 179                 outb(0x60+(irq&7), PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
 180                 outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
 181         } else {
 182                 inb(PIC_MASTER_IMR);    /* DUMMY - (do we need this?) */
 183                 outb(cached_master_mask, PIC_MASTER_IMR);
 184                 outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
 185         }
 186         smtc_im_ack_irq(irq);
 187         raw_spin_unlock_irqrestore(&i8259A_lock, flags);
 188         return;
 189
 190 spurious_8259A_irq:
 191         /*
 192          * this is the slow path - should happen rarely.
 193          */
 194         if (i8259A_irq_real(irq))
 195                 /*
 196                  * oops, the IRQ _is_ in service according to the
 197                  * 8259A - not spurious, go handle it.
 198                  */
 199                 goto handle_real_irq;
 200
 201         {
 202                 static int spurious_irq_mask;
 203                 /*
 204                  * At this point we can be sure the IRQ is spurious,
 205                  * lets ACK and report it. [once per IRQ]
 206                  */
 207                 if (!(spurious_irq_mask & irqmask)) {
 208                         printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
 209                         spurious_irq_mask |= irqmask;
 210                 }
 211                 atomic_inc(&irq_err_count);
 212                 /*
 213                  * Theoretically we do not have to handle this IRQ,
 214                  * but in Linux this does not cause problems and is
 215                  * simpler for us.
 216                  */
 217                 goto handle_real_irq;
 218         }
 219 }
 220
 221 static int i8259A_resume(struct sys_device *dev)
 222 {
 223         if (i8259A_auto_eoi >= 0)
 224                 init_8259A(i8259A_auto_eoi);
 225         return 0;
 226 }
 227
 228 static int i8259A_shutdown(struct sys_device *dev)
 229 {
 230         /* Put the i8259A into a quiescent state that
 231          * the kernel initialization code can get it
 232          * out of.
 233          */
 234         if (i8259A_auto_eoi >= 0) {
 235                 outb(0xff, PIC_MASTER_IMR);     /* mask all of 8259A-1 */
 236                 outb(0xff, PIC_SLAVE_IMR);      /* mask all of 8259A-1 */
 237         }
 238         return 0;
 239 }
 240
 241 static struct sysdev_class i8259_sysdev_class = {
 242         .name = "i8259",
 243         .resume = i8259A_resume,
 244         .shutdown = i8259A_shutdown,
 245 };
 246
 247 static struct sys_device device_i8259A = {
 248         .id     = 0,
 249         .cls    = &i8259_sysdev_class,
 250 };
 251
 252 static int __init i8259A_init_sysfs(void)
 253 {
 254         int error = sysdev_class_register(&i8259_sysdev_class);
 255         if (!error)
 256                 error = sysdev_register(&device_i8259A);
 257         return error;
 258 }
 259
 260 device_initcall(i8259A_init_sysfs);
 261
 262 static void init_8259A(int auto_eoi)
 263 {
 264         unsigned long flags;
 265
 266         i8259A_auto_eoi = auto_eoi;
 267
 268         raw_spin_lock_irqsave(&i8259A_lock, flags);
 269
 270         outb(0xff, PIC_MASTER_IMR);     /* mask all of 8259A-1 */
 271         outb(0xff, PIC_SLAVE_IMR);      /* mask all of 8259A-2 */
 272
 273         /*
 274          * outb_p - this has to work on a wide range of PC hardware.
 275          */
 276         outb_p(0x11, PIC_MASTER_CMD);   /* ICW1: select 8259A-1 init */
 277         outb_p(I8259A_IRQ_BASE + 0, PIC_MASTER_IMR);    /* ICW2: 8259A-1 IR0 mapped to I8259A_IRQ_BASE + 0x00 */
 278         outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);   /* 8259A-1 (the master) has a slave on IR2 */
 279         if (auto_eoi)   /* master does Auto EOI */
 280                 outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
 281         else            /* master expects normal EOI */
 282                 outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
 283
 284         outb_p(0x11, PIC_SLAVE_CMD);    /* ICW1: select 8259A-2 init */
 285         outb_p(I8259A_IRQ_BASE + 8, PIC_SLAVE_IMR);     /* ICW2: 8259A-2 IR0 mapped to I8259A_IRQ_BASE + 0x08 */
 286         outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR);  /* 8259A-2 is a slave on master's IR2 */
 287         outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
 288         if (auto_eoi)
 289                 /*
 290                  * In AEOI mode we just have to mask the interrupt
 291                  * when acking.
 292                  */
 293                 i8259A_chip.mask_ack = disable_8259A_irq;
 294         else
 295                 i8259A_chip.mask_ack = mask_and_ack_8259A;
 296
 297         udelay(100);            /* wait for 8259A to initialize */
 298
 299         outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
 300         outb(cached_slave_mask, PIC_SLAVE_IMR);   /* restore slave IRQ mask */
 301
 302         raw_spin_unlock_irqrestore(&i8259A_lock, flags);
 303 }
 304
 305 /*
 306  * IRQ2 is cascade interrupt to second interrupt controller
 307  */
 308 static struct irqaction irq2 = {
 309         .handler = no_action,
 310         .name = "cascade",
 311 };
 312
 313 static struct resource pic1_io_resource = {
 314         .name = "pic1",
 315         .start = PIC_MASTER_CMD,
 316         .end = PIC_MASTER_IMR,
 317         .flags = IORESOURCE_BUSY
 318 };
 319
 320 static struct resource pic2_io_resource = {
 321         .name = "pic2",
 322         .start = PIC_SLAVE_CMD,
 323         .end = PIC_SLAVE_IMR,
 324         .flags = IORESOURCE_BUSY
 325 };
 326
 327 /*
 328  * On systems with i8259-style interrupt controllers we assume for
 329  * driver compatibility reasons interrupts 0 - 15 to be the i8259
 330  * interrupts even if the hardware uses a different interrupt numbering.
 331  */
 332 void __init init_i8259_irqs(void)
 333 {
 334         int i;
 335
 336         insert_resource(&ioport_resource, &pic1_io_resource);
 337         insert_resource(&ioport_resource, &pic2_io_resource);
 338
 339         init_8259A(0);
 340
 341         for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++) {
 342                 set_irq_chip_and_handler(i, &i8259A_chip, handle_level_irq);
 343                 set_irq_probe(i);
 344         }
 345
 346         setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);
 347 }