arch/mips/kernel/smp-mt.c

   1 /*
   2  *  This program is free software; you can distribute it and/or modify it
   3  *  under the terms of the GNU General Public License (Version 2) as
   4  *  published by the Free Software Foundation.
   5  *
   6  *  This program is distributed in the hope it will be useful, but WITHOUT
   7  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   8  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
   9  *  for more details.
  10  *
  11  *  You should have received a copy of the GNU General Public License along
  12  *  with this program; if not, write to the Free Software Foundation, Inc.,
  13  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  14  *
  15  * Copyright (C) 2004, 05, 06 MIPS Technologies, Inc.
  16  *    Elizabeth Clarke (beth@mips.com)
  17  *    Ralf Baechle (ralf@linux-mips.org)
  18  * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/sched.h>
  22 #include <linux/cpumask.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irqchip/mips-gic.h>
  25 #include <linux/compiler.h>
  26 #include <linux/sched/task_stack.h>
  27 #include <linux/smp.h>
  28
  29 #include <linux/atomic.h>
  30 #include <asm/cacheflush.h>
  31 #include <asm/cpu.h>
  32 #include <asm/processor.h>
  33 #include <asm/hardirq.h>
  34 #include <asm/mmu_context.h>
  35 #include <asm/time.h>
  36 #include <asm/mipsregs.h>
  37 #include <asm/mipsmtregs.h>
  38 #include <asm/mips_mt.h>
  39
  40 static void __init smvp_copy_vpe_config(void)
  41 {
  42         write_vpe_c0_status(
  43                 (read_c0_status() & ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0);
  44
  45         /* set config to be the same as vpe0, particularly kseg0 coherency alg */
  46         write_vpe_c0_config( read_c0_config());
  47
  48         /* make sure there are no software interrupts pending */
  49         write_vpe_c0_cause(0);
  50
  51         /* Propagate Config7 */
  52         write_vpe_c0_config7(read_c0_config7());
  53
  54         write_vpe_c0_count(read_c0_count());
  55 }
  56
  57 static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0,
  58         unsigned int ncpu)
  59 {
  60         if (tc > ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT))
  61                 return ncpu;
  62
  63         /* Deactivate all but VPE 0 */
  64         if (tc != 0) {
  65                 unsigned long tmp = read_vpe_c0_vpeconf0();
  66
  67                 tmp &= ~VPECONF0_VPA;
  68
  69                 /* master VPE */
  70                 tmp |= VPECONF0_MVP;
  71                 write_vpe_c0_vpeconf0(tmp);
  72
  73                 /* Record this as available CPU */
  74                 set_cpu_possible(tc, true);
  75                 set_cpu_present(tc, true);
  76                 __cpu_number_map[tc]    = ++ncpu;
  77                 __cpu_logical_map[ncpu] = tc;
  78         }
  79
  80         /* Disable multi-threading with TC's */
  81         write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);
  82
  83         if (tc != 0)
  84                 smvp_copy_vpe_config();
  85
  86         return ncpu;
  87 }
  88
  89 static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0)
  90 {
  91         unsigned long tmp;
  92
  93         if (!tc)
  94                 return;
  95
  96         /* bind a TC to each VPE, May as well put all excess TC's
  97            on the last VPE */
  98         if (tc >= (((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1))
  99                 write_tc_c0_tcbind(read_tc_c0_tcbind() | ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT));
 100         else {
 101                 write_tc_c0_tcbind(read_tc_c0_tcbind() | tc);
 102
 103                 /* and set XTC */
 104                 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | (tc << VPECONF0_XTC_SHIFT));
 105         }
 106
 107         tmp = read_tc_c0_tcstatus();
 108
 109         /* mark not allocated and not dynamically allocatable */
 110         tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
 111         tmp |= TCSTATUS_IXMT;           /* interrupt exempt */
 112         write_tc_c0_tcstatus(tmp);
 113
 114         write_tc_c0_tchalt(TCHALT_H);
 115 }
 116
 117 static void vsmp_send_ipi_single(int cpu, unsigned int action)
 118 {
 119         int i;
 120         unsigned long flags;
 121         int vpflags;
 122
 123 #ifdef CONFIG_MIPS_GIC
 124         if (gic_present) {
 125                 mips_smp_send_ipi_single(cpu, action);
 126                 return;
 127         }
 128 #endif
 129         local_irq_save(flags);
 130
 131         vpflags = dvpe();       /* can't access the other CPU's registers whilst MVPE enabled */
 132
 133         switch (action) {
 134         case SMP_CALL_FUNCTION:
 135                 i = C_SW1;
 136                 break;
 137
 138         case SMP_RESCHEDULE_YOURSELF:
 139         default:
 140                 i = C_SW0;
 141                 break;
 142         }
 143
 144         /* 1:1 mapping of vpe and tc... */
 145         settc(cpu);
 146         write_vpe_c0_cause(read_vpe_c0_cause() | i);
 147         evpe(vpflags);
 148
 149         local_irq_restore(flags);
 150 }
 151
 152 static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
 153 {
 154         unsigned int i;
 155
 156         for_each_cpu(i, mask)
 157                 vsmp_send_ipi_single(i, action);
 158 }
 159
 160 static void vsmp_init_secondary(void)
 161 {
 162 #ifdef CONFIG_MIPS_GIC
 163         /* This is Malta specific: IPI,performance and timer interrupts */
 164         if (gic_present)
 165                 change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
 166                                          STATUSF_IP4 | STATUSF_IP5 |
 167                                          STATUSF_IP6 | STATUSF_IP7);
 168         else
 169 #endif
 170                 change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 |
 171                                          STATUSF_IP6 | STATUSF_IP7);
 172 }
 173
 174 static void vsmp_smp_finish(void)
 175 {
 176         /* CDFIXME: remove this? */
 177         write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
 178
 179 #ifdef CONFIG_MIPS_MT_FPAFF
 180         /* If we have an FPU, enroll ourselves in the FPU-full mask */
 181         if (cpu_has_fpu)
 182                 cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
 183 #endif /* CONFIG_MIPS_MT_FPAFF */
 184
 185         local_irq_enable();
 186 }
 187
 188 /*
 189  * Setup the PC, SP, and GP of a secondary processor and start it
 190  * running!
 191  * smp_bootstrap is the place to resume from
 192  * __KSTK_TOS(idle) is apparently the stack pointer
 193  * (unsigned long)idle->thread_info the gp
 194  * assumes a 1:1 mapping of TC => VPE
 195  */
 196 static void vsmp_boot_secondary(int cpu, struct task_struct *idle)
 197 {
 198         struct thread_info *gp = task_thread_info(idle);
 199         dvpe();
 200         set_c0_mvpcontrol(MVPCONTROL_VPC);
 201
 202         settc(cpu);
 203
 204         /* restart */
 205         write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);
 206
 207         /* enable the tc this vpe/cpu will be running */
 208         write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~TCSTATUS_IXMT) | TCSTATUS_A);
 209
 210         write_tc_c0_tchalt(0);
 211
 212         /* enable the VPE */
 213         write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
 214
 215         /* stack pointer */
 216         write_tc_gpr_sp( __KSTK_TOS(idle));
 217
 218         /* global pointer */
 219         write_tc_gpr_gp((unsigned long)gp);
 220
 221         flush_icache_range((unsigned long)gp,
 222                            (unsigned long)(gp + sizeof(struct thread_info)));
 223
 224         /* finally out of configuration and into chaos */
 225         clear_c0_mvpcontrol(MVPCONTROL_VPC);
 226
 227         evpe(EVPE_ENABLE);
 228 }
 229
 230 /*
 231  * Common setup before any secondaries are started
 232  * Make sure all CPU's are in a sensible state before we boot any of the
 233  * secondaries
 234  */
 235 static void __init vsmp_smp_setup(void)
 236 {
 237         unsigned int mvpconf0, ntc, tc, ncpu = 0;
 238         unsigned int nvpe;
 239
 240 #ifdef CONFIG_MIPS_MT_FPAFF
 241         /* If we have an FPU, enroll ourselves in the FPU-full mask */
 242         if (cpu_has_fpu)
 243                 cpumask_set_cpu(0, &mt_fpu_cpumask);
 244 #endif /* CONFIG_MIPS_MT_FPAFF */
 245         if (!cpu_has_mipsmt)
 246                 return;
 247
 248         /* disable MT so we can configure */
 249         dvpe();
 250         dmt();
 251
 252         /* Put MVPE's into 'configuration state' */
 253         set_c0_mvpcontrol(MVPCONTROL_VPC);
 254
 255         mvpconf0 = read_c0_mvpconf0();
 256         ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT;
 257
 258         nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
 259         smp_num_siblings = nvpe;
 260
 261         /* we'll always have more TC's than VPE's, so loop setting everything
 262            to a sensible state */
 263         for (tc = 0; tc <= ntc; tc++) {
 264                 settc(tc);
 265
 266                 smvp_tc_init(tc, mvpconf0);
 267                 ncpu = smvp_vpe_init(tc, mvpconf0, ncpu);
 268         }
 269
 270         /* Release config state */
 271         clear_c0_mvpcontrol(MVPCONTROL_VPC);
 272
 273         /* We'll wait until starting the secondaries before starting MVPE */
 274
 275         printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu);
 276 }
 277
 278 static void __init vsmp_prepare_cpus(unsigned int max_cpus)
 279 {
 280         mips_mt_set_cpuoptions();
 281 }
 282
 283 struct plat_smp_ops vsmp_smp_ops = {
 284         .send_ipi_single        = vsmp_send_ipi_single,
 285         .send_ipi_mask          = vsmp_send_ipi_mask,
 286         .init_secondary         = vsmp_init_secondary,
 287         .smp_finish             = vsmp_smp_finish,
 288         .boot_secondary         = vsmp_boot_secondary,
 289         .smp_setup              = vsmp_smp_setup,
 290         .prepare_cpus           = vsmp_prepare_cpus,
 291 };
 292