2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version 2
5 * of the License, or (at your option) any later version.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
16 * Copyright (C) 2004 Mips Technologies, Inc
17 * Copyright (C) 2008 Kevin D. Kissell
20 #include <linux/clockchips.h>
21 #include <linux/kernel.h>
22 #include <linux/sched.h>
23 #include <linux/smp.h>
24 #include <linux/cpumask.h>
25 #include <linux/interrupt.h>
26 #include <linux/kernel_stat.h>
27 #include <linux/module.h>
30 #include <asm/processor.h>
31 #include <asm/atomic.h>
32 #include <asm/system.h>
33 #include <asm/hardirq.h>
34 #include <asm/hazards.h>
36 #include <asm/mmu_context.h>
37 #include <asm/mipsregs.h>
38 #include <asm/cacheflush.h>
40 #include <asm/addrspace.h>
42 #include <asm/smtc_proc.h>
45 * SMTC Kernel needs to manipulate low-level CPU interrupt mask
46 * in do_IRQ. These are passed in setup_irq_smtc() and stored
49 unsigned long irq_hwmask
[NR_IRQS
];
51 #define LOCK_MT_PRA() \
52 local_irq_save(flags); \
55 #define UNLOCK_MT_PRA() \
57 local_irq_restore(flags)
59 #define LOCK_CORE_PRA() \
60 local_irq_save(flags); \
63 #define UNLOCK_CORE_PRA() \
65 local_irq_restore(flags)
68 * Data structures purely associated with SMTC parallelism
73 * Table for tracking ASIDs whose lifetime is prolonged.
76 asiduse smtc_live_asid
[MAX_SMTC_TLBS
][MAX_SMTC_ASIDS
];
80 * Number of InterProcessor Interrupt (IPI) message buffers to allocate
83 #define IPIBUF_PER_CPU 4
85 struct smtc_ipi_q IPIQ
[NR_CPUS
];
86 static struct smtc_ipi_q freeIPIq
;
89 /* Forward declarations */
91 void ipi_decode(struct smtc_ipi
*);
92 static void post_direct_ipi(int cpu
, struct smtc_ipi
*pipi
);
93 static void setup_cross_vpe_interrupts(unsigned int nvpe
);
94 void init_smtc_stats(void);
96 /* Global SMTC Status */
98 unsigned int smtc_status
= 0;
100 /* Boot command line configuration overrides */
102 static int vpe0limit
;
103 static int ipibuffers
= 0;
104 static int nostlb
= 0;
105 static int asidmask
= 0;
106 unsigned long smtc_asid_mask
= 0xff;
108 static int __init
vpe0tcs(char *str
)
110 get_option(&str
, &vpe0limit
);
115 static int __init
ipibufs(char *str
)
117 get_option(&str
, &ipibuffers
);
121 static int __init
stlb_disable(char *s
)
127 static int __init
asidmask_set(char *str
)
129 get_option(&str
, &asidmask
);
139 smtc_asid_mask
= (unsigned long)asidmask
;
142 printk("ILLEGAL ASID mask 0x%x from command line\n", asidmask
);
147 __setup("vpe0tcs=", vpe0tcs
);
148 __setup("ipibufs=", ipibufs
);
149 __setup("nostlb", stlb_disable
);
150 __setup("asidmask=", asidmask_set
);
152 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
154 static int hang_trig
= 0;
156 static int __init
hangtrig_enable(char *s
)
163 __setup("hangtrig", hangtrig_enable
);
165 #define DEFAULT_BLOCKED_IPI_LIMIT 32
167 static int timerq_limit
= DEFAULT_BLOCKED_IPI_LIMIT
;
169 static int __init
tintq(char *str
)
171 get_option(&str
, &timerq_limit
);
175 __setup("tintq=", tintq
);
177 static int imstuckcount
[2][8];
178 /* vpemask represents IM/IE bits of per-VPE Status registers, low-to-high */
179 static int vpemask
[2][8] = {
180 {0, 0, 1, 0, 0, 0, 0, 1},
181 {0, 0, 0, 0, 0, 0, 0, 1}
183 int tcnoprog
[NR_CPUS
];
184 static atomic_t idle_hook_initialized
= {0};
185 static int clock_hang_reported
[NR_CPUS
];
187 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
190 * Configure shared TLB - VPC configuration bit must be set by caller
193 static void smtc_configure_tlb(void)
196 unsigned long mvpconf0
;
197 unsigned long config1val
;
199 /* Set up ASID preservation table */
200 for (vpes
=0; vpes
<MAX_SMTC_TLBS
; vpes
++) {
201 for(i
= 0; i
< MAX_SMTC_ASIDS
; i
++) {
202 smtc_live_asid
[vpes
][i
] = 0;
205 mvpconf0
= read_c0_mvpconf0();
207 if ((vpes
= ((mvpconf0
& MVPCONF0_PVPE
)
208 >> MVPCONF0_PVPE_SHIFT
) + 1) > 1) {
209 /* If we have multiple VPEs, try to share the TLB */
210 if ((mvpconf0
& MVPCONF0_TLBS
) && !nostlb
) {
212 * If TLB sizing is programmable, shared TLB
213 * size is the total available complement.
214 * Otherwise, we have to take the sum of all
215 * static VPE TLB entries.
217 if ((tlbsiz
= ((mvpconf0
& MVPCONF0_PTLBE
)
218 >> MVPCONF0_PTLBE_SHIFT
)) == 0) {
220 * If there's more than one VPE, there had better
221 * be more than one TC, because we need one to bind
222 * to each VPE in turn to be able to read
223 * its configuration state!
226 /* Stop the TC from doing anything foolish */
227 write_tc_c0_tchalt(TCHALT_H
);
229 /* No need to un-Halt - that happens later anyway */
230 for (i
=0; i
< vpes
; i
++) {
231 write_tc_c0_tcbind(i
);
233 * To be 100% sure we're really getting the right
234 * information, we exit the configuration state
235 * and do an IHB after each rebinding.
238 read_c0_mvpcontrol() & ~ MVPCONTROL_VPC
);
241 * Only count if the MMU Type indicated is TLB
243 if (((read_vpe_c0_config() & MIPS_CONF_MT
) >> 7) == 1) {
244 config1val
= read_vpe_c0_config1();
245 tlbsiz
+= ((config1val
>> 25) & 0x3f) + 1;
248 /* Put core back in configuration state */
250 read_c0_mvpcontrol() | MVPCONTROL_VPC
);
254 write_c0_mvpcontrol(read_c0_mvpcontrol() | MVPCONTROL_STLB
);
258 * Setup kernel data structures to use software total,
259 * rather than read the per-VPE Config1 value. The values
260 * for "CPU 0" gets copied to all the other CPUs as part
261 * of their initialization in smtc_cpu_setup().
264 /* MIPS32 limits TLB indices to 64 */
267 cpu_data
[0].tlbsize
= current_cpu_data
.tlbsize
= tlbsiz
;
268 smtc_status
|= SMTC_TLB_SHARED
;
269 local_flush_tlb_all();
271 printk("TLB of %d entry pairs shared by %d VPEs\n",
274 printk("WARNING: TLB Not Sharable on SMTC Boot!\n");
281 * Incrementally build the CPU map out of constituent MIPS MT cores,
282 * using the specified available VPEs and TCs. Plaform code needs
283 * to ensure that each MIPS MT core invokes this routine on reset,
286 * This version of the build_cpu_map and prepare_cpus routines assumes
287 * that *all* TCs of a MIPS MT core will be used for Linux, and that
288 * they will be spread across *all* available VPEs (to minimise the
289 * loss of efficiency due to exception service serialization).
290 * An improved version would pick up configuration information and
291 * possibly leave some TCs/VPEs as "slave" processors.
293 * Use c0_MVPConf0 to find out how many TCs are available, setting up
294 * cpu_possible_map and the logical/physical mappings.
297 int __init
smtc_build_cpu_map(int start_cpu_slot
)
302 * The CPU map isn't actually used for anything at this point,
303 * so it's not clear what else we should do apart from set
304 * everything up so that "logical" = "physical".
306 ntcs
= ((read_c0_mvpconf0() & MVPCONF0_PTC
) >> MVPCONF0_PTC_SHIFT
) + 1;
307 for (i
=start_cpu_slot
; i
<NR_CPUS
&& i
<ntcs
; i
++) {
308 cpu_set(i
, cpu_possible_map
);
309 __cpu_number_map
[i
] = i
;
310 __cpu_logical_map
[i
] = i
;
312 #ifdef CONFIG_MIPS_MT_FPAFF
313 /* Initialize map of CPUs with FPUs */
314 cpus_clear(mt_fpu_cpumask
);
317 /* One of those TC's is the one booting, and not a secondary... */
318 printk("%i available secondary CPU TC(s)\n", i
- 1);
324 * Common setup before any secondaries are started
325 * Make sure all CPU's are in a sensible state before we boot any of the
328 * For MIPS MT "SMTC" operation, we set up all TCs, spread as evenly
329 * as possible across the available VPEs.
332 static void smtc_tc_setup(int vpe
, int tc
, int cpu
)
335 write_tc_c0_tchalt(TCHALT_H
);
337 write_tc_c0_tcstatus((read_tc_c0_tcstatus()
338 & ~(TCSTATUS_TKSU
| TCSTATUS_DA
| TCSTATUS_IXMT
))
341 * TCContext gets an offset from the base of the IPIQ array
342 * to be used in low-level code to detect the presence of
343 * an active IPI queue
345 write_tc_c0_tccontext((sizeof(struct smtc_ipi_q
) * cpu
) << 16);
347 write_tc_c0_tcbind(vpe
);
348 /* In general, all TCs should have the same cpu_data indications */
349 memcpy(&cpu_data
[cpu
], &cpu_data
[0], sizeof(struct cpuinfo_mips
));
350 /* For 34Kf, start with TC/CPU 0 as sole owner of single FPU context */
351 if (cpu_data
[0].cputype
== CPU_34K
||
352 cpu_data
[0].cputype
== CPU_1004K
)
353 cpu_data
[cpu
].options
&= ~MIPS_CPU_FPU
;
354 cpu_data
[cpu
].vpe_id
= vpe
;
355 cpu_data
[cpu
].tc_id
= tc
;
356 /* Multi-core SMTC hasn't been tested, but be prepared */
357 cpu_data
[cpu
].core
= (read_vpe_c0_ebase() >> 1) & 0xff;
361 * Tweak to get Count registes in as close a sync as possible.
362 * Value seems good for 34K-class cores.
367 void smtc_prepare_cpus(int cpus
)
369 int i
, vpe
, tc
, ntc
, nvpe
, tcpervpe
[NR_CPUS
], slop
, cpu
;
373 struct smtc_ipi
*pipi
;
375 /* disable interrupts so we can disable MT */
376 local_irq_save(flags
);
377 /* disable MT so we can configure */
381 spin_lock_init(&freeIPIq
.lock
);
384 * We probably don't have as many VPEs as we do SMP "CPUs",
385 * but it's possible - and in any case we'll never use more!
387 for (i
=0; i
<NR_CPUS
; i
++) {
388 IPIQ
[i
].head
= IPIQ
[i
].tail
= NULL
;
389 spin_lock_init(&IPIQ
[i
].lock
);
393 /* cpu_data index starts at zero */
395 cpu_data
[cpu
].vpe_id
= 0;
396 cpu_data
[cpu
].tc_id
= 0;
397 cpu_data
[cpu
].core
= (read_c0_ebase() >> 1) & 0xff;
400 /* Report on boot-time options */
401 mips_mt_set_cpuoptions();
403 printk("Limit of %d VPEs set\n", vpelimit
);
405 printk("Limit of %d TCs set\n", tclimit
);
407 printk("Shared TLB Use Inhibited - UNSAFE for Multi-VPE Operation\n");
410 printk("ASID mask value override to 0x%x\n", asidmask
);
413 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
415 printk("Logic Analyser Trigger on suspected TC hang\n");
416 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
418 /* Put MVPE's into 'configuration state' */
419 write_c0_mvpcontrol( read_c0_mvpcontrol() | MVPCONTROL_VPC
);
421 val
= read_c0_mvpconf0();
422 nvpe
= ((val
& MVPCONF0_PVPE
) >> MVPCONF0_PVPE_SHIFT
) + 1;
423 if (vpelimit
> 0 && nvpe
> vpelimit
)
425 ntc
= ((val
& MVPCONF0_PTC
) >> MVPCONF0_PTC_SHIFT
) + 1;
428 if (tclimit
> 0 && ntc
> tclimit
)
431 for (i
= 0; i
< nvpe
; i
++) {
432 tcpervpe
[i
] = ntc
/ nvpe
;
434 if((slop
- i
) > 0) tcpervpe
[i
]++;
437 /* Handle command line override for VPE0 */
438 if (vpe0limit
> ntc
) vpe0limit
= ntc
;
441 if (vpe0limit
< tcpervpe
[0]) {
442 /* Reducing TC count - distribute to others */
443 slop
= tcpervpe
[0] - vpe0limit
;
444 slopslop
= slop
% (nvpe
- 1);
445 tcpervpe
[0] = vpe0limit
;
446 for (i
= 1; i
< nvpe
; i
++) {
447 tcpervpe
[i
] += slop
/ (nvpe
- 1);
448 if(slopslop
&& ((slopslop
- (i
- 1) > 0)))
451 } else if (vpe0limit
> tcpervpe
[0]) {
452 /* Increasing TC count - steal from others */
453 slop
= vpe0limit
- tcpervpe
[0];
454 slopslop
= slop
% (nvpe
- 1);
455 tcpervpe
[0] = vpe0limit
;
456 for (i
= 1; i
< nvpe
; i
++) {
457 tcpervpe
[i
] -= slop
/ (nvpe
- 1);
458 if(slopslop
&& ((slopslop
- (i
- 1) > 0)))
464 /* Set up shared TLB */
465 smtc_configure_tlb();
467 for (tc
= 0, vpe
= 0 ; (vpe
< nvpe
) && (tc
< ntc
) ; vpe
++) {
472 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_MVP
);
475 printk("VPE %d: TC", vpe
);
476 for (i
= 0; i
< tcpervpe
[vpe
]; i
++) {
478 * TC 0 is bound to VPE 0 at reset,
479 * and is presumably executing this
480 * code. Leave it alone!
483 smtc_tc_setup(vpe
, tc
, cpu
);
491 * Clear any stale software interrupts from VPE's Cause
493 write_vpe_c0_cause(0);
496 * Clear ERL/EXL of VPEs other than 0
497 * and set restricted interrupt enable/mask.
499 write_vpe_c0_status((read_vpe_c0_status()
500 & ~(ST0_BEV
| ST0_ERL
| ST0_EXL
| ST0_IM
))
501 | (STATUSF_IP0
| STATUSF_IP1
| STATUSF_IP7
504 * set config to be the same as vpe0,
505 * particularly kseg0 coherency alg
507 write_vpe_c0_config(read_c0_config());
508 /* Clear any pending timer interrupt */
509 write_vpe_c0_compare(0);
510 /* Propagate Config7 */
511 write_vpe_c0_config7(read_c0_config7());
512 write_vpe_c0_count(read_c0_count() + CP0_SKEW
);
515 /* enable multi-threading within VPE */
516 write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() | VPECONTROL_TE
);
518 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA
);
522 * Pull any physically present but unused TCs out of circulation.
524 while (tc
< (((val
& MVPCONF0_PTC
) >> MVPCONF0_PTC_SHIFT
) + 1)) {
525 cpu_clear(tc
, cpu_possible_map
);
526 cpu_clear(tc
, cpu_present_map
);
530 /* release config state */
531 write_c0_mvpcontrol( read_c0_mvpcontrol() & ~ MVPCONTROL_VPC
);
535 /* Set up coprocessor affinity CPU mask(s) */
537 #ifdef CONFIG_MIPS_MT_FPAFF
538 for (tc
= 0; tc
< ntc
; tc
++) {
539 if (cpu_data
[tc
].options
& MIPS_CPU_FPU
)
540 cpu_set(tc
, mt_fpu_cpumask
);
544 /* set up ipi interrupts... */
546 /* If we have multiple VPEs running, set up the cross-VPE interrupt */
548 setup_cross_vpe_interrupts(nvpe
);
550 /* Set up queue of free IPI "messages". */
551 nipi
= NR_CPUS
* IPIBUF_PER_CPU
;
555 pipi
= kmalloc(nipi
*sizeof(struct smtc_ipi
), GFP_KERNEL
);
557 panic("kmalloc of IPI message buffers failed\n");
559 printk("IPI buffer pool of %d buffers\n", nipi
);
560 for (i
= 0; i
< nipi
; i
++) {
561 smtc_ipi_nq(&freeIPIq
, pipi
);
565 /* Arm multithreading and enable other VPEs - but all TCs are Halted */
568 local_irq_restore(flags
);
569 /* Initialize SMTC /proc statistics/diagnostics */
575 * Setup the PC, SP, and GP of a secondary processor and start it
577 * smp_bootstrap is the place to resume from
578 * __KSTK_TOS(idle) is apparently the stack pointer
579 * (unsigned long)idle->thread_info the gp
582 void __cpuinit
smtc_boot_secondary(int cpu
, struct task_struct
*idle
)
584 extern u32 kernelsp
[NR_CPUS
];
589 if (cpu_data
[cpu
].vpe_id
!= cpu_data
[smp_processor_id()].vpe_id
) {
592 settc(cpu_data
[cpu
].tc_id
);
595 write_tc_c0_tcrestart((unsigned long)&smp_bootstrap
);
598 kernelsp
[cpu
] = __KSTK_TOS(idle
);
599 write_tc_gpr_sp(__KSTK_TOS(idle
));
602 write_tc_gpr_gp((unsigned long)task_thread_info(idle
));
604 smtc_status
|= SMTC_MTC_ACTIVE
;
605 write_tc_c0_tchalt(0);
606 if (cpu_data
[cpu
].vpe_id
!= cpu_data
[smp_processor_id()].vpe_id
) {
612 void smtc_init_secondary(void)
617 void smtc_smp_finish(void)
619 int cpu
= smp_processor_id();
622 * Lowest-numbered CPU per VPE starts a clock tick.
623 * Like per_cpu_trap_init() hack, this assumes that
624 * SMTC init code assigns TCs consdecutively and
625 * in ascending order across available VPEs.
627 if (cpu
> 0 && (cpu_data
[cpu
].vpe_id
!= cpu_data
[cpu
- 1].vpe_id
))
628 write_c0_compare(read_c0_count() + mips_hpt_frequency
/HZ
);
630 printk("TC %d going on-line as CPU %d\n",
631 cpu_data
[smp_processor_id()].tc_id
, smp_processor_id());
634 void smtc_cpus_done(void)
639 * Support for SMTC-optimized driver IRQ registration
643 * SMTC Kernel needs to manipulate low-level CPU interrupt mask
644 * in do_IRQ. These are passed in setup_irq_smtc() and stored
648 int setup_irq_smtc(unsigned int irq
, struct irqaction
* new,
649 unsigned long hwmask
)
651 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
652 unsigned int vpe
= current_cpu_data
.vpe_id
;
654 vpemask
[vpe
][irq
- MIPS_CPU_IRQ_BASE
] = 1;
656 irq_hwmask
[irq
] = hwmask
;
658 return setup_irq(irq
, new);
661 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
663 * Support for IRQ affinity to TCs
666 void smtc_set_irq_affinity(unsigned int irq
, cpumask_t affinity
)
669 * If a "fast path" cache of quickly decodable affinity state
670 * is maintained, this is where it gets done, on a call up
671 * from the platform affinity code.
675 void smtc_forward_irq(unsigned int irq
)
680 * OK wise guy, now figure out how to get the IRQ
681 * to be serviced on an authorized "CPU".
683 * Ideally, to handle the situation where an IRQ has multiple
684 * eligible CPUS, we would maintain state per IRQ that would
685 * allow a fair distribution of service requests. Since the
686 * expected use model is any-or-only-one, for simplicity
687 * and efficiency, we just pick the easiest one to find.
690 target
= cpumask_first(irq_desc
[irq
].affinity
);
693 * We depend on the platform code to have correctly processed
694 * IRQ affinity change requests to ensure that the IRQ affinity
695 * mask has been purged of bits corresponding to nonexistent and
696 * offline "CPUs", and to TCs bound to VPEs other than the VPE
697 * connected to the physical interrupt input for the interrupt
698 * in question. Otherwise we have a nasty problem with interrupt
699 * mask management. This is best handled in non-performance-critical
700 * platform IRQ affinity setting code, to minimize interrupt-time
704 /* If no one is eligible, service locally */
705 if (target
>= NR_CPUS
) {
706 do_IRQ_no_affinity(irq
);
710 smtc_send_ipi(target
, IRQ_AFFINITY_IPI
, irq
);
713 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
716 * IPI model for SMTC is tricky, because interrupts aren't TC-specific.
717 * Within a VPE one TC can interrupt another by different approaches.
718 * The easiest to get right would probably be to make all TCs except
719 * the target IXMT and set a software interrupt, but an IXMT-based
720 * scheme requires that a handler must run before a new IPI could
721 * be sent, which would break the "broadcast" loops in MIPS MT.
722 * A more gonzo approach within a VPE is to halt the TC, extract
723 * its Restart, Status, and a couple of GPRs, and program the Restart
724 * address to emulate an interrupt.
726 * Within a VPE, one can be confident that the target TC isn't in
727 * a critical EXL state when halted, since the write to the Halt
728 * register could not have issued on the writing thread if the
729 * halting thread had EXL set. So k0 and k1 of the target TC
730 * can be used by the injection code. Across VPEs, one can't
731 * be certain that the target TC isn't in a critical exception
732 * state. So we try a two-step process of sending a software
733 * interrupt to the target VPE, which either handles the event
734 * itself (if it was the target) or injects the event within
738 static void smtc_ipi_qdump(void)
742 for (i
= 0; i
< NR_CPUS
;i
++) {
743 printk("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n",
744 i
, (unsigned)IPIQ
[i
].head
, (unsigned)IPIQ
[i
].tail
,
750 * The standard atomic.h primitives don't quite do what we want
751 * here: We need an atomic add-and-return-previous-value (which
752 * could be done with atomic_add_return and a decrement) and an
753 * atomic set/zero-and-return-previous-value (which can't really
754 * be done with the atomic.h primitives). And since this is
755 * MIPS MT, we can assume that we have LL/SC.
757 static inline int atomic_postincrement(atomic_t
*v
)
759 unsigned long result
;
763 __asm__
__volatile__(
769 : "=&r" (result
), "=&r" (temp
), "=m" (v
->counter
)
776 void smtc_send_ipi(int cpu
, int type
, unsigned int action
)
779 struct smtc_ipi
*pipi
;
782 unsigned long tcrestart
;
783 extern void r4k_wait_irqoff(void), __pastwait(void);
785 if (cpu
== smp_processor_id()) {
786 printk("Cannot Send IPI to self!\n");
789 /* Set up a descriptor, to be delivered either promptly or queued */
790 pipi
= smtc_ipi_dq(&freeIPIq
);
793 mips_mt_regdump(dvpe());
794 panic("IPI Msg. Buffers Depleted\n");
797 pipi
->arg
= (void *)action
;
799 if (cpu_data
[cpu
].vpe_id
!= cpu_data
[smp_processor_id()].vpe_id
) {
800 /* If not on same VPE, enqueue and send cross-VPE interrupt */
801 smtc_ipi_nq(&IPIQ
[cpu
], pipi
);
803 settc(cpu_data
[cpu
].tc_id
);
804 write_vpe_c0_cause(read_vpe_c0_cause() | C_SW1
);
808 * Not sufficient to do a LOCK_MT_PRA (dmt) here,
809 * since ASID shootdown on the other VPE may
810 * collide with this operation.
813 settc(cpu_data
[cpu
].tc_id
);
814 /* Halt the targeted TC */
815 write_tc_c0_tchalt(TCHALT_H
);
819 * Inspect TCStatus - if IXMT is set, we have to queue
820 * a message. Otherwise, we set up the "interrupt"
823 tcstatus
= read_tc_c0_tcstatus();
825 if ((tcstatus
& TCSTATUS_IXMT
) != 0) {
827 * If we're in the the irq-off version of the wait
828 * loop, we need to force exit from the wait and
829 * do a direct post of the IPI.
831 if (cpu_wait
== r4k_wait_irqoff
) {
832 tcrestart
= read_tc_c0_tcrestart();
833 if (tcrestart
>= (unsigned long)r4k_wait_irqoff
834 && tcrestart
< (unsigned long)__pastwait
) {
835 write_tc_c0_tcrestart(__pastwait
);
836 tcstatus
&= ~TCSTATUS_IXMT
;
837 write_tc_c0_tcstatus(tcstatus
);
842 * Otherwise we queue the message for the target TC
843 * to pick up when he does a local_irq_restore()
845 write_tc_c0_tchalt(0);
847 smtc_ipi_nq(&IPIQ
[cpu
], pipi
);
850 post_direct_ipi(cpu
, pipi
);
851 write_tc_c0_tchalt(0);
858 * Send IPI message to Halted TC, TargTC/TargVPE already having been set
860 static void post_direct_ipi(int cpu
, struct smtc_ipi
*pipi
)
862 struct pt_regs
*kstack
;
863 unsigned long tcstatus
;
864 unsigned long tcrestart
;
865 extern u32 kernelsp
[NR_CPUS
];
866 extern void __smtc_ipi_vector(void);
867 //printk("%s: on %d for %d\n", __func__, smp_processor_id(), cpu);
869 /* Extract Status, EPC from halted TC */
870 tcstatus
= read_tc_c0_tcstatus();
871 tcrestart
= read_tc_c0_tcrestart();
872 /* If TCRestart indicates a WAIT instruction, advance the PC */
873 if ((tcrestart
& 0x80000000)
874 && ((*(unsigned int *)tcrestart
& 0xfe00003f) == 0x42000020)) {
878 * Save on TC's future kernel stack
880 * CU bit of Status is indicator that TC was
881 * already running on a kernel stack...
883 if (tcstatus
& ST0_CU0
) {
884 /* Note that this "- 1" is pointer arithmetic */
885 kstack
= ((struct pt_regs
*)read_tc_gpr_sp()) - 1;
887 kstack
= ((struct pt_regs
*)kernelsp
[cpu
]) - 1;
890 kstack
->cp0_epc
= (long)tcrestart
;
892 kstack
->cp0_tcstatus
= tcstatus
;
893 /* Pass token of operation to be performed kernel stack pad area */
894 kstack
->pad0
[4] = (unsigned long)pipi
;
895 /* Pass address of function to be called likewise */
896 kstack
->pad0
[5] = (unsigned long)&ipi_decode
;
897 /* Set interrupt exempt and kernel mode */
898 tcstatus
|= TCSTATUS_IXMT
;
899 tcstatus
&= ~TCSTATUS_TKSU
;
900 write_tc_c0_tcstatus(tcstatus
);
902 /* Set TC Restart address to be SMTC IPI vector */
903 write_tc_c0_tcrestart(__smtc_ipi_vector
);
906 static void ipi_resched_interrupt(void)
908 /* Return from interrupt should be enough to cause scheduler check */
911 static void ipi_call_interrupt(void)
913 /* Invoke generic function invocation code in smp.c */
914 smp_call_function_interrupt();
917 DECLARE_PER_CPU(struct clock_event_device
, mips_clockevent_device
);
919 void ipi_decode(struct smtc_ipi
*pipi
)
921 unsigned int cpu
= smp_processor_id();
922 struct clock_event_device
*cd
;
923 void *arg_copy
= pipi
->arg
;
924 int type_copy
= pipi
->type
;
925 int irq
= MIPS_CPU_IRQ_BASE
+ 1;
927 smtc_ipi_nq(&freeIPIq
, pipi
);
930 case SMTC_CLOCK_TICK
:
932 kstat_incr_irqs_this_cpu(irq
, irq_to_desc(irq
));
933 cd
= &per_cpu(mips_clockevent_device
, cpu
);
934 cd
->event_handler(cd
);
939 switch ((int)arg_copy
) {
940 case SMP_RESCHEDULE_YOURSELF
:
941 ipi_resched_interrupt();
943 case SMP_CALL_FUNCTION
:
944 ipi_call_interrupt();
947 printk("Impossible SMTC IPI Argument 0x%x\n",
952 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
953 case IRQ_AFFINITY_IPI
:
955 * Accept a "forwarded" interrupt that was initially
956 * taken by a TC who doesn't have affinity for the IRQ.
958 do_IRQ_no_affinity((int)arg_copy
);
960 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
962 printk("Impossible SMTC IPI Type 0x%x\n", type_copy
);
968 * Similar to smtc_ipi_replay(), but invoked from context restore,
969 * so it reuses the current exception frame rather than set up a
970 * new one with self_ipi.
973 void deferred_smtc_ipi(void)
975 int cpu
= smp_processor_id();
978 * Test is not atomic, but much faster than a dequeue,
979 * and the vast majority of invocations will have a null queue.
980 * If irq_disabled when this was called, then any IPIs queued
981 * after we test last will be taken on the next irq_enable/restore.
982 * If interrupts were enabled, then any IPIs added after the
983 * last test will be taken directly.
986 while (IPIQ
[cpu
].head
!= NULL
) {
987 struct smtc_ipi_q
*q
= &IPIQ
[cpu
];
988 struct smtc_ipi
*pipi
;
992 * It may be possible we'll come in with interrupts
995 local_irq_save(flags
);
998 pipi
= __smtc_ipi_dq(q
);
999 spin_unlock(&q
->lock
);
1003 * The use of the __raw_local restore isn't
1004 * as obviously necessary here as in smtc_ipi_replay(),
1005 * but it's more efficient, given that we're already
1006 * running down the IPI queue.
1008 __raw_local_irq_restore(flags
);
1013 * Cross-VPE interrupts in the SMTC prototype use "software interrupts"
1014 * set via cross-VPE MTTR manipulation of the Cause register. It would be
1015 * in some regards preferable to have external logic for "doorbell" hardware
1019 static int cpu_ipi_irq
= MIPS_CPU_IRQ_BASE
+ MIPS_CPU_IPI_IRQ
;
1021 static irqreturn_t
ipi_interrupt(int irq
, void *dev_idm
)
1023 int my_vpe
= cpu_data
[smp_processor_id()].vpe_id
;
1024 int my_tc
= cpu_data
[smp_processor_id()].tc_id
;
1026 struct smtc_ipi
*pipi
;
1027 unsigned long tcstatus
;
1029 unsigned long flags
;
1030 unsigned int mtflags
;
1031 unsigned int vpflags
;
1034 * So long as cross-VPE interrupts are done via
1035 * MFTR/MTTR read-modify-writes of Cause, we need
1036 * to stop other VPEs whenever the local VPE does
1039 local_irq_save(flags
);
1041 clear_c0_cause(0x100 << MIPS_CPU_IPI_IRQ
);
1042 set_c0_status(0x100 << MIPS_CPU_IPI_IRQ
);
1043 irq_enable_hazard();
1045 local_irq_restore(flags
);
1048 * Cross-VPE Interrupt handler: Try to directly deliver IPIs
1049 * queued for TCs on this VPE other than the current one.
1050 * Return-from-interrupt should cause us to drain the queue
1051 * for the current TC, so we ought not to have to do it explicitly here.
1054 for_each_online_cpu(cpu
) {
1055 if (cpu_data
[cpu
].vpe_id
!= my_vpe
)
1058 pipi
= smtc_ipi_dq(&IPIQ
[cpu
]);
1060 if (cpu_data
[cpu
].tc_id
!= my_tc
) {
1063 settc(cpu_data
[cpu
].tc_id
);
1064 write_tc_c0_tchalt(TCHALT_H
);
1066 tcstatus
= read_tc_c0_tcstatus();
1067 if ((tcstatus
& TCSTATUS_IXMT
) == 0) {
1068 post_direct_ipi(cpu
, pipi
);
1071 write_tc_c0_tchalt(0);
1074 smtc_ipi_req(&IPIQ
[cpu
], pipi
);
1078 * ipi_decode() should be called
1079 * with interrupts off
1081 local_irq_save(flags
);
1083 local_irq_restore(flags
);
1091 static void ipi_irq_dispatch(void)
1093 do_IRQ(cpu_ipi_irq
);
1096 static struct irqaction irq_ipi
= {
1097 .handler
= ipi_interrupt
,
1098 .flags
= IRQF_DISABLED
,
1100 .flags
= IRQF_PERCPU
1103 static void setup_cross_vpe_interrupts(unsigned int nvpe
)
1109 panic("SMTC Kernel requires Vectored Interrupt support");
1111 set_vi_handler(MIPS_CPU_IPI_IRQ
, ipi_irq_dispatch
);
1113 setup_irq_smtc(cpu_ipi_irq
, &irq_ipi
, (0x100 << MIPS_CPU_IPI_IRQ
));
1115 set_irq_handler(cpu_ipi_irq
, handle_percpu_irq
);
1119 * SMTC-specific hacks invoked from elsewhere in the kernel.
1123 * smtc_ipi_replay is called from raw_local_irq_restore
1126 void smtc_ipi_replay(void)
1128 unsigned int cpu
= smp_processor_id();
1131 * To the extent that we've ever turned interrupts off,
1132 * we may have accumulated deferred IPIs. This is subtle.
1133 * we should be OK: If we pick up something and dispatch
1134 * it here, that's great. If we see nothing, but concurrent
1135 * with this operation, another TC sends us an IPI, IXMT
1136 * is clear, and we'll handle it as a real pseudo-interrupt
1137 * and not a pseudo-pseudo interrupt. The important thing
1138 * is to do the last check for queued message *after* the
1139 * re-enabling of interrupts.
1141 while (IPIQ
[cpu
].head
!= NULL
) {
1142 struct smtc_ipi_q
*q
= &IPIQ
[cpu
];
1143 struct smtc_ipi
*pipi
;
1144 unsigned long flags
;
1147 * It's just possible we'll come in with interrupts
1150 local_irq_save(flags
);
1152 spin_lock(&q
->lock
);
1153 pipi
= __smtc_ipi_dq(q
);
1154 spin_unlock(&q
->lock
);
1156 ** But use a raw restore here to avoid recursion.
1158 __raw_local_irq_restore(flags
);
1162 smtc_cpu_stats
[cpu
].selfipis
++;
1167 EXPORT_SYMBOL(smtc_ipi_replay
);
1169 void smtc_idle_loop_hook(void)
1171 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
1180 * printk within DMT-protected regions can deadlock,
1181 * so buffer diagnostic messages for later output.
1184 char id_ho_db_msg
[768]; /* worst-case use should be less than 700 */
1186 if (atomic_read(&idle_hook_initialized
) == 0) { /* fast test */
1187 if (atomic_add_return(1, &idle_hook_initialized
) == 1) {
1189 /* Tedious stuff to just do once */
1190 mvpconf0
= read_c0_mvpconf0();
1191 hook_ntcs
= ((mvpconf0
& MVPCONF0_PTC
) >> MVPCONF0_PTC_SHIFT
) + 1;
1192 if (hook_ntcs
> NR_CPUS
)
1193 hook_ntcs
= NR_CPUS
;
1194 for (tc
= 0; tc
< hook_ntcs
; tc
++) {
1196 clock_hang_reported
[tc
] = 0;
1198 for (vpe
= 0; vpe
< 2; vpe
++)
1199 for (im
= 0; im
< 8; im
++)
1200 imstuckcount
[vpe
][im
] = 0;
1201 printk("Idle loop test hook initialized for %d TCs\n", hook_ntcs
);
1202 atomic_set(&idle_hook_initialized
, 1000);
1204 /* Someone else is initializing in parallel - let 'em finish */
1205 while (atomic_read(&idle_hook_initialized
) < 1000)
1210 /* Have we stupidly left IXMT set somewhere? */
1211 if (read_c0_tcstatus() & 0x400) {
1212 write_c0_tcstatus(read_c0_tcstatus() & ~0x400);
1214 printk("Dangling IXMT in cpu_idle()\n");
1217 /* Have we stupidly left an IM bit turned off? */
1218 #define IM_LIMIT 2000
1219 local_irq_save(flags
);
1221 pdb_msg
= &id_ho_db_msg
[0];
1222 im
= read_c0_status();
1223 vpe
= current_cpu_data
.vpe_id
;
1224 for (bit
= 0; bit
< 8; bit
++) {
1226 * In current prototype, I/O interrupts
1227 * are masked for VPE > 0
1229 if (vpemask
[vpe
][bit
]) {
1230 if (!(im
& (0x100 << bit
)))
1231 imstuckcount
[vpe
][bit
]++;
1233 imstuckcount
[vpe
][bit
] = 0;
1234 if (imstuckcount
[vpe
][bit
] > IM_LIMIT
) {
1235 set_c0_status(0x100 << bit
);
1237 imstuckcount
[vpe
][bit
] = 0;
1238 pdb_msg
+= sprintf(pdb_msg
,
1239 "Dangling IM %d fixed for VPE %d\n", bit
,
1246 local_irq_restore(flags
);
1247 if (pdb_msg
!= &id_ho_db_msg
[0])
1248 printk("CPU%d: %s", smp_processor_id(), id_ho_db_msg
);
1249 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
1254 void smtc_soft_dump(void)
1258 printk("Counter Interrupts taken per CPU (TC)\n");
1259 for (i
=0; i
< NR_CPUS
; i
++) {
1260 printk("%d: %ld\n", i
, smtc_cpu_stats
[i
].timerints
);
1262 printk("Self-IPI invocations:\n");
1263 for (i
=0; i
< NR_CPUS
; i
++) {
1264 printk("%d: %ld\n", i
, smtc_cpu_stats
[i
].selfipis
);
1267 printk("%d Recoveries of \"stolen\" FPU\n",
1268 atomic_read(&smtc_fpu_recoveries
));
1273 * TLB management routines special to SMTC
1276 void smtc_get_new_mmu_context(struct mm_struct
*mm
, unsigned long cpu
)
1278 unsigned long flags
, mtflags
, tcstat
, prevhalt
, asid
;
1282 * It would be nice to be able to use a spinlock here,
1283 * but this is invoked from within TLB flush routines
1284 * that protect themselves with DVPE, so if a lock is
1285 * held by another TC, it'll never be freed.
1287 * DVPE/DMT must not be done with interrupts enabled,
1288 * so even so most callers will already have disabled
1289 * them, let's be really careful...
1292 local_irq_save(flags
);
1293 if (smtc_status
& SMTC_TLB_SHARED
) {
1298 tlb
= cpu_data
[cpu
].vpe_id
;
1300 asid
= asid_cache(cpu
);
1303 if (!((asid
+= ASID_INC
) & ASID_MASK
) ) {
1304 if (cpu_has_vtag_icache
)
1306 /* Traverse all online CPUs (hack requires contigous range) */
1307 for_each_online_cpu(i
) {
1309 * We don't need to worry about our own CPU, nor those of
1310 * CPUs who don't share our TLB.
1312 if ((i
!= smp_processor_id()) &&
1313 ((smtc_status
& SMTC_TLB_SHARED
) ||
1314 (cpu_data
[i
].vpe_id
== cpu_data
[cpu
].vpe_id
))) {
1315 settc(cpu_data
[i
].tc_id
);
1316 prevhalt
= read_tc_c0_tchalt() & TCHALT_H
;
1318 write_tc_c0_tchalt(TCHALT_H
);
1321 tcstat
= read_tc_c0_tcstatus();
1322 smtc_live_asid
[tlb
][(tcstat
& ASID_MASK
)] |= (asiduse
)(0x1 << i
);
1324 write_tc_c0_tchalt(0);
1327 if (!asid
) /* fix version if needed */
1328 asid
= ASID_FIRST_VERSION
;
1329 local_flush_tlb_all(); /* start new asid cycle */
1331 } while (smtc_live_asid
[tlb
][(asid
& ASID_MASK
)]);
1334 * SMTC shares the TLB within VPEs and possibly across all VPEs.
1336 for_each_online_cpu(i
) {
1337 if ((smtc_status
& SMTC_TLB_SHARED
) ||
1338 (cpu_data
[i
].vpe_id
== cpu_data
[cpu
].vpe_id
))
1339 cpu_context(i
, mm
) = asid_cache(i
) = asid
;
1342 if (smtc_status
& SMTC_TLB_SHARED
)
1346 local_irq_restore(flags
);
1350 * Invoked from macros defined in mmu_context.h
1351 * which must already have disabled interrupts
1352 * and done a DVPE or DMT as appropriate.
1355 void smtc_flush_tlb_asid(unsigned long asid
)
1360 entry
= read_c0_wired();
1362 /* Traverse all non-wired entries */
1363 while (entry
< current_cpu_data
.tlbsize
) {
1364 write_c0_index(entry
);
1368 ehi
= read_c0_entryhi();
1369 if ((ehi
& ASID_MASK
) == asid
) {
1371 * Invalidate only entries with specified ASID,
1372 * makiing sure all entries differ.
1374 write_c0_entryhi(CKSEG0
+ (entry
<< (PAGE_SHIFT
+ 1)));
1375 write_c0_entrylo0(0);
1376 write_c0_entrylo1(0);
1378 tlb_write_indexed();
1382 write_c0_index(PARKED_INDEX
);
1387 * Support for single-threading cache flush operations.
1390 static int halt_state_save
[NR_CPUS
];
1393 * To really, really be sure that nothing is being done
1394 * by other TCs, halt them all. This code assumes that
1395 * a DVPE has already been done, so while their Halted
1396 * state is theoretically architecturally unstable, in
1397 * practice, it's not going to change while we're looking
1401 void smtc_cflush_lockdown(void)
1405 for_each_online_cpu(cpu
) {
1406 if (cpu
!= smp_processor_id()) {
1407 settc(cpu_data
[cpu
].tc_id
);
1408 halt_state_save
[cpu
] = read_tc_c0_tchalt();
1409 write_tc_c0_tchalt(TCHALT_H
);
1415 /* It would be cheating to change the cpu_online states during a flush! */
1417 void smtc_cflush_release(void)
1422 * Start with a hazard barrier to ensure
1423 * that all CACHE ops have played through.
1427 for_each_online_cpu(cpu
) {
1428 if (cpu
!= smp_processor_id()) {
1429 settc(cpu_data
[cpu
].tc_id
);
1430 write_tc_c0_tchalt(halt_state_save
[cpu
]);