arch/mips/kernel/time.c

   1 /*
   2  * Copyright 2001 MontaVista Software Inc.
   3  * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
   4  * Copyright (c) 2003, 2004  Maciej W. Rozycki
   5  *
   6  * Common time service routines for MIPS machines. See
   7  * Documentation/mips/time.README.
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  */
  14 #include <linux/clockchips.h>
  15 #include <linux/types.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/sched.h>
  19 #include <linux/param.h>
  20 #include <linux/profile.h>
  21 #include <linux/time.h>
  22 #include <linux/timex.h>
  23 #include <linux/smp.h>
  24 #include <linux/kernel_stat.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/module.h>
  28 #include <linux/kallsyms.h>
  29
  30 #include <asm/bootinfo.h>
  31 #include <asm/cache.h>
  32 #include <asm/compiler.h>
  33 #include <asm/cpu.h>
  34 #include <asm/cpu-features.h>
  35 #include <asm/div64.h>
  36 #include <asm/sections.h>
  37 #include <asm/smtc_ipi.h>
  38 #include <asm/time.h>
  39
  40 #include <irq.h>
  41
  42 /*
  43  * The integer part of the number of usecs per jiffy is taken from tick,
  44  * but the fractional part is not recorded, so we calculate it using the
  45  * initial value of HZ.  This aids systems where tick isn't really an
  46  * integer (e.g. for HZ = 128).
  47  */
  48 #define USECS_PER_JIFFY         TICK_SIZE
  49 #define USECS_PER_JIFFY_FRAC    ((unsigned long)(u32)((1000000ULL << 32) / HZ))
  50
  51 #define TICK_SIZE       (tick_nsec / 1000)
  52
  53 /*
  54  * forward reference
  55  */
  56 DEFINE_SPINLOCK(rtc_lock);
  57 EXPORT_SYMBOL(rtc_lock);
  58
  59 int __weak rtc_mips_set_time(unsigned long sec)
  60 {
  61         return 0;
  62 }
  63 EXPORT_SYMBOL(rtc_mips_set_time);
  64
  65 int __weak rtc_mips_set_mmss(unsigned long nowtime)
  66 {
  67         return rtc_mips_set_time(nowtime);
  68 }
  69
  70 int update_persistent_clock(struct timespec now)
  71 {
  72         return rtc_mips_set_mmss(now.tv_sec);
  73 }
  74
  75 /*
  76  * Null high precision timer functions for systems lacking one.
  77  */
  78 static cycle_t null_hpt_read(void)
  79 {
  80         return 0;
  81 }
  82
  83 /*
  84  * High precision timer functions for a R4k-compatible timer.
  85  */
  86 static cycle_t c0_hpt_read(void)
  87 {
  88         return read_c0_count();
  89 }
  90
  91 int (*mips_timer_state)(void);
  92
  93 /*
  94  * local_timer_interrupt() does profiling and process accounting
  95  * on a per-CPU basis.
  96  *
  97  * In UP mode, it is invoked from the (global) timer_interrupt.
  98  *
  99  * In SMP mode, it might invoked by per-CPU timer interrupt, or
 100  * a broadcasted inter-processor interrupt which itself is triggered
 101  * by the global timer interrupt.
 102  */
 103 void local_timer_interrupt(int irq, void *dev_id)
 104 {
 105         profile_tick(CPU_PROFILING);
 106         update_process_times(user_mode(get_irq_regs()));
 107 }
 108
 109 int null_perf_irq(void)
 110 {
 111         return 0;
 112 }
 113
 114 EXPORT_SYMBOL(null_perf_irq);
 115
 116 int (*perf_irq)(void) = null_perf_irq;
 117
 118 EXPORT_SYMBOL(perf_irq);
 119
 120 /*
 121  * time_init() - it does the following things.
 122  *
 123  * 1) plat_time_init() -
 124  *      a) (optional) set up RTC routines,
 125  *      b) (optional) calibrate and set the mips_hpt_frequency
 126  *          (only needed if you intended to use cpu counter as timer interrupt
 127  *           source)
 128  * 2) calculate a couple of cached variables for later usage
 129  * 3) plat_timer_setup() -
 130  *      a) (optional) over-write any choices made above by time_init().
 131  *      b) machine specific code should setup the timer irqaction.
 132  *      c) enable the timer interrupt
 133  */
 134
 135 unsigned int mips_hpt_frequency;
 136
 137 static unsigned int __init calibrate_hpt(void)
 138 {
 139         cycle_t frequency, hpt_start, hpt_end, hpt_count, hz;
 140
 141         const int loops = HZ / 10;
 142         int log_2_loops = 0;
 143         int i;
 144
 145         /*
 146          * We want to calibrate for 0.1s, but to avoid a 64-bit
 147          * division we round the number of loops up to the nearest
 148          * power of 2.
 149          */
 150         while (loops > 1 << log_2_loops)
 151                 log_2_loops++;
 152         i = 1 << log_2_loops;
 153
 154         /*
 155          * Wait for a rising edge of the timer interrupt.
 156          */
 157         while (mips_timer_state());
 158         while (!mips_timer_state());
 159
 160         /*
 161          * Now see how many high precision timer ticks happen
 162          * during the calculated number of periods between timer
 163          * interrupts.
 164          */
 165         hpt_start = clocksource_mips.read();
 166         do {
 167                 while (mips_timer_state());
 168                 while (!mips_timer_state());
 169         } while (--i);
 170         hpt_end = clocksource_mips.read();
 171
 172         hpt_count = (hpt_end - hpt_start) & clocksource_mips.mask;
 173         hz = HZ;
 174         frequency = hpt_count * hz;
 175
 176         return frequency >> log_2_loops;
 177 }
 178
 179 struct clocksource clocksource_mips = {
 180         .name           = "MIPS",
 181         .mask           = CLOCKSOURCE_MASK(32),
 182         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 183 };
 184
 185 static void __init init_mips_clocksource(void)
 186 {
 187         u64 temp;
 188         u32 shift;
 189
 190         if (!mips_hpt_frequency || clocksource_mips.read == null_hpt_read)
 191                 return;
 192
 193         /* Calclate a somewhat reasonable rating value */
 194         clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
 195         /* Find a shift value */
 196         for (shift = 32; shift > 0; shift--) {
 197                 temp = (u64) NSEC_PER_SEC << shift;
 198                 do_div(temp, mips_hpt_frequency);
 199                 if ((temp >> 32) == 0)
 200                         break;
 201         }
 202         clocksource_mips.shift = shift;
 203         clocksource_mips.mult = (u32)temp;
 204
 205         clocksource_register(&clocksource_mips);
 206 }
 207
 208 void __init __weak plat_time_init(void)
 209 {
 210 }
 211
 212 void __init __weak plat_timer_setup(struct irqaction *irq)
 213 {
 214 }
 215
 216 #ifdef CONFIG_MIPS_MT_SMTC
 217 DEFINE_PER_CPU(struct clock_event_device, smtc_dummy_clockevent_device);
 218
 219 static void smtc_set_mode(enum clock_event_mode mode,
 220                           struct clock_event_device *evt)
 221 {
 222 }
 223
 224 static void mips_broadcast(cpumask_t mask)
 225 {
 226         unsigned int cpu;
 227
 228         for_each_cpu_mask(cpu, mask)
 229                 smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0);
 230 }
 231
 232 static void setup_smtc_dummy_clockevent_device(void)
 233 {
 234         //uint64_t mips_freq = mips_hpt_^frequency;
 235         unsigned int cpu = smp_processor_id();
 236         struct clock_event_device *cd;
 237
 238         cd = &per_cpu(smtc_dummy_clockevent_device, cpu);
 239
 240         cd->name                = "SMTC";
 241         cd->features            = CLOCK_EVT_FEAT_DUMMY;
 242
 243         /* Calculate the min / max delta */
 244         cd->mult        = 0; //div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
 245         cd->shift               = 0; //32;
 246         cd->max_delta_ns        = 0; //clockevent_delta2ns(0x7fffffff, cd);
 247         cd->min_delta_ns        = 0; //clockevent_delta2ns(0x30, cd);
 248
 249         cd->rating              = 200;
 250         cd->irq                 = 17; //-1;
 251 //      if (cpu)
 252 //              cd->cpumask     = CPU_MASK_ALL; // cpumask_of_cpu(cpu);
 253 //      else
 254                 cd->cpumask     = cpumask_of_cpu(cpu);
 255
 256         cd->set_mode            = smtc_set_mode;
 257
 258         cd->broadcast           = mips_broadcast;
 259
 260         clockevents_register_device(cd);
 261 }
 262 #endif
 263
 264 void __init time_init(void)
 265 {
 266         plat_time_init();
 267
 268         /* Choose appropriate high precision timer routines.  */
 269         if (!cpu_has_counter && !clocksource_mips.read)
 270                 /* No high precision timer -- sorry.  */
 271                 clocksource_mips.read = null_hpt_read;
 272         else if (!mips_hpt_frequency && !mips_timer_state) {
 273                 /* A high precision timer of unknown frequency.  */
 274                 if (!clocksource_mips.read)
 275                         /* No external high precision timer -- use R4k.  */
 276                         clocksource_mips.read = c0_hpt_read;
 277         } else {
 278                 /* We know counter frequency.  Or we can get it.  */
 279                 if (!clocksource_mips.read) {
 280                         /* No external high precision timer -- use R4k.  */
 281                         clocksource_mips.read = c0_hpt_read;
 282                 }
 283                 if (!mips_hpt_frequency)
 284                         mips_hpt_frequency = calibrate_hpt();
 285
 286                 /* Report the high precision timer rate for a reference.  */
 287                 printk("Using %u.%03u MHz high precision timer.\n",
 288                        ((mips_hpt_frequency + 500) / 1000) / 1000,
 289                        ((mips_hpt_frequency + 500) / 1000) % 1000);
 290         }
 291
 292         init_mips_clocksource();
 293         mips_clockevent_init();
 294 }