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mm: add new mmgrab() helper
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1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
13 * Copyright (C) 2014, Imagination Technologies Ltd.
14 */
15 #include <linux/bitops.h>
16 #include <linux/bug.h>
17 #include <linux/compiler.h>
18 #include <linux/context_tracking.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/kexec.h>
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/extable.h>
25 #include <linux/mm.h>
26 #include <linux/sched.h>
27 #include <linux/smp.h>
28 #include <linux/spinlock.h>
29 #include <linux/kallsyms.h>
30 #include <linux/bootmem.h>
31 #include <linux/interrupt.h>
32 #include <linux/ptrace.h>
33 #include <linux/kgdb.h>
34 #include <linux/kdebug.h>
35 #include <linux/kprobes.h>
36 #include <linux/notifier.h>
37 #include <linux/kdb.h>
38 #include <linux/irq.h>
39 #include <linux/perf_event.h>
40
41 #include <asm/addrspace.h>
42 #include <asm/bootinfo.h>
43 #include <asm/branch.h>
44 #include <asm/break.h>
45 #include <asm/cop2.h>
46 #include <asm/cpu.h>
47 #include <asm/cpu-type.h>
48 #include <asm/dsp.h>
49 #include <asm/fpu.h>
50 #include <asm/fpu_emulator.h>
51 #include <asm/idle.h>
52 #include <asm/mips-cm.h>
53 #include <asm/mips-r2-to-r6-emul.h>
54 #include <asm/mips-cm.h>
55 #include <asm/mipsregs.h>
56 #include <asm/mipsmtregs.h>
57 #include <asm/module.h>
58 #include <asm/msa.h>
59 #include <asm/pgtable.h>
60 #include <asm/ptrace.h>
61 #include <asm/sections.h>
62 #include <asm/siginfo.h>
63 #include <asm/tlbdebug.h>
64 #include <asm/traps.h>
65 #include <linux/uaccess.h>
66 #include <asm/watch.h>
67 #include <asm/mmu_context.h>
68 #include <asm/types.h>
69 #include <asm/stacktrace.h>
70 #include <asm/uasm.h>
71
72 extern void check_wait(void);
73 extern asmlinkage void rollback_handle_int(void);
74 extern asmlinkage void handle_int(void);
75 extern u32 handle_tlbl[];
76 extern u32 handle_tlbs[];
77 extern u32 handle_tlbm[];
78 extern asmlinkage void handle_adel(void);
79 extern asmlinkage void handle_ades(void);
80 extern asmlinkage void handle_ibe(void);
81 extern asmlinkage void handle_dbe(void);
82 extern asmlinkage void handle_sys(void);
83 extern asmlinkage void handle_bp(void);
84 extern asmlinkage void handle_ri(void);
85 extern asmlinkage void handle_ri_rdhwr_vivt(void);
86 extern asmlinkage void handle_ri_rdhwr(void);
87 extern asmlinkage void handle_cpu(void);
88 extern asmlinkage void handle_ov(void);
89 extern asmlinkage void handle_tr(void);
90 extern asmlinkage void handle_msa_fpe(void);
91 extern asmlinkage void handle_fpe(void);
92 extern asmlinkage void handle_ftlb(void);
93 extern asmlinkage void handle_msa(void);
94 extern asmlinkage void handle_mdmx(void);
95 extern asmlinkage void handle_watch(void);
96 extern asmlinkage void handle_mt(void);
97 extern asmlinkage void handle_dsp(void);
98 extern asmlinkage void handle_mcheck(void);
99 extern asmlinkage void handle_reserved(void);
100 extern void tlb_do_page_fault_0(void);
101
102 void (*board_be_init)(void);
103 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
104 void (*board_nmi_handler_setup)(void);
105 void (*board_ejtag_handler_setup)(void);
106 void (*board_bind_eic_interrupt)(int irq, int regset);
107 void (*board_ebase_setup)(void);
108 void(*board_cache_error_setup)(void);
109
110 static void show_raw_backtrace(unsigned long reg29)
111 {
112 unsigned long *sp = (unsigned long *)(reg29 & ~3);
113 unsigned long addr;
114
115 printk("Call Trace:");
116 #ifdef CONFIG_KALLSYMS
117 printk("\n");
118 #endif
119 while (!kstack_end(sp)) {
120 unsigned long __user *p =
121 (unsigned long __user *)(unsigned long)sp++;
122 if (__get_user(addr, p)) {
123 printk(" (Bad stack address)");
124 break;
125 }
126 if (__kernel_text_address(addr))
127 print_ip_sym(addr);
128 }
129 printk("\n");
130 }
131
132 #ifdef CONFIG_KALLSYMS
133 int raw_show_trace;
134 static int __init set_raw_show_trace(char *str)
135 {
136 raw_show_trace = 1;
137 return 1;
138 }
139 __setup("raw_show_trace", set_raw_show_trace);
140 #endif
141
142 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
143 {
144 unsigned long sp = regs->regs[29];
145 unsigned long ra = regs->regs[31];
146 unsigned long pc = regs->cp0_epc;
147
148 if (!task)
149 task = current;
150
151 if (raw_show_trace || user_mode(regs) || !__kernel_text_address(pc)) {
152 show_raw_backtrace(sp);
153 return;
154 }
155 printk("Call Trace:\n");
156 do {
157 print_ip_sym(pc);
158 pc = unwind_stack(task, &sp, pc, &ra);
159 } while (pc);
160 pr_cont("\n");
161 }
162
163 /*
164 * This routine abuses get_user()/put_user() to reference pointers
165 * with at least a bit of error checking ...
166 */
167 static void show_stacktrace(struct task_struct *task,
168 const struct pt_regs *regs)
169 {
170 const int field = 2 * sizeof(unsigned long);
171 long stackdata;
172 int i;
173 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
174
175 printk("Stack :");
176 i = 0;
177 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
178 if (i && ((i % (64 / field)) == 0)) {
179 pr_cont("\n");
180 printk(" ");
181 }
182 if (i > 39) {
183 pr_cont(" ...");
184 break;
185 }
186
187 if (__get_user(stackdata, sp++)) {
188 pr_cont(" (Bad stack address)");
189 break;
190 }
191
192 pr_cont(" %0*lx", field, stackdata);
193 i++;
194 }
195 pr_cont("\n");
196 show_backtrace(task, regs);
197 }
198
199 void show_stack(struct task_struct *task, unsigned long *sp)
200 {
201 struct pt_regs regs;
202 mm_segment_t old_fs = get_fs();
203 if (sp) {
204 regs.regs[29] = (unsigned long)sp;
205 regs.regs[31] = 0;
206 regs.cp0_epc = 0;
207 } else {
208 if (task && task != current) {
209 regs.regs[29] = task->thread.reg29;
210 regs.regs[31] = 0;
211 regs.cp0_epc = task->thread.reg31;
212 #ifdef CONFIG_KGDB_KDB
213 } else if (atomic_read(&kgdb_active) != -1 &&
214 kdb_current_regs) {
215 memcpy(&regs, kdb_current_regs, sizeof(regs));
216 #endif /* CONFIG_KGDB_KDB */
217 } else {
218 prepare_frametrace(&regs);
219 }
220 }
221 /*
222 * show_stack() deals exclusively with kernel mode, so be sure to access
223 * the stack in the kernel (not user) address space.
224 */
225 set_fs(KERNEL_DS);
226 show_stacktrace(task, &regs);
227 set_fs(old_fs);
228 }
229
230 static void show_code(unsigned int __user *pc)
231 {
232 long i;
233 unsigned short __user *pc16 = NULL;
234
235 printk("Code:");
236
237 if ((unsigned long)pc & 1)
238 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
239 for(i = -3 ; i < 6 ; i++) {
240 unsigned int insn;
241 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
242 pr_cont(" (Bad address in epc)\n");
243 break;
244 }
245 pr_cont("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
246 }
247 pr_cont("\n");
248 }
249
250 static void __show_regs(const struct pt_regs *regs)
251 {
252 const int field = 2 * sizeof(unsigned long);
253 unsigned int cause = regs->cp0_cause;
254 unsigned int exccode;
255 int i;
256
257 show_regs_print_info(KERN_DEFAULT);
258
259 /*
260 * Saved main processor registers
261 */
262 for (i = 0; i < 32; ) {
263 if ((i % 4) == 0)
264 printk("$%2d :", i);
265 if (i == 0)
266 pr_cont(" %0*lx", field, 0UL);
267 else if (i == 26 || i == 27)
268 pr_cont(" %*s", field, "");
269 else
270 pr_cont(" %0*lx", field, regs->regs[i]);
271
272 i++;
273 if ((i % 4) == 0)
274 pr_cont("\n");
275 }
276
277 #ifdef CONFIG_CPU_HAS_SMARTMIPS
278 printk("Acx : %0*lx\n", field, regs->acx);
279 #endif
280 printk("Hi : %0*lx\n", field, regs->hi);
281 printk("Lo : %0*lx\n", field, regs->lo);
282
283 /*
284 * Saved cp0 registers
285 */
286 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
287 (void *) regs->cp0_epc);
288 printk("ra : %0*lx %pS\n", field, regs->regs[31],
289 (void *) regs->regs[31]);
290
291 printk("Status: %08x ", (uint32_t) regs->cp0_status);
292
293 if (cpu_has_3kex) {
294 if (regs->cp0_status & ST0_KUO)
295 pr_cont("KUo ");
296 if (regs->cp0_status & ST0_IEO)
297 pr_cont("IEo ");
298 if (regs->cp0_status & ST0_KUP)
299 pr_cont("KUp ");
300 if (regs->cp0_status & ST0_IEP)
301 pr_cont("IEp ");
302 if (regs->cp0_status & ST0_KUC)
303 pr_cont("KUc ");
304 if (regs->cp0_status & ST0_IEC)
305 pr_cont("IEc ");
306 } else if (cpu_has_4kex) {
307 if (regs->cp0_status & ST0_KX)
308 pr_cont("KX ");
309 if (regs->cp0_status & ST0_SX)
310 pr_cont("SX ");
311 if (regs->cp0_status & ST0_UX)
312 pr_cont("UX ");
313 switch (regs->cp0_status & ST0_KSU) {
314 case KSU_USER:
315 pr_cont("USER ");
316 break;
317 case KSU_SUPERVISOR:
318 pr_cont("SUPERVISOR ");
319 break;
320 case KSU_KERNEL:
321 pr_cont("KERNEL ");
322 break;
323 default:
324 pr_cont("BAD_MODE ");
325 break;
326 }
327 if (regs->cp0_status & ST0_ERL)
328 pr_cont("ERL ");
329 if (regs->cp0_status & ST0_EXL)
330 pr_cont("EXL ");
331 if (regs->cp0_status & ST0_IE)
332 pr_cont("IE ");
333 }
334 pr_cont("\n");
335
336 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
337 printk("Cause : %08x (ExcCode %02x)\n", cause, exccode);
338
339 if (1 <= exccode && exccode <= 5)
340 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
341
342 printk("PrId : %08x (%s)\n", read_c0_prid(),
343 cpu_name_string());
344 }
345
346 /*
347 * FIXME: really the generic show_regs should take a const pointer argument.
348 */
349 void show_regs(struct pt_regs *regs)
350 {
351 __show_regs((struct pt_regs *)regs);
352 }
353
354 void show_registers(struct pt_regs *regs)
355 {
356 const int field = 2 * sizeof(unsigned long);
357 mm_segment_t old_fs = get_fs();
358
359 __show_regs(regs);
360 print_modules();
361 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
362 current->comm, current->pid, current_thread_info(), current,
363 field, current_thread_info()->tp_value);
364 if (cpu_has_userlocal) {
365 unsigned long tls;
366
367 tls = read_c0_userlocal();
368 if (tls != current_thread_info()->tp_value)
369 printk("*HwTLS: %0*lx\n", field, tls);
370 }
371
372 if (!user_mode(regs))
373 /* Necessary for getting the correct stack content */
374 set_fs(KERNEL_DS);
375 show_stacktrace(current, regs);
376 show_code((unsigned int __user *) regs->cp0_epc);
377 printk("\n");
378 set_fs(old_fs);
379 }
380
381 static DEFINE_RAW_SPINLOCK(die_lock);
382
383 void __noreturn die(const char *str, struct pt_regs *regs)
384 {
385 static int die_counter;
386 int sig = SIGSEGV;
387
388 oops_enter();
389
390 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr,
391 SIGSEGV) == NOTIFY_STOP)
392 sig = 0;
393
394 console_verbose();
395 raw_spin_lock_irq(&die_lock);
396 bust_spinlocks(1);
397
398 printk("%s[#%d]:\n", str, ++die_counter);
399 show_registers(regs);
400 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
401 raw_spin_unlock_irq(&die_lock);
402
403 oops_exit();
404
405 if (in_interrupt())
406 panic("Fatal exception in interrupt");
407
408 if (panic_on_oops)
409 panic("Fatal exception");
410
411 if (regs && kexec_should_crash(current))
412 crash_kexec(regs);
413
414 do_exit(sig);
415 }
416
417 extern struct exception_table_entry __start___dbe_table[];
418 extern struct exception_table_entry __stop___dbe_table[];
419
420 __asm__(
421 " .section __dbe_table, \"a\"\n"
422 " .previous \n");
423
424 /* Given an address, look for it in the exception tables. */
425 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
426 {
427 const struct exception_table_entry *e;
428
429 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
430 if (!e)
431 e = search_module_dbetables(addr);
432 return e;
433 }
434
435 asmlinkage void do_be(struct pt_regs *regs)
436 {
437 const int field = 2 * sizeof(unsigned long);
438 const struct exception_table_entry *fixup = NULL;
439 int data = regs->cp0_cause & 4;
440 int action = MIPS_BE_FATAL;
441 enum ctx_state prev_state;
442
443 prev_state = exception_enter();
444 /* XXX For now. Fixme, this searches the wrong table ... */
445 if (data && !user_mode(regs))
446 fixup = search_dbe_tables(exception_epc(regs));
447
448 if (fixup)
449 action = MIPS_BE_FIXUP;
450
451 if (board_be_handler)
452 action = board_be_handler(regs, fixup != NULL);
453 else
454 mips_cm_error_report();
455
456 switch (action) {
457 case MIPS_BE_DISCARD:
458 goto out;
459 case MIPS_BE_FIXUP:
460 if (fixup) {
461 regs->cp0_epc = fixup->nextinsn;
462 goto out;
463 }
464 break;
465 default:
466 break;
467 }
468
469 /*
470 * Assume it would be too dangerous to continue ...
471 */
472 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
473 data ? "Data" : "Instruction",
474 field, regs->cp0_epc, field, regs->regs[31]);
475 if (notify_die(DIE_OOPS, "bus error", regs, 0, current->thread.trap_nr,
476 SIGBUS) == NOTIFY_STOP)
477 goto out;
478
479 die_if_kernel("Oops", regs);
480 force_sig(SIGBUS, current);
481
482 out:
483 exception_exit(prev_state);
484 }
485
486 /*
487 * ll/sc, rdhwr, sync emulation
488 */
489
490 #define OPCODE 0xfc000000
491 #define BASE 0x03e00000
492 #define RT 0x001f0000
493 #define OFFSET 0x0000ffff
494 #define LL 0xc0000000
495 #define SC 0xe0000000
496 #define SPEC0 0x00000000
497 #define SPEC3 0x7c000000
498 #define RD 0x0000f800
499 #define FUNC 0x0000003f
500 #define SYNC 0x0000000f
501 #define RDHWR 0x0000003b
502
503 /* microMIPS definitions */
504 #define MM_POOL32A_FUNC 0xfc00ffff
505 #define MM_RDHWR 0x00006b3c
506 #define MM_RS 0x001f0000
507 #define MM_RT 0x03e00000
508
509 /*
510 * The ll_bit is cleared by r*_switch.S
511 */
512
513 unsigned int ll_bit;
514 struct task_struct *ll_task;
515
516 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
517 {
518 unsigned long value, __user *vaddr;
519 long offset;
520
521 /*
522 * analyse the ll instruction that just caused a ri exception
523 * and put the referenced address to addr.
524 */
525
526 /* sign extend offset */
527 offset = opcode & OFFSET;
528 offset <<= 16;
529 offset >>= 16;
530
531 vaddr = (unsigned long __user *)
532 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
533
534 if ((unsigned long)vaddr & 3)
535 return SIGBUS;
536 if (get_user(value, vaddr))
537 return SIGSEGV;
538
539 preempt_disable();
540
541 if (ll_task == NULL || ll_task == current) {
542 ll_bit = 1;
543 } else {
544 ll_bit = 0;
545 }
546 ll_task = current;
547
548 preempt_enable();
549
550 regs->regs[(opcode & RT) >> 16] = value;
551
552 return 0;
553 }
554
555 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
556 {
557 unsigned long __user *vaddr;
558 unsigned long reg;
559 long offset;
560
561 /*
562 * analyse the sc instruction that just caused a ri exception
563 * and put the referenced address to addr.
564 */
565
566 /* sign extend offset */
567 offset = opcode & OFFSET;
568 offset <<= 16;
569 offset >>= 16;
570
571 vaddr = (unsigned long __user *)
572 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
573 reg = (opcode & RT) >> 16;
574
575 if ((unsigned long)vaddr & 3)
576 return SIGBUS;
577
578 preempt_disable();
579
580 if (ll_bit == 0 || ll_task != current) {
581 regs->regs[reg] = 0;
582 preempt_enable();
583 return 0;
584 }
585
586 preempt_enable();
587
588 if (put_user(regs->regs[reg], vaddr))
589 return SIGSEGV;
590
591 regs->regs[reg] = 1;
592
593 return 0;
594 }
595
596 /*
597 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
598 * opcodes are supposed to result in coprocessor unusable exceptions if
599 * executed on ll/sc-less processors. That's the theory. In practice a
600 * few processors such as NEC's VR4100 throw reserved instruction exceptions
601 * instead, so we're doing the emulation thing in both exception handlers.
602 */
603 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
604 {
605 if ((opcode & OPCODE) == LL) {
606 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
607 1, regs, 0);
608 return simulate_ll(regs, opcode);
609 }
610 if ((opcode & OPCODE) == SC) {
611 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
612 1, regs, 0);
613 return simulate_sc(regs, opcode);
614 }
615
616 return -1; /* Must be something else ... */
617 }
618
619 /*
620 * Simulate trapping 'rdhwr' instructions to provide user accessible
621 * registers not implemented in hardware.
622 */
623 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
624 {
625 struct thread_info *ti = task_thread_info(current);
626
627 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
628 1, regs, 0);
629 switch (rd) {
630 case MIPS_HWR_CPUNUM: /* CPU number */
631 regs->regs[rt] = smp_processor_id();
632 return 0;
633 case MIPS_HWR_SYNCISTEP: /* SYNCI length */
634 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
635 current_cpu_data.icache.linesz);
636 return 0;
637 case MIPS_HWR_CC: /* Read count register */
638 regs->regs[rt] = read_c0_count();
639 return 0;
640 case MIPS_HWR_CCRES: /* Count register resolution */
641 switch (current_cpu_type()) {
642 case CPU_20KC:
643 case CPU_25KF:
644 regs->regs[rt] = 1;
645 break;
646 default:
647 regs->regs[rt] = 2;
648 }
649 return 0;
650 case MIPS_HWR_ULR: /* Read UserLocal register */
651 regs->regs[rt] = ti->tp_value;
652 return 0;
653 default:
654 return -1;
655 }
656 }
657
658 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
659 {
660 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
661 int rd = (opcode & RD) >> 11;
662 int rt = (opcode & RT) >> 16;
663
664 simulate_rdhwr(regs, rd, rt);
665 return 0;
666 }
667
668 /* Not ours. */
669 return -1;
670 }
671
672 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode)
673 {
674 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
675 int rd = (opcode & MM_RS) >> 16;
676 int rt = (opcode & MM_RT) >> 21;
677 simulate_rdhwr(regs, rd, rt);
678 return 0;
679 }
680
681 /* Not ours. */
682 return -1;
683 }
684
685 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
686 {
687 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
688 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
689 1, regs, 0);
690 return 0;
691 }
692
693 return -1; /* Must be something else ... */
694 }
695
696 asmlinkage void do_ov(struct pt_regs *regs)
697 {
698 enum ctx_state prev_state;
699 siginfo_t info = {
700 .si_signo = SIGFPE,
701 .si_code = FPE_INTOVF,
702 .si_addr = (void __user *)regs->cp0_epc,
703 };
704
705 prev_state = exception_enter();
706 die_if_kernel("Integer overflow", regs);
707
708 force_sig_info(SIGFPE, &info, current);
709 exception_exit(prev_state);
710 }
711
712 /*
713 * Send SIGFPE according to FCSR Cause bits, which must have already
714 * been masked against Enable bits. This is impotant as Inexact can
715 * happen together with Overflow or Underflow, and `ptrace' can set
716 * any bits.
717 */
718 void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr,
719 struct task_struct *tsk)
720 {
721 struct siginfo si = { .si_addr = fault_addr, .si_signo = SIGFPE };
722
723 if (fcr31 & FPU_CSR_INV_X)
724 si.si_code = FPE_FLTINV;
725 else if (fcr31 & FPU_CSR_DIV_X)
726 si.si_code = FPE_FLTDIV;
727 else if (fcr31 & FPU_CSR_OVF_X)
728 si.si_code = FPE_FLTOVF;
729 else if (fcr31 & FPU_CSR_UDF_X)
730 si.si_code = FPE_FLTUND;
731 else if (fcr31 & FPU_CSR_INE_X)
732 si.si_code = FPE_FLTRES;
733 else
734 si.si_code = __SI_FAULT;
735 force_sig_info(SIGFPE, &si, tsk);
736 }
737
738 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31)
739 {
740 struct siginfo si = { 0 };
741 struct vm_area_struct *vma;
742
743 switch (sig) {
744 case 0:
745 return 0;
746
747 case SIGFPE:
748 force_fcr31_sig(fcr31, fault_addr, current);
749 return 1;
750
751 case SIGBUS:
752 si.si_addr = fault_addr;
753 si.si_signo = sig;
754 si.si_code = BUS_ADRERR;
755 force_sig_info(sig, &si, current);
756 return 1;
757
758 case SIGSEGV:
759 si.si_addr = fault_addr;
760 si.si_signo = sig;
761 down_read(&current->mm->mmap_sem);
762 vma = find_vma(current->mm, (unsigned long)fault_addr);
763 if (vma && (vma->vm_start <= (unsigned long)fault_addr))
764 si.si_code = SEGV_ACCERR;
765 else
766 si.si_code = SEGV_MAPERR;
767 up_read(&current->mm->mmap_sem);
768 force_sig_info(sig, &si, current);
769 return 1;
770
771 default:
772 force_sig(sig, current);
773 return 1;
774 }
775 }
776
777 static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
778 unsigned long old_epc, unsigned long old_ra)
779 {
780 union mips_instruction inst = { .word = opcode };
781 void __user *fault_addr;
782 unsigned long fcr31;
783 int sig;
784
785 /* If it's obviously not an FP instruction, skip it */
786 switch (inst.i_format.opcode) {
787 case cop1_op:
788 case cop1x_op:
789 case lwc1_op:
790 case ldc1_op:
791 case swc1_op:
792 case sdc1_op:
793 break;
794
795 default:
796 return -1;
797 }
798
799 /*
800 * do_ri skipped over the instruction via compute_return_epc, undo
801 * that for the FPU emulator.
802 */
803 regs->cp0_epc = old_epc;
804 regs->regs[31] = old_ra;
805
806 /* Save the FP context to struct thread_struct */
807 lose_fpu(1);
808
809 /* Run the emulator */
810 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
811 &fault_addr);
812
813 /*
814 * We can't allow the emulated instruction to leave any
815 * enabled Cause bits set in $fcr31.
816 */
817 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
818 current->thread.fpu.fcr31 &= ~fcr31;
819
820 /* Restore the hardware register state */
821 own_fpu(1);
822
823 /* Send a signal if required. */
824 process_fpemu_return(sig, fault_addr, fcr31);
825
826 return 0;
827 }
828
829 /*
830 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
831 */
832 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
833 {
834 enum ctx_state prev_state;
835 void __user *fault_addr;
836 int sig;
837
838 prev_state = exception_enter();
839 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr,
840 SIGFPE) == NOTIFY_STOP)
841 goto out;
842
843 /* Clear FCSR.Cause before enabling interrupts */
844 write_32bit_cp1_register(CP1_STATUS, fcr31 & ~mask_fcr31_x(fcr31));
845 local_irq_enable();
846
847 die_if_kernel("FP exception in kernel code", regs);
848
849 if (fcr31 & FPU_CSR_UNI_X) {
850 /*
851 * Unimplemented operation exception. If we've got the full
852 * software emulator on-board, let's use it...
853 *
854 * Force FPU to dump state into task/thread context. We're
855 * moving a lot of data here for what is probably a single
856 * instruction, but the alternative is to pre-decode the FP
857 * register operands before invoking the emulator, which seems
858 * a bit extreme for what should be an infrequent event.
859 */
860 /* Ensure 'resume' not overwrite saved fp context again. */
861 lose_fpu(1);
862
863 /* Run the emulator */
864 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
865 &fault_addr);
866
867 /*
868 * We can't allow the emulated instruction to leave any
869 * enabled Cause bits set in $fcr31.
870 */
871 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
872 current->thread.fpu.fcr31 &= ~fcr31;
873
874 /* Restore the hardware register state */
875 own_fpu(1); /* Using the FPU again. */
876 } else {
877 sig = SIGFPE;
878 fault_addr = (void __user *) regs->cp0_epc;
879 }
880
881 /* Send a signal if required. */
882 process_fpemu_return(sig, fault_addr, fcr31);
883
884 out:
885 exception_exit(prev_state);
886 }
887
888 void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code,
889 const char *str)
890 {
891 siginfo_t info = { 0 };
892 char b[40];
893
894 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
895 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, current->thread.trap_nr,
896 SIGTRAP) == NOTIFY_STOP)
897 return;
898 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
899
900 if (notify_die(DIE_TRAP, str, regs, code, current->thread.trap_nr,
901 SIGTRAP) == NOTIFY_STOP)
902 return;
903
904 /*
905 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
906 * insns, even for trap and break codes that indicate arithmetic
907 * failures. Weird ...
908 * But should we continue the brokenness??? --macro
909 */
910 switch (code) {
911 case BRK_OVERFLOW:
912 case BRK_DIVZERO:
913 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
914 die_if_kernel(b, regs);
915 if (code == BRK_DIVZERO)
916 info.si_code = FPE_INTDIV;
917 else
918 info.si_code = FPE_INTOVF;
919 info.si_signo = SIGFPE;
920 info.si_addr = (void __user *) regs->cp0_epc;
921 force_sig_info(SIGFPE, &info, current);
922 break;
923 case BRK_BUG:
924 die_if_kernel("Kernel bug detected", regs);
925 force_sig(SIGTRAP, current);
926 break;
927 case BRK_MEMU:
928 /*
929 * This breakpoint code is used by the FPU emulator to retake
930 * control of the CPU after executing the instruction from the
931 * delay slot of an emulated branch.
932 *
933 * Terminate if exception was recognized as a delay slot return
934 * otherwise handle as normal.
935 */
936 if (do_dsemulret(regs))
937 return;
938
939 die_if_kernel("Math emu break/trap", regs);
940 force_sig(SIGTRAP, current);
941 break;
942 default:
943 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
944 die_if_kernel(b, regs);
945 if (si_code) {
946 info.si_signo = SIGTRAP;
947 info.si_code = si_code;
948 force_sig_info(SIGTRAP, &info, current);
949 } else {
950 force_sig(SIGTRAP, current);
951 }
952 }
953 }
954
955 asmlinkage void do_bp(struct pt_regs *regs)
956 {
957 unsigned long epc = msk_isa16_mode(exception_epc(regs));
958 unsigned int opcode, bcode;
959 enum ctx_state prev_state;
960 mm_segment_t seg;
961
962 seg = get_fs();
963 if (!user_mode(regs))
964 set_fs(KERNEL_DS);
965
966 prev_state = exception_enter();
967 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
968 if (get_isa16_mode(regs->cp0_epc)) {
969 u16 instr[2];
970
971 if (__get_user(instr[0], (u16 __user *)epc))
972 goto out_sigsegv;
973
974 if (!cpu_has_mmips) {
975 /* MIPS16e mode */
976 bcode = (instr[0] >> 5) & 0x3f;
977 } else if (mm_insn_16bit(instr[0])) {
978 /* 16-bit microMIPS BREAK */
979 bcode = instr[0] & 0xf;
980 } else {
981 /* 32-bit microMIPS BREAK */
982 if (__get_user(instr[1], (u16 __user *)(epc + 2)))
983 goto out_sigsegv;
984 opcode = (instr[0] << 16) | instr[1];
985 bcode = (opcode >> 6) & ((1 << 20) - 1);
986 }
987 } else {
988 if (__get_user(opcode, (unsigned int __user *)epc))
989 goto out_sigsegv;
990 bcode = (opcode >> 6) & ((1 << 20) - 1);
991 }
992
993 /*
994 * There is the ancient bug in the MIPS assemblers that the break
995 * code starts left to bit 16 instead to bit 6 in the opcode.
996 * Gas is bug-compatible, but not always, grrr...
997 * We handle both cases with a simple heuristics. --macro
998 */
999 if (bcode >= (1 << 10))
1000 bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10);
1001
1002 /*
1003 * notify the kprobe handlers, if instruction is likely to
1004 * pertain to them.
1005 */
1006 switch (bcode) {
1007 case BRK_UPROBE:
1008 if (notify_die(DIE_UPROBE, "uprobe", regs, bcode,
1009 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1010 goto out;
1011 else
1012 break;
1013 case BRK_UPROBE_XOL:
1014 if (notify_die(DIE_UPROBE_XOL, "uprobe_xol", regs, bcode,
1015 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1016 goto out;
1017 else
1018 break;
1019 case BRK_KPROBE_BP:
1020 if (notify_die(DIE_BREAK, "debug", regs, bcode,
1021 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1022 goto out;
1023 else
1024 break;
1025 case BRK_KPROBE_SSTEPBP:
1026 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
1027 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1028 goto out;
1029 else
1030 break;
1031 default:
1032 break;
1033 }
1034
1035 do_trap_or_bp(regs, bcode, TRAP_BRKPT, "Break");
1036
1037 out:
1038 set_fs(seg);
1039 exception_exit(prev_state);
1040 return;
1041
1042 out_sigsegv:
1043 force_sig(SIGSEGV, current);
1044 goto out;
1045 }
1046
1047 asmlinkage void do_tr(struct pt_regs *regs)
1048 {
1049 u32 opcode, tcode = 0;
1050 enum ctx_state prev_state;
1051 u16 instr[2];
1052 mm_segment_t seg;
1053 unsigned long epc = msk_isa16_mode(exception_epc(regs));
1054
1055 seg = get_fs();
1056 if (!user_mode(regs))
1057 set_fs(get_ds());
1058
1059 prev_state = exception_enter();
1060 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1061 if (get_isa16_mode(regs->cp0_epc)) {
1062 if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
1063 __get_user(instr[1], (u16 __user *)(epc + 2)))
1064 goto out_sigsegv;
1065 opcode = (instr[0] << 16) | instr[1];
1066 /* Immediate versions don't provide a code. */
1067 if (!(opcode & OPCODE))
1068 tcode = (opcode >> 12) & ((1 << 4) - 1);
1069 } else {
1070 if (__get_user(opcode, (u32 __user *)epc))
1071 goto out_sigsegv;
1072 /* Immediate versions don't provide a code. */
1073 if (!(opcode & OPCODE))
1074 tcode = (opcode >> 6) & ((1 << 10) - 1);
1075 }
1076
1077 do_trap_or_bp(regs, tcode, 0, "Trap");
1078
1079 out:
1080 set_fs(seg);
1081 exception_exit(prev_state);
1082 return;
1083
1084 out_sigsegv:
1085 force_sig(SIGSEGV, current);
1086 goto out;
1087 }
1088
1089 asmlinkage void do_ri(struct pt_regs *regs)
1090 {
1091 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
1092 unsigned long old_epc = regs->cp0_epc;
1093 unsigned long old31 = regs->regs[31];
1094 enum ctx_state prev_state;
1095 unsigned int opcode = 0;
1096 int status = -1;
1097
1098 /*
1099 * Avoid any kernel code. Just emulate the R2 instruction
1100 * as quickly as possible.
1101 */
1102 if (mipsr2_emulation && cpu_has_mips_r6 &&
1103 likely(user_mode(regs)) &&
1104 likely(get_user(opcode, epc) >= 0)) {
1105 unsigned long fcr31 = 0;
1106
1107 status = mipsr2_decoder(regs, opcode, &fcr31);
1108 switch (status) {
1109 case 0:
1110 case SIGEMT:
1111 return;
1112 case SIGILL:
1113 goto no_r2_instr;
1114 default:
1115 process_fpemu_return(status,
1116 &current->thread.cp0_baduaddr,
1117 fcr31);
1118 return;
1119 }
1120 }
1121
1122 no_r2_instr:
1123
1124 prev_state = exception_enter();
1125 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1126
1127 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr,
1128 SIGILL) == NOTIFY_STOP)
1129 goto out;
1130
1131 die_if_kernel("Reserved instruction in kernel code", regs);
1132
1133 if (unlikely(compute_return_epc(regs) < 0))
1134 goto out;
1135
1136 if (!get_isa16_mode(regs->cp0_epc)) {
1137 if (unlikely(get_user(opcode, epc) < 0))
1138 status = SIGSEGV;
1139
1140 if (!cpu_has_llsc && status < 0)
1141 status = simulate_llsc(regs, opcode);
1142
1143 if (status < 0)
1144 status = simulate_rdhwr_normal(regs, opcode);
1145
1146 if (status < 0)
1147 status = simulate_sync(regs, opcode);
1148
1149 if (status < 0)
1150 status = simulate_fp(regs, opcode, old_epc, old31);
1151 } else if (cpu_has_mmips) {
1152 unsigned short mmop[2] = { 0 };
1153
1154 if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0))
1155 status = SIGSEGV;
1156 if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0))
1157 status = SIGSEGV;
1158 opcode = mmop[0];
1159 opcode = (opcode << 16) | mmop[1];
1160
1161 if (status < 0)
1162 status = simulate_rdhwr_mm(regs, opcode);
1163 }
1164
1165 if (status < 0)
1166 status = SIGILL;
1167
1168 if (unlikely(status > 0)) {
1169 regs->cp0_epc = old_epc; /* Undo skip-over. */
1170 regs->regs[31] = old31;
1171 force_sig(status, current);
1172 }
1173
1174 out:
1175 exception_exit(prev_state);
1176 }
1177
1178 /*
1179 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
1180 * emulated more than some threshold number of instructions, force migration to
1181 * a "CPU" that has FP support.
1182 */
1183 static void mt_ase_fp_affinity(void)
1184 {
1185 #ifdef CONFIG_MIPS_MT_FPAFF
1186 if (mt_fpemul_threshold > 0 &&
1187 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
1188 /*
1189 * If there's no FPU present, or if the application has already
1190 * restricted the allowed set to exclude any CPUs with FPUs,
1191 * we'll skip the procedure.
1192 */
1193 if (cpumask_intersects(&current->cpus_allowed, &mt_fpu_cpumask)) {
1194 cpumask_t tmask;
1195
1196 current->thread.user_cpus_allowed
1197 = current->cpus_allowed;
1198 cpumask_and(&tmask, &current->cpus_allowed,
1199 &mt_fpu_cpumask);
1200 set_cpus_allowed_ptr(current, &tmask);
1201 set_thread_flag(TIF_FPUBOUND);
1202 }
1203 }
1204 #endif /* CONFIG_MIPS_MT_FPAFF */
1205 }
1206
1207 /*
1208 * No lock; only written during early bootup by CPU 0.
1209 */
1210 static RAW_NOTIFIER_HEAD(cu2_chain);
1211
1212 int __ref register_cu2_notifier(struct notifier_block *nb)
1213 {
1214 return raw_notifier_chain_register(&cu2_chain, nb);
1215 }
1216
1217 int cu2_notifier_call_chain(unsigned long val, void *v)
1218 {
1219 return raw_notifier_call_chain(&cu2_chain, val, v);
1220 }
1221
1222 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
1223 void *data)
1224 {
1225 struct pt_regs *regs = data;
1226
1227 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
1228 "instruction", regs);
1229 force_sig(SIGILL, current);
1230
1231 return NOTIFY_OK;
1232 }
1233
1234 static int wait_on_fp_mode_switch(atomic_t *p)
1235 {
1236 /*
1237 * The FP mode for this task is currently being switched. That may
1238 * involve modifications to the format of this tasks FP context which
1239 * make it unsafe to proceed with execution for the moment. Instead,
1240 * schedule some other task.
1241 */
1242 schedule();
1243 return 0;
1244 }
1245
1246 static int enable_restore_fp_context(int msa)
1247 {
1248 int err, was_fpu_owner, prior_msa;
1249
1250 /*
1251 * If an FP mode switch is currently underway, wait for it to
1252 * complete before proceeding.
1253 */
1254 wait_on_atomic_t(&current->mm->context.fp_mode_switching,
1255 wait_on_fp_mode_switch, TASK_KILLABLE);
1256
1257 if (!used_math()) {
1258 /* First time FP context user. */
1259 preempt_disable();
1260 err = init_fpu();
1261 if (msa && !err) {
1262 enable_msa();
1263 init_msa_upper();
1264 set_thread_flag(TIF_USEDMSA);
1265 set_thread_flag(TIF_MSA_CTX_LIVE);
1266 }
1267 preempt_enable();
1268 if (!err)
1269 set_used_math();
1270 return err;
1271 }
1272
1273 /*
1274 * This task has formerly used the FP context.
1275 *
1276 * If this thread has no live MSA vector context then we can simply
1277 * restore the scalar FP context. If it has live MSA vector context
1278 * (that is, it has or may have used MSA since last performing a
1279 * function call) then we'll need to restore the vector context. This
1280 * applies even if we're currently only executing a scalar FP
1281 * instruction. This is because if we were to later execute an MSA
1282 * instruction then we'd either have to:
1283 *
1284 * - Restore the vector context & clobber any registers modified by
1285 * scalar FP instructions between now & then.
1286 *
1287 * or
1288 *
1289 * - Not restore the vector context & lose the most significant bits
1290 * of all vector registers.
1291 *
1292 * Neither of those options is acceptable. We cannot restore the least
1293 * significant bits of the registers now & only restore the most
1294 * significant bits later because the most significant bits of any
1295 * vector registers whose aliased FP register is modified now will have
1296 * been zeroed. We'd have no way to know that when restoring the vector
1297 * context & thus may load an outdated value for the most significant
1298 * bits of a vector register.
1299 */
1300 if (!msa && !thread_msa_context_live())
1301 return own_fpu(1);
1302
1303 /*
1304 * This task is using or has previously used MSA. Thus we require
1305 * that Status.FR == 1.
1306 */
1307 preempt_disable();
1308 was_fpu_owner = is_fpu_owner();
1309 err = own_fpu_inatomic(0);
1310 if (err)
1311 goto out;
1312
1313 enable_msa();
1314 write_msa_csr(current->thread.fpu.msacsr);
1315 set_thread_flag(TIF_USEDMSA);
1316
1317 /*
1318 * If this is the first time that the task is using MSA and it has
1319 * previously used scalar FP in this time slice then we already nave
1320 * FP context which we shouldn't clobber. We do however need to clear
1321 * the upper 64b of each vector register so that this task has no
1322 * opportunity to see data left behind by another.
1323 */
1324 prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE);
1325 if (!prior_msa && was_fpu_owner) {
1326 init_msa_upper();
1327
1328 goto out;
1329 }
1330
1331 if (!prior_msa) {
1332 /*
1333 * Restore the least significant 64b of each vector register
1334 * from the existing scalar FP context.
1335 */
1336 _restore_fp(current);
1337
1338 /*
1339 * The task has not formerly used MSA, so clear the upper 64b
1340 * of each vector register such that it cannot see data left
1341 * behind by another task.
1342 */
1343 init_msa_upper();
1344 } else {
1345 /* We need to restore the vector context. */
1346 restore_msa(current);
1347
1348 /* Restore the scalar FP control & status register */
1349 if (!was_fpu_owner)
1350 write_32bit_cp1_register(CP1_STATUS,
1351 current->thread.fpu.fcr31);
1352 }
1353
1354 out:
1355 preempt_enable();
1356
1357 return 0;
1358 }
1359
1360 asmlinkage void do_cpu(struct pt_regs *regs)
1361 {
1362 enum ctx_state prev_state;
1363 unsigned int __user *epc;
1364 unsigned long old_epc, old31;
1365 void __user *fault_addr;
1366 unsigned int opcode;
1367 unsigned long fcr31;
1368 unsigned int cpid;
1369 int status, err;
1370 int sig;
1371
1372 prev_state = exception_enter();
1373 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1374
1375 if (cpid != 2)
1376 die_if_kernel("do_cpu invoked from kernel context!", regs);
1377
1378 switch (cpid) {
1379 case 0:
1380 epc = (unsigned int __user *)exception_epc(regs);
1381 old_epc = regs->cp0_epc;
1382 old31 = regs->regs[31];
1383 opcode = 0;
1384 status = -1;
1385
1386 if (unlikely(compute_return_epc(regs) < 0))
1387 break;
1388
1389 if (!get_isa16_mode(regs->cp0_epc)) {
1390 if (unlikely(get_user(opcode, epc) < 0))
1391 status = SIGSEGV;
1392
1393 if (!cpu_has_llsc && status < 0)
1394 status = simulate_llsc(regs, opcode);
1395 }
1396
1397 if (status < 0)
1398 status = SIGILL;
1399
1400 if (unlikely(status > 0)) {
1401 regs->cp0_epc = old_epc; /* Undo skip-over. */
1402 regs->regs[31] = old31;
1403 force_sig(status, current);
1404 }
1405
1406 break;
1407
1408 case 3:
1409 /*
1410 * The COP3 opcode space and consequently the CP0.Status.CU3
1411 * bit and the CP0.Cause.CE=3 encoding have been removed as
1412 * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs
1413 * up the space has been reused for COP1X instructions, that
1414 * are enabled by the CP0.Status.CU1 bit and consequently
1415 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable
1416 * exceptions. Some FPU-less processors that implement one
1417 * of these ISAs however use this code erroneously for COP1X
1418 * instructions. Therefore we redirect this trap to the FP
1419 * emulator too.
1420 */
1421 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) {
1422 force_sig(SIGILL, current);
1423 break;
1424 }
1425 /* Fall through. */
1426
1427 case 1:
1428 err = enable_restore_fp_context(0);
1429
1430 if (raw_cpu_has_fpu && !err)
1431 break;
1432
1433 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 0,
1434 &fault_addr);
1435
1436 /*
1437 * We can't allow the emulated instruction to leave
1438 * any enabled Cause bits set in $fcr31.
1439 */
1440 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
1441 current->thread.fpu.fcr31 &= ~fcr31;
1442
1443 /* Send a signal if required. */
1444 if (!process_fpemu_return(sig, fault_addr, fcr31) && !err)
1445 mt_ase_fp_affinity();
1446
1447 break;
1448
1449 case 2:
1450 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1451 break;
1452 }
1453
1454 exception_exit(prev_state);
1455 }
1456
1457 asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr)
1458 {
1459 enum ctx_state prev_state;
1460
1461 prev_state = exception_enter();
1462 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1463 if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0,
1464 current->thread.trap_nr, SIGFPE) == NOTIFY_STOP)
1465 goto out;
1466
1467 /* Clear MSACSR.Cause before enabling interrupts */
1468 write_msa_csr(msacsr & ~MSA_CSR_CAUSEF);
1469 local_irq_enable();
1470
1471 die_if_kernel("do_msa_fpe invoked from kernel context!", regs);
1472 force_sig(SIGFPE, current);
1473 out:
1474 exception_exit(prev_state);
1475 }
1476
1477 asmlinkage void do_msa(struct pt_regs *regs)
1478 {
1479 enum ctx_state prev_state;
1480 int err;
1481
1482 prev_state = exception_enter();
1483
1484 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) {
1485 force_sig(SIGILL, current);
1486 goto out;
1487 }
1488
1489 die_if_kernel("do_msa invoked from kernel context!", regs);
1490
1491 err = enable_restore_fp_context(1);
1492 if (err)
1493 force_sig(SIGILL, current);
1494 out:
1495 exception_exit(prev_state);
1496 }
1497
1498 asmlinkage void do_mdmx(struct pt_regs *regs)
1499 {
1500 enum ctx_state prev_state;
1501
1502 prev_state = exception_enter();
1503 force_sig(SIGILL, current);
1504 exception_exit(prev_state);
1505 }
1506
1507 /*
1508 * Called with interrupts disabled.
1509 */
1510 asmlinkage void do_watch(struct pt_regs *regs)
1511 {
1512 siginfo_t info = { .si_signo = SIGTRAP, .si_code = TRAP_HWBKPT };
1513 enum ctx_state prev_state;
1514
1515 prev_state = exception_enter();
1516 /*
1517 * Clear WP (bit 22) bit of cause register so we don't loop
1518 * forever.
1519 */
1520 clear_c0_cause(CAUSEF_WP);
1521
1522 /*
1523 * If the current thread has the watch registers loaded, save
1524 * their values and send SIGTRAP. Otherwise another thread
1525 * left the registers set, clear them and continue.
1526 */
1527 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1528 mips_read_watch_registers();
1529 local_irq_enable();
1530 force_sig_info(SIGTRAP, &info, current);
1531 } else {
1532 mips_clear_watch_registers();
1533 local_irq_enable();
1534 }
1535 exception_exit(prev_state);
1536 }
1537
1538 asmlinkage void do_mcheck(struct pt_regs *regs)
1539 {
1540 int multi_match = regs->cp0_status & ST0_TS;
1541 enum ctx_state prev_state;
1542 mm_segment_t old_fs = get_fs();
1543
1544 prev_state = exception_enter();
1545 show_regs(regs);
1546
1547 if (multi_match) {
1548 dump_tlb_regs();
1549 pr_info("\n");
1550 dump_tlb_all();
1551 }
1552
1553 if (!user_mode(regs))
1554 set_fs(KERNEL_DS);
1555
1556 show_code((unsigned int __user *) regs->cp0_epc);
1557
1558 set_fs(old_fs);
1559
1560 /*
1561 * Some chips may have other causes of machine check (e.g. SB1
1562 * graduation timer)
1563 */
1564 panic("Caught Machine Check exception - %scaused by multiple "
1565 "matching entries in the TLB.",
1566 (multi_match) ? "" : "not ");
1567 }
1568
1569 asmlinkage void do_mt(struct pt_regs *regs)
1570 {
1571 int subcode;
1572
1573 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1574 >> VPECONTROL_EXCPT_SHIFT;
1575 switch (subcode) {
1576 case 0:
1577 printk(KERN_DEBUG "Thread Underflow\n");
1578 break;
1579 case 1:
1580 printk(KERN_DEBUG "Thread Overflow\n");
1581 break;
1582 case 2:
1583 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1584 break;
1585 case 3:
1586 printk(KERN_DEBUG "Gating Storage Exception\n");
1587 break;
1588 case 4:
1589 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1590 break;
1591 case 5:
1592 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
1593 break;
1594 default:
1595 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1596 subcode);
1597 break;
1598 }
1599 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1600
1601 force_sig(SIGILL, current);
1602 }
1603
1604
1605 asmlinkage void do_dsp(struct pt_regs *regs)
1606 {
1607 if (cpu_has_dsp)
1608 panic("Unexpected DSP exception");
1609
1610 force_sig(SIGILL, current);
1611 }
1612
1613 asmlinkage void do_reserved(struct pt_regs *regs)
1614 {
1615 /*
1616 * Game over - no way to handle this if it ever occurs. Most probably
1617 * caused by a new unknown cpu type or after another deadly
1618 * hard/software error.
1619 */
1620 show_regs(regs);
1621 panic("Caught reserved exception %ld - should not happen.",
1622 (regs->cp0_cause & 0x7f) >> 2);
1623 }
1624
1625 static int __initdata l1parity = 1;
1626 static int __init nol1parity(char *s)
1627 {
1628 l1parity = 0;
1629 return 1;
1630 }
1631 __setup("nol1par", nol1parity);
1632 static int __initdata l2parity = 1;
1633 static int __init nol2parity(char *s)
1634 {
1635 l2parity = 0;
1636 return 1;
1637 }
1638 __setup("nol2par", nol2parity);
1639
1640 /*
1641 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1642 * it different ways.
1643 */
1644 static inline void parity_protection_init(void)
1645 {
1646 #define ERRCTL_PE 0x80000000
1647 #define ERRCTL_L2P 0x00800000
1648
1649 if (mips_cm_revision() >= CM_REV_CM3) {
1650 ulong gcr_ectl, cp0_ectl;
1651
1652 /*
1653 * With CM3 systems we need to ensure that the L1 & L2
1654 * parity enables are set to the same value, since this
1655 * is presumed by the hardware engineers.
1656 *
1657 * If the user disabled either of L1 or L2 ECC checking,
1658 * disable both.
1659 */
1660 l1parity &= l2parity;
1661 l2parity &= l1parity;
1662
1663 /* Probe L1 ECC support */
1664 cp0_ectl = read_c0_ecc();
1665 write_c0_ecc(cp0_ectl | ERRCTL_PE);
1666 back_to_back_c0_hazard();
1667 cp0_ectl = read_c0_ecc();
1668
1669 /* Probe L2 ECC support */
1670 gcr_ectl = read_gcr_err_control();
1671
1672 if (!(gcr_ectl & CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT_MSK) ||
1673 !(cp0_ectl & ERRCTL_PE)) {
1674 /*
1675 * One of L1 or L2 ECC checking isn't supported,
1676 * so we cannot enable either.
1677 */
1678 l1parity = l2parity = 0;
1679 }
1680
1681 /* Configure L1 ECC checking */
1682 if (l1parity)
1683 cp0_ectl |= ERRCTL_PE;
1684 else
1685 cp0_ectl &= ~ERRCTL_PE;
1686 write_c0_ecc(cp0_ectl);
1687 back_to_back_c0_hazard();
1688 WARN_ON(!!(read_c0_ecc() & ERRCTL_PE) != l1parity);
1689
1690 /* Configure L2 ECC checking */
1691 if (l2parity)
1692 gcr_ectl |= CM_GCR_ERR_CONTROL_L2_ECC_EN_MSK;
1693 else
1694 gcr_ectl &= ~CM_GCR_ERR_CONTROL_L2_ECC_EN_MSK;
1695 write_gcr_err_control(gcr_ectl);
1696 gcr_ectl = read_gcr_err_control();
1697 gcr_ectl &= CM_GCR_ERR_CONTROL_L2_ECC_EN_MSK;
1698 WARN_ON(!!gcr_ectl != l2parity);
1699
1700 pr_info("Cache parity protection %sabled\n",
1701 l1parity ? "en" : "dis");
1702 return;
1703 }
1704
1705 switch (current_cpu_type()) {
1706 case CPU_24K:
1707 case CPU_34K:
1708 case CPU_74K:
1709 case CPU_1004K:
1710 case CPU_1074K:
1711 case CPU_INTERAPTIV:
1712 case CPU_PROAPTIV:
1713 case CPU_P5600:
1714 case CPU_QEMU_GENERIC:
1715 case CPU_P6600:
1716 {
1717 unsigned long errctl;
1718 unsigned int l1parity_present, l2parity_present;
1719
1720 errctl = read_c0_ecc();
1721 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1722
1723 /* probe L1 parity support */
1724 write_c0_ecc(errctl | ERRCTL_PE);
1725 back_to_back_c0_hazard();
1726 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1727
1728 /* probe L2 parity support */
1729 write_c0_ecc(errctl|ERRCTL_L2P);
1730 back_to_back_c0_hazard();
1731 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1732
1733 if (l1parity_present && l2parity_present) {
1734 if (l1parity)
1735 errctl |= ERRCTL_PE;
1736 if (l1parity ^ l2parity)
1737 errctl |= ERRCTL_L2P;
1738 } else if (l1parity_present) {
1739 if (l1parity)
1740 errctl |= ERRCTL_PE;
1741 } else if (l2parity_present) {
1742 if (l2parity)
1743 errctl |= ERRCTL_L2P;
1744 } else {
1745 /* No parity available */
1746 }
1747
1748 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1749
1750 write_c0_ecc(errctl);
1751 back_to_back_c0_hazard();
1752 errctl = read_c0_ecc();
1753 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1754
1755 if (l1parity_present)
1756 printk(KERN_INFO "Cache parity protection %sabled\n",
1757 (errctl & ERRCTL_PE) ? "en" : "dis");
1758
1759 if (l2parity_present) {
1760 if (l1parity_present && l1parity)
1761 errctl ^= ERRCTL_L2P;
1762 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1763 (errctl & ERRCTL_L2P) ? "en" : "dis");
1764 }
1765 }
1766 break;
1767
1768 case CPU_5KC:
1769 case CPU_5KE:
1770 case CPU_LOONGSON1:
1771 write_c0_ecc(0x80000000);
1772 back_to_back_c0_hazard();
1773 /* Set the PE bit (bit 31) in the c0_errctl register. */
1774 printk(KERN_INFO "Cache parity protection %sabled\n",
1775 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1776 break;
1777 case CPU_20KC:
1778 case CPU_25KF:
1779 /* Clear the DE bit (bit 16) in the c0_status register. */
1780 printk(KERN_INFO "Enable cache parity protection for "
1781 "MIPS 20KC/25KF CPUs.\n");
1782 clear_c0_status(ST0_DE);
1783 break;
1784 default:
1785 break;
1786 }
1787 }
1788
1789 asmlinkage void cache_parity_error(void)
1790 {
1791 const int field = 2 * sizeof(unsigned long);
1792 unsigned int reg_val;
1793
1794 /* For the moment, report the problem and hang. */
1795 printk("Cache error exception:\n");
1796 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1797 reg_val = read_c0_cacheerr();
1798 printk("c0_cacheerr == %08x\n", reg_val);
1799
1800 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1801 reg_val & (1<<30) ? "secondary" : "primary",
1802 reg_val & (1<<31) ? "data" : "insn");
1803 if ((cpu_has_mips_r2_r6) &&
1804 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1805 pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1806 reg_val & (1<<29) ? "ED " : "",
1807 reg_val & (1<<28) ? "ET " : "",
1808 reg_val & (1<<27) ? "ES " : "",
1809 reg_val & (1<<26) ? "EE " : "",
1810 reg_val & (1<<25) ? "EB " : "",
1811 reg_val & (1<<24) ? "EI " : "",
1812 reg_val & (1<<23) ? "E1 " : "",
1813 reg_val & (1<<22) ? "E0 " : "");
1814 } else {
1815 pr_err("Error bits: %s%s%s%s%s%s%s\n",
1816 reg_val & (1<<29) ? "ED " : "",
1817 reg_val & (1<<28) ? "ET " : "",
1818 reg_val & (1<<26) ? "EE " : "",
1819 reg_val & (1<<25) ? "EB " : "",
1820 reg_val & (1<<24) ? "EI " : "",
1821 reg_val & (1<<23) ? "E1 " : "",
1822 reg_val & (1<<22) ? "E0 " : "");
1823 }
1824 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1825
1826 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1827 if (reg_val & (1<<22))
1828 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1829
1830 if (reg_val & (1<<23))
1831 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1832 #endif
1833
1834 panic("Can't handle the cache error!");
1835 }
1836
1837 asmlinkage void do_ftlb(void)
1838 {
1839 const int field = 2 * sizeof(unsigned long);
1840 unsigned int reg_val;
1841
1842 /* For the moment, report the problem and hang. */
1843 if ((cpu_has_mips_r2_r6) &&
1844 (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) ||
1845 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) {
1846 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1847 read_c0_ecc());
1848 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1849 reg_val = read_c0_cacheerr();
1850 pr_err("c0_cacheerr == %08x\n", reg_val);
1851
1852 if ((reg_val & 0xc0000000) == 0xc0000000) {
1853 pr_err("Decoded c0_cacheerr: FTLB parity error\n");
1854 } else {
1855 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1856 reg_val & (1<<30) ? "secondary" : "primary",
1857 reg_val & (1<<31) ? "data" : "insn");
1858 }
1859 } else {
1860 pr_err("FTLB error exception\n");
1861 }
1862 /* Just print the cacheerr bits for now */
1863 cache_parity_error();
1864 }
1865
1866 /*
1867 * SDBBP EJTAG debug exception handler.
1868 * We skip the instruction and return to the next instruction.
1869 */
1870 void ejtag_exception_handler(struct pt_regs *regs)
1871 {
1872 const int field = 2 * sizeof(unsigned long);
1873 unsigned long depc, old_epc, old_ra;
1874 unsigned int debug;
1875
1876 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1877 depc = read_c0_depc();
1878 debug = read_c0_debug();
1879 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1880 if (debug & 0x80000000) {
1881 /*
1882 * In branch delay slot.
1883 * We cheat a little bit here and use EPC to calculate the
1884 * debug return address (DEPC). EPC is restored after the
1885 * calculation.
1886 */
1887 old_epc = regs->cp0_epc;
1888 old_ra = regs->regs[31];
1889 regs->cp0_epc = depc;
1890 compute_return_epc(regs);
1891 depc = regs->cp0_epc;
1892 regs->cp0_epc = old_epc;
1893 regs->regs[31] = old_ra;
1894 } else
1895 depc += 4;
1896 write_c0_depc(depc);
1897
1898 #if 0
1899 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1900 write_c0_debug(debug | 0x100);
1901 #endif
1902 }
1903
1904 /*
1905 * NMI exception handler.
1906 * No lock; only written during early bootup by CPU 0.
1907 */
1908 static RAW_NOTIFIER_HEAD(nmi_chain);
1909
1910 int register_nmi_notifier(struct notifier_block *nb)
1911 {
1912 return raw_notifier_chain_register(&nmi_chain, nb);
1913 }
1914
1915 void __noreturn nmi_exception_handler(struct pt_regs *regs)
1916 {
1917 char str[100];
1918
1919 nmi_enter();
1920 raw_notifier_call_chain(&nmi_chain, 0, regs);
1921 bust_spinlocks(1);
1922 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1923 smp_processor_id(), regs->cp0_epc);
1924 regs->cp0_epc = read_c0_errorepc();
1925 die(str, regs);
1926 nmi_exit();
1927 }
1928
1929 #define VECTORSPACING 0x100 /* for EI/VI mode */
1930
1931 unsigned long ebase;
1932 EXPORT_SYMBOL_GPL(ebase);
1933 unsigned long exception_handlers[32];
1934 unsigned long vi_handlers[64];
1935
1936 void __init *set_except_vector(int n, void *addr)
1937 {
1938 unsigned long handler = (unsigned long) addr;
1939 unsigned long old_handler;
1940
1941 #ifdef CONFIG_CPU_MICROMIPS
1942 /*
1943 * Only the TLB handlers are cache aligned with an even
1944 * address. All other handlers are on an odd address and
1945 * require no modification. Otherwise, MIPS32 mode will
1946 * be entered when handling any TLB exceptions. That
1947 * would be bad...since we must stay in microMIPS mode.
1948 */
1949 if (!(handler & 0x1))
1950 handler |= 1;
1951 #endif
1952 old_handler = xchg(&exception_handlers[n], handler);
1953
1954 if (n == 0 && cpu_has_divec) {
1955 #ifdef CONFIG_CPU_MICROMIPS
1956 unsigned long jump_mask = ~((1 << 27) - 1);
1957 #else
1958 unsigned long jump_mask = ~((1 << 28) - 1);
1959 #endif
1960 u32 *buf = (u32 *)(ebase + 0x200);
1961 unsigned int k0 = 26;
1962 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1963 uasm_i_j(&buf, handler & ~jump_mask);
1964 uasm_i_nop(&buf);
1965 } else {
1966 UASM_i_LA(&buf, k0, handler);
1967 uasm_i_jr(&buf, k0);
1968 uasm_i_nop(&buf);
1969 }
1970 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1971 }
1972 return (void *)old_handler;
1973 }
1974
1975 static void do_default_vi(void)
1976 {
1977 show_regs(get_irq_regs());
1978 panic("Caught unexpected vectored interrupt.");
1979 }
1980
1981 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1982 {
1983 unsigned long handler;
1984 unsigned long old_handler = vi_handlers[n];
1985 int srssets = current_cpu_data.srsets;
1986 u16 *h;
1987 unsigned char *b;
1988
1989 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1990
1991 if (addr == NULL) {
1992 handler = (unsigned long) do_default_vi;
1993 srs = 0;
1994 } else
1995 handler = (unsigned long) addr;
1996 vi_handlers[n] = handler;
1997
1998 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1999
2000 if (srs >= srssets)
2001 panic("Shadow register set %d not supported", srs);
2002
2003 if (cpu_has_veic) {
2004 if (board_bind_eic_interrupt)
2005 board_bind_eic_interrupt(n, srs);
2006 } else if (cpu_has_vint) {
2007 /* SRSMap is only defined if shadow sets are implemented */
2008 if (srssets > 1)
2009 change_c0_srsmap(0xf << n*4, srs << n*4);
2010 }
2011
2012 if (srs == 0) {
2013 /*
2014 * If no shadow set is selected then use the default handler
2015 * that does normal register saving and standard interrupt exit
2016 */
2017 extern char except_vec_vi, except_vec_vi_lui;
2018 extern char except_vec_vi_ori, except_vec_vi_end;
2019 extern char rollback_except_vec_vi;
2020 char *vec_start = using_rollback_handler() ?
2021 &rollback_except_vec_vi : &except_vec_vi;
2022 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
2023 const int lui_offset = &except_vec_vi_lui - vec_start + 2;
2024 const int ori_offset = &except_vec_vi_ori - vec_start + 2;
2025 #else
2026 const int lui_offset = &except_vec_vi_lui - vec_start;
2027 const int ori_offset = &except_vec_vi_ori - vec_start;
2028 #endif
2029 const int handler_len = &except_vec_vi_end - vec_start;
2030
2031 if (handler_len > VECTORSPACING) {
2032 /*
2033 * Sigh... panicing won't help as the console
2034 * is probably not configured :(
2035 */
2036 panic("VECTORSPACING too small");
2037 }
2038
2039 set_handler(((unsigned long)b - ebase), vec_start,
2040 #ifdef CONFIG_CPU_MICROMIPS
2041 (handler_len - 1));
2042 #else
2043 handler_len);
2044 #endif
2045 h = (u16 *)(b + lui_offset);
2046 *h = (handler >> 16) & 0xffff;
2047 h = (u16 *)(b + ori_offset);
2048 *h = (handler & 0xffff);
2049 local_flush_icache_range((unsigned long)b,
2050 (unsigned long)(b+handler_len));
2051 }
2052 else {
2053 /*
2054 * In other cases jump directly to the interrupt handler. It
2055 * is the handler's responsibility to save registers if required
2056 * (eg hi/lo) and return from the exception using "eret".
2057 */
2058 u32 insn;
2059
2060 h = (u16 *)b;
2061 /* j handler */
2062 #ifdef CONFIG_CPU_MICROMIPS
2063 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
2064 #else
2065 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
2066 #endif
2067 h[0] = (insn >> 16) & 0xffff;
2068 h[1] = insn & 0xffff;
2069 h[2] = 0;
2070 h[3] = 0;
2071 local_flush_icache_range((unsigned long)b,
2072 (unsigned long)(b+8));
2073 }
2074
2075 return (void *)old_handler;
2076 }
2077
2078 void *set_vi_handler(int n, vi_handler_t addr)
2079 {
2080 return set_vi_srs_handler(n, addr, 0);
2081 }
2082
2083 extern void tlb_init(void);
2084
2085 /*
2086 * Timer interrupt
2087 */
2088 int cp0_compare_irq;
2089 EXPORT_SYMBOL_GPL(cp0_compare_irq);
2090 int cp0_compare_irq_shift;
2091
2092 /*
2093 * Performance counter IRQ or -1 if shared with timer
2094 */
2095 int cp0_perfcount_irq;
2096 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
2097
2098 /*
2099 * Fast debug channel IRQ or -1 if not present
2100 */
2101 int cp0_fdc_irq;
2102 EXPORT_SYMBOL_GPL(cp0_fdc_irq);
2103
2104 static int noulri;
2105
2106 static int __init ulri_disable(char *s)
2107 {
2108 pr_info("Disabling ulri\n");
2109 noulri = 1;
2110
2111 return 1;
2112 }
2113 __setup("noulri", ulri_disable);
2114
2115 /* configure STATUS register */
2116 static void configure_status(void)
2117 {
2118 /*
2119 * Disable coprocessors and select 32-bit or 64-bit addressing
2120 * and the 16/32 or 32/32 FPR register model. Reset the BEV
2121 * flag that some firmware may have left set and the TS bit (for
2122 * IP27). Set XX for ISA IV code to work.
2123 */
2124 unsigned int status_set = ST0_CU0;
2125 #ifdef CONFIG_64BIT
2126 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
2127 #endif
2128 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
2129 status_set |= ST0_XX;
2130 if (cpu_has_dsp)
2131 status_set |= ST0_MX;
2132
2133 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
2134 status_set);
2135 }
2136
2137 unsigned int hwrena;
2138 EXPORT_SYMBOL_GPL(hwrena);
2139
2140 /* configure HWRENA register */
2141 static void configure_hwrena(void)
2142 {
2143 hwrena = cpu_hwrena_impl_bits;
2144
2145 if (cpu_has_mips_r2_r6)
2146 hwrena |= MIPS_HWRENA_CPUNUM |
2147 MIPS_HWRENA_SYNCISTEP |
2148 MIPS_HWRENA_CC |
2149 MIPS_HWRENA_CCRES;
2150
2151 if (!noulri && cpu_has_userlocal)
2152 hwrena |= MIPS_HWRENA_ULR;
2153
2154 if (hwrena)
2155 write_c0_hwrena(hwrena);
2156 }
2157
2158 static void configure_exception_vector(void)
2159 {
2160 if (cpu_has_veic || cpu_has_vint) {
2161 unsigned long sr = set_c0_status(ST0_BEV);
2162 /* If available, use WG to set top bits of EBASE */
2163 if (cpu_has_ebase_wg) {
2164 #ifdef CONFIG_64BIT
2165 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
2166 #else
2167 write_c0_ebase(ebase | MIPS_EBASE_WG);
2168 #endif
2169 }
2170 write_c0_ebase(ebase);
2171 write_c0_status(sr);
2172 /* Setting vector spacing enables EI/VI mode */
2173 change_c0_intctl(0x3e0, VECTORSPACING);
2174 }
2175 if (cpu_has_divec) {
2176 if (cpu_has_mipsmt) {
2177 unsigned int vpflags = dvpe();
2178 set_c0_cause(CAUSEF_IV);
2179 evpe(vpflags);
2180 } else
2181 set_c0_cause(CAUSEF_IV);
2182 }
2183 }
2184
2185 void per_cpu_trap_init(bool is_boot_cpu)
2186 {
2187 unsigned int cpu = smp_processor_id();
2188
2189 configure_status();
2190 configure_hwrena();
2191
2192 configure_exception_vector();
2193
2194 /*
2195 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
2196 *
2197 * o read IntCtl.IPTI to determine the timer interrupt
2198 * o read IntCtl.IPPCI to determine the performance counter interrupt
2199 * o read IntCtl.IPFDC to determine the fast debug channel interrupt
2200 */
2201 if (cpu_has_mips_r2_r6) {
2202 /*
2203 * We shouldn't trust a secondary core has a sane EBASE register
2204 * so use the one calculated by the boot CPU.
2205 */
2206 if (!is_boot_cpu) {
2207 /* If available, use WG to set top bits of EBASE */
2208 if (cpu_has_ebase_wg) {
2209 #ifdef CONFIG_64BIT
2210 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
2211 #else
2212 write_c0_ebase(ebase | MIPS_EBASE_WG);
2213 #endif
2214 }
2215 write_c0_ebase(ebase);
2216 }
2217
2218 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
2219 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
2220 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
2221 cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7;
2222 if (!cp0_fdc_irq)
2223 cp0_fdc_irq = -1;
2224
2225 } else {
2226 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
2227 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
2228 cp0_perfcount_irq = -1;
2229 cp0_fdc_irq = -1;
2230 }
2231
2232 if (!cpu_data[cpu].asid_cache)
2233 cpu_data[cpu].asid_cache = asid_first_version(cpu);
2234
2235 mmgrab(&init_mm);
2236 current->active_mm = &init_mm;
2237 BUG_ON(current->mm);
2238 enter_lazy_tlb(&init_mm, current);
2239
2240 /* Boot CPU's cache setup in setup_arch(). */
2241 if (!is_boot_cpu)
2242 cpu_cache_init();
2243 tlb_init();
2244 TLBMISS_HANDLER_SETUP();
2245 }
2246
2247 /* Install CPU exception handler */
2248 void set_handler(unsigned long offset, void *addr, unsigned long size)
2249 {
2250 #ifdef CONFIG_CPU_MICROMIPS
2251 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
2252 #else
2253 memcpy((void *)(ebase + offset), addr, size);
2254 #endif
2255 local_flush_icache_range(ebase + offset, ebase + offset + size);
2256 }
2257
2258 static char panic_null_cerr[] =
2259 "Trying to set NULL cache error exception handler";
2260
2261 /*
2262 * Install uncached CPU exception handler.
2263 * This is suitable only for the cache error exception which is the only
2264 * exception handler that is being run uncached.
2265 */
2266 void set_uncached_handler(unsigned long offset, void *addr,
2267 unsigned long size)
2268 {
2269 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
2270
2271 if (!addr)
2272 panic(panic_null_cerr);
2273
2274 memcpy((void *)(uncached_ebase + offset), addr, size);
2275 }
2276
2277 static int __initdata rdhwr_noopt;
2278 static int __init set_rdhwr_noopt(char *str)
2279 {
2280 rdhwr_noopt = 1;
2281 return 1;
2282 }
2283
2284 __setup("rdhwr_noopt", set_rdhwr_noopt);
2285
2286 void __init trap_init(void)
2287 {
2288 extern char except_vec3_generic;
2289 extern char except_vec4;
2290 extern char except_vec3_r4000;
2291 unsigned long i;
2292
2293 check_wait();
2294
2295 if (cpu_has_veic || cpu_has_vint) {
2296 unsigned long size = 0x200 + VECTORSPACING*64;
2297 phys_addr_t ebase_pa;
2298
2299 ebase = (unsigned long)
2300 __alloc_bootmem(size, 1 << fls(size), 0);
2301
2302 /*
2303 * Try to ensure ebase resides in KSeg0 if possible.
2304 *
2305 * It shouldn't generally be in XKPhys on MIPS64 to avoid
2306 * hitting a poorly defined exception base for Cache Errors.
2307 * The allocation is likely to be in the low 512MB of physical,
2308 * in which case we should be able to convert to KSeg0.
2309 *
2310 * EVA is special though as it allows segments to be rearranged
2311 * and to become uncached during cache error handling.
2312 */
2313 ebase_pa = __pa(ebase);
2314 if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000))
2315 ebase = CKSEG0ADDR(ebase_pa);
2316 } else {
2317 ebase = CAC_BASE;
2318
2319 if (cpu_has_mips_r2_r6) {
2320 if (cpu_has_ebase_wg) {
2321 #ifdef CONFIG_64BIT
2322 ebase = (read_c0_ebase_64() & ~0xfff);
2323 #else
2324 ebase = (read_c0_ebase() & ~0xfff);
2325 #endif
2326 } else {
2327 ebase += (read_c0_ebase() & 0x3ffff000);
2328 }
2329 }
2330 }
2331
2332 if (cpu_has_mmips) {
2333 unsigned int config3 = read_c0_config3();
2334
2335 if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
2336 write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
2337 else
2338 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
2339 }
2340
2341 if (board_ebase_setup)
2342 board_ebase_setup();
2343 per_cpu_trap_init(true);
2344
2345 /*
2346 * Copy the generic exception handlers to their final destination.
2347 * This will be overridden later as suitable for a particular
2348 * configuration.
2349 */
2350 set_handler(0x180, &except_vec3_generic, 0x80);
2351
2352 /*
2353 * Setup default vectors
2354 */
2355 for (i = 0; i <= 31; i++)
2356 set_except_vector(i, handle_reserved);
2357
2358 /*
2359 * Copy the EJTAG debug exception vector handler code to it's final
2360 * destination.
2361 */
2362 if (cpu_has_ejtag && board_ejtag_handler_setup)
2363 board_ejtag_handler_setup();
2364
2365 /*
2366 * Only some CPUs have the watch exceptions.
2367 */
2368 if (cpu_has_watch)
2369 set_except_vector(EXCCODE_WATCH, handle_watch);
2370
2371 /*
2372 * Initialise interrupt handlers
2373 */
2374 if (cpu_has_veic || cpu_has_vint) {
2375 int nvec = cpu_has_veic ? 64 : 8;
2376 for (i = 0; i < nvec; i++)
2377 set_vi_handler(i, NULL);
2378 }
2379 else if (cpu_has_divec)
2380 set_handler(0x200, &except_vec4, 0x8);
2381
2382 /*
2383 * Some CPUs can enable/disable for cache parity detection, but does
2384 * it different ways.
2385 */
2386 parity_protection_init();
2387
2388 /*
2389 * The Data Bus Errors / Instruction Bus Errors are signaled
2390 * by external hardware. Therefore these two exceptions
2391 * may have board specific handlers.
2392 */
2393 if (board_be_init)
2394 board_be_init();
2395
2396 set_except_vector(EXCCODE_INT, using_rollback_handler() ?
2397 rollback_handle_int : handle_int);
2398 set_except_vector(EXCCODE_MOD, handle_tlbm);
2399 set_except_vector(EXCCODE_TLBL, handle_tlbl);
2400 set_except_vector(EXCCODE_TLBS, handle_tlbs);
2401
2402 set_except_vector(EXCCODE_ADEL, handle_adel);
2403 set_except_vector(EXCCODE_ADES, handle_ades);
2404
2405 set_except_vector(EXCCODE_IBE, handle_ibe);
2406 set_except_vector(EXCCODE_DBE, handle_dbe);
2407
2408 set_except_vector(EXCCODE_SYS, handle_sys);
2409 set_except_vector(EXCCODE_BP, handle_bp);
2410 set_except_vector(EXCCODE_RI, rdhwr_noopt ? handle_ri :
2411 (cpu_has_vtag_icache ?
2412 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
2413 set_except_vector(EXCCODE_CPU, handle_cpu);
2414 set_except_vector(EXCCODE_OV, handle_ov);
2415 set_except_vector(EXCCODE_TR, handle_tr);
2416 set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe);
2417
2418 if (current_cpu_type() == CPU_R6000 ||
2419 current_cpu_type() == CPU_R6000A) {
2420 /*
2421 * The R6000 is the only R-series CPU that features a machine
2422 * check exception (similar to the R4000 cache error) and
2423 * unaligned ldc1/sdc1 exception. The handlers have not been
2424 * written yet. Well, anyway there is no R6000 machine on the
2425 * current list of targets for Linux/MIPS.
2426 * (Duh, crap, there is someone with a triple R6k machine)
2427 */
2428 //set_except_vector(14, handle_mc);
2429 //set_except_vector(15, handle_ndc);
2430 }
2431
2432
2433 if (board_nmi_handler_setup)
2434 board_nmi_handler_setup();
2435
2436 if (cpu_has_fpu && !cpu_has_nofpuex)
2437 set_except_vector(EXCCODE_FPE, handle_fpe);
2438
2439 set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb);
2440
2441 if (cpu_has_rixiex) {
2442 set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0);
2443 set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0);
2444 }
2445
2446 set_except_vector(EXCCODE_MSADIS, handle_msa);
2447 set_except_vector(EXCCODE_MDMX, handle_mdmx);
2448
2449 if (cpu_has_mcheck)
2450 set_except_vector(EXCCODE_MCHECK, handle_mcheck);
2451
2452 if (cpu_has_mipsmt)
2453 set_except_vector(EXCCODE_THREAD, handle_mt);
2454
2455 set_except_vector(EXCCODE_DSPDIS, handle_dsp);
2456
2457 if (board_cache_error_setup)
2458 board_cache_error_setup();
2459
2460 if (cpu_has_vce)
2461 /* Special exception: R4[04]00 uses also the divec space. */
2462 set_handler(0x180, &except_vec3_r4000, 0x100);
2463 else if (cpu_has_4kex)
2464 set_handler(0x180, &except_vec3_generic, 0x80);
2465 else
2466 set_handler(0x080, &except_vec3_generic, 0x80);
2467
2468 local_flush_icache_range(ebase, ebase + 0x400);
2469
2470 sort_extable(__start___dbe_table, __stop___dbe_table);
2471
2472 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
2473 }
2474
2475 static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd,
2476 void *v)
2477 {
2478 switch (cmd) {
2479 case CPU_PM_ENTER_FAILED:
2480 case CPU_PM_EXIT:
2481 configure_status();
2482 configure_hwrena();
2483 configure_exception_vector();
2484
2485 /* Restore register with CPU number for TLB handlers */
2486 TLBMISS_HANDLER_RESTORE();
2487
2488 break;
2489 }
2490
2491 return NOTIFY_OK;
2492 }
2493
2494 static struct notifier_block trap_pm_notifier_block = {
2495 .notifier_call = trap_pm_notifier,
2496 };
2497
2498 static int __init trap_pm_init(void)
2499 {
2500 return cpu_pm_register_notifier(&trap_pm_notifier_block);
2501 }
2502 arch_initcall(trap_pm_init);
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