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1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
13 */
14 #include <linux/bug.h>
15 #include <linux/compiler.h>
16 #include <linux/kexec.h>
17 #include <linux/init.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/mm.h>
21 #include <linux/sched.h>
22 #include <linux/smp.h>
23 #include <linux/spinlock.h>
24 #include <linux/kallsyms.h>
25 #include <linux/bootmem.h>
26 #include <linux/interrupt.h>
27 #include <linux/ptrace.h>
28 #include <linux/kgdb.h>
29 #include <linux/kdebug.h>
30 #include <linux/kprobes.h>
31 #include <linux/notifier.h>
32 #include <linux/kdb.h>
33 #include <linux/irq.h>
34 #include <linux/perf_event.h>
35
36 #include <asm/bootinfo.h>
37 #include <asm/branch.h>
38 #include <asm/break.h>
39 #include <asm/cop2.h>
40 #include <asm/cpu.h>
41 #include <asm/dsp.h>
42 #include <asm/fpu.h>
43 #include <asm/fpu_emulator.h>
44 #include <asm/mipsregs.h>
45 #include <asm/mipsmtregs.h>
46 #include <asm/module.h>
47 #include <asm/pgtable.h>
48 #include <asm/ptrace.h>
49 #include <asm/sections.h>
50 #include <asm/tlbdebug.h>
51 #include <asm/traps.h>
52 #include <asm/uaccess.h>
53 #include <asm/watch.h>
54 #include <asm/mmu_context.h>
55 #include <asm/types.h>
56 #include <asm/stacktrace.h>
57 #include <asm/uasm.h>
58
59 extern void check_wait(void);
60 extern asmlinkage void r4k_wait(void);
61 extern asmlinkage void rollback_handle_int(void);
62 extern asmlinkage void handle_int(void);
63 extern asmlinkage void handle_tlbm(void);
64 extern asmlinkage void handle_tlbl(void);
65 extern asmlinkage void handle_tlbs(void);
66 extern asmlinkage void handle_adel(void);
67 extern asmlinkage void handle_ades(void);
68 extern asmlinkage void handle_ibe(void);
69 extern asmlinkage void handle_dbe(void);
70 extern asmlinkage void handle_sys(void);
71 extern asmlinkage void handle_bp(void);
72 extern asmlinkage void handle_ri(void);
73 extern asmlinkage void handle_ri_rdhwr_vivt(void);
74 extern asmlinkage void handle_ri_rdhwr(void);
75 extern asmlinkage void handle_cpu(void);
76 extern asmlinkage void handle_ov(void);
77 extern asmlinkage void handle_tr(void);
78 extern asmlinkage void handle_fpe(void);
79 extern asmlinkage void handle_mdmx(void);
80 extern asmlinkage void handle_watch(void);
81 extern asmlinkage void handle_mt(void);
82 extern asmlinkage void handle_dsp(void);
83 extern asmlinkage void handle_mcheck(void);
84 extern asmlinkage void handle_reserved(void);
85
86 void (*board_be_init)(void);
87 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
88 void (*board_nmi_handler_setup)(void);
89 void (*board_ejtag_handler_setup)(void);
90 void (*board_bind_eic_interrupt)(int irq, int regset);
91 void (*board_ebase_setup)(void);
92 void __cpuinitdata(*board_cache_error_setup)(void);
93
94 static void show_raw_backtrace(unsigned long reg29)
95 {
96 unsigned long *sp = (unsigned long *)(reg29 & ~3);
97 unsigned long addr;
98
99 printk("Call Trace:");
100 #ifdef CONFIG_KALLSYMS
101 printk("\n");
102 #endif
103 while (!kstack_end(sp)) {
104 unsigned long __user *p =
105 (unsigned long __user *)(unsigned long)sp++;
106 if (__get_user(addr, p)) {
107 printk(" (Bad stack address)");
108 break;
109 }
110 if (__kernel_text_address(addr))
111 print_ip_sym(addr);
112 }
113 printk("\n");
114 }
115
116 #ifdef CONFIG_KALLSYMS
117 int raw_show_trace;
118 static int __init set_raw_show_trace(char *str)
119 {
120 raw_show_trace = 1;
121 return 1;
122 }
123 __setup("raw_show_trace", set_raw_show_trace);
124 #endif
125
126 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
127 {
128 unsigned long sp = regs->regs[29];
129 unsigned long ra = regs->regs[31];
130 unsigned long pc = regs->cp0_epc;
131
132 if (!task)
133 task = current;
134
135 if (raw_show_trace || !__kernel_text_address(pc)) {
136 show_raw_backtrace(sp);
137 return;
138 }
139 printk("Call Trace:\n");
140 do {
141 print_ip_sym(pc);
142 pc = unwind_stack(task, &sp, pc, &ra);
143 } while (pc);
144 printk("\n");
145 }
146
147 /*
148 * This routine abuses get_user()/put_user() to reference pointers
149 * with at least a bit of error checking ...
150 */
151 static void show_stacktrace(struct task_struct *task,
152 const struct pt_regs *regs)
153 {
154 const int field = 2 * sizeof(unsigned long);
155 long stackdata;
156 int i;
157 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
158
159 printk("Stack :");
160 i = 0;
161 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
162 if (i && ((i % (64 / field)) == 0))
163 printk("\n ");
164 if (i > 39) {
165 printk(" ...");
166 break;
167 }
168
169 if (__get_user(stackdata, sp++)) {
170 printk(" (Bad stack address)");
171 break;
172 }
173
174 printk(" %0*lx", field, stackdata);
175 i++;
176 }
177 printk("\n");
178 show_backtrace(task, regs);
179 }
180
181 void show_stack(struct task_struct *task, unsigned long *sp)
182 {
183 struct pt_regs regs;
184 if (sp) {
185 regs.regs[29] = (unsigned long)sp;
186 regs.regs[31] = 0;
187 regs.cp0_epc = 0;
188 } else {
189 if (task && task != current) {
190 regs.regs[29] = task->thread.reg29;
191 regs.regs[31] = 0;
192 regs.cp0_epc = task->thread.reg31;
193 #ifdef CONFIG_KGDB_KDB
194 } else if (atomic_read(&kgdb_active) != -1 &&
195 kdb_current_regs) {
196 memcpy(&regs, kdb_current_regs, sizeof(regs));
197 #endif /* CONFIG_KGDB_KDB */
198 } else {
199 prepare_frametrace(&regs);
200 }
201 }
202 show_stacktrace(task, &regs);
203 }
204
205 /*
206 * The architecture-independent dump_stack generator
207 */
208 void dump_stack(void)
209 {
210 struct pt_regs regs;
211
212 prepare_frametrace(&regs);
213 show_backtrace(current, &regs);
214 }
215
216 EXPORT_SYMBOL(dump_stack);
217
218 static void show_code(unsigned int __user *pc)
219 {
220 long i;
221 unsigned short __user *pc16 = NULL;
222
223 printk("\nCode:");
224
225 if ((unsigned long)pc & 1)
226 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
227 for(i = -3 ; i < 6 ; i++) {
228 unsigned int insn;
229 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
230 printk(" (Bad address in epc)\n");
231 break;
232 }
233 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
234 }
235 }
236
237 static void __show_regs(const struct pt_regs *regs)
238 {
239 const int field = 2 * sizeof(unsigned long);
240 unsigned int cause = regs->cp0_cause;
241 int i;
242
243 printk("Cpu %d\n", smp_processor_id());
244
245 /*
246 * Saved main processor registers
247 */
248 for (i = 0; i < 32; ) {
249 if ((i % 4) == 0)
250 printk("$%2d :", i);
251 if (i == 0)
252 printk(" %0*lx", field, 0UL);
253 else if (i == 26 || i == 27)
254 printk(" %*s", field, "");
255 else
256 printk(" %0*lx", field, regs->regs[i]);
257
258 i++;
259 if ((i % 4) == 0)
260 printk("\n");
261 }
262
263 #ifdef CONFIG_CPU_HAS_SMARTMIPS
264 printk("Acx : %0*lx\n", field, regs->acx);
265 #endif
266 printk("Hi : %0*lx\n", field, regs->hi);
267 printk("Lo : %0*lx\n", field, regs->lo);
268
269 /*
270 * Saved cp0 registers
271 */
272 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
273 (void *) regs->cp0_epc);
274 printk(" %s\n", print_tainted());
275 printk("ra : %0*lx %pS\n", field, regs->regs[31],
276 (void *) regs->regs[31]);
277
278 printk("Status: %08x ", (uint32_t) regs->cp0_status);
279
280 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
281 if (regs->cp0_status & ST0_KUO)
282 printk("KUo ");
283 if (regs->cp0_status & ST0_IEO)
284 printk("IEo ");
285 if (regs->cp0_status & ST0_KUP)
286 printk("KUp ");
287 if (regs->cp0_status & ST0_IEP)
288 printk("IEp ");
289 if (regs->cp0_status & ST0_KUC)
290 printk("KUc ");
291 if (regs->cp0_status & ST0_IEC)
292 printk("IEc ");
293 } else {
294 if (regs->cp0_status & ST0_KX)
295 printk("KX ");
296 if (regs->cp0_status & ST0_SX)
297 printk("SX ");
298 if (regs->cp0_status & ST0_UX)
299 printk("UX ");
300 switch (regs->cp0_status & ST0_KSU) {
301 case KSU_USER:
302 printk("USER ");
303 break;
304 case KSU_SUPERVISOR:
305 printk("SUPERVISOR ");
306 break;
307 case KSU_KERNEL:
308 printk("KERNEL ");
309 break;
310 default:
311 printk("BAD_MODE ");
312 break;
313 }
314 if (regs->cp0_status & ST0_ERL)
315 printk("ERL ");
316 if (regs->cp0_status & ST0_EXL)
317 printk("EXL ");
318 if (regs->cp0_status & ST0_IE)
319 printk("IE ");
320 }
321 printk("\n");
322
323 printk("Cause : %08x\n", cause);
324
325 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
326 if (1 <= cause && cause <= 5)
327 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
328
329 printk("PrId : %08x (%s)\n", read_c0_prid(),
330 cpu_name_string());
331 }
332
333 /*
334 * FIXME: really the generic show_regs should take a const pointer argument.
335 */
336 void show_regs(struct pt_regs *regs)
337 {
338 __show_regs((struct pt_regs *)regs);
339 }
340
341 void show_registers(struct pt_regs *regs)
342 {
343 const int field = 2 * sizeof(unsigned long);
344
345 __show_regs(regs);
346 print_modules();
347 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
348 current->comm, current->pid, current_thread_info(), current,
349 field, current_thread_info()->tp_value);
350 if (cpu_has_userlocal) {
351 unsigned long tls;
352
353 tls = read_c0_userlocal();
354 if (tls != current_thread_info()->tp_value)
355 printk("*HwTLS: %0*lx\n", field, tls);
356 }
357
358 show_stacktrace(current, regs);
359 show_code((unsigned int __user *) regs->cp0_epc);
360 printk("\n");
361 }
362
363 static int regs_to_trapnr(struct pt_regs *regs)
364 {
365 return (regs->cp0_cause >> 2) & 0x1f;
366 }
367
368 static DEFINE_RAW_SPINLOCK(die_lock);
369
370 void __noreturn die(const char *str, struct pt_regs *regs)
371 {
372 static int die_counter;
373 int sig = SIGSEGV;
374 #ifdef CONFIG_MIPS_MT_SMTC
375 unsigned long dvpret;
376 #endif /* CONFIG_MIPS_MT_SMTC */
377
378 oops_enter();
379
380 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP)
381 sig = 0;
382
383 console_verbose();
384 raw_spin_lock_irq(&die_lock);
385 #ifdef CONFIG_MIPS_MT_SMTC
386 dvpret = dvpe();
387 #endif /* CONFIG_MIPS_MT_SMTC */
388 bust_spinlocks(1);
389 #ifdef CONFIG_MIPS_MT_SMTC
390 mips_mt_regdump(dvpret);
391 #endif /* CONFIG_MIPS_MT_SMTC */
392
393 printk("%s[#%d]:\n", str, ++die_counter);
394 show_registers(regs);
395 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
396 raw_spin_unlock_irq(&die_lock);
397
398 oops_exit();
399
400 if (in_interrupt())
401 panic("Fatal exception in interrupt");
402
403 if (panic_on_oops) {
404 printk(KERN_EMERG "Fatal exception: panic in 5 seconds");
405 ssleep(5);
406 panic("Fatal exception");
407 }
408
409 if (regs && kexec_should_crash(current))
410 crash_kexec(regs);
411
412 do_exit(sig);
413 }
414
415 extern struct exception_table_entry __start___dbe_table[];
416 extern struct exception_table_entry __stop___dbe_table[];
417
418 __asm__(
419 " .section __dbe_table, \"a\"\n"
420 " .previous \n");
421
422 /* Given an address, look for it in the exception tables. */
423 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
424 {
425 const struct exception_table_entry *e;
426
427 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
428 if (!e)
429 e = search_module_dbetables(addr);
430 return e;
431 }
432
433 asmlinkage void do_be(struct pt_regs *regs)
434 {
435 const int field = 2 * sizeof(unsigned long);
436 const struct exception_table_entry *fixup = NULL;
437 int data = regs->cp0_cause & 4;
438 int action = MIPS_BE_FATAL;
439
440 /* XXX For now. Fixme, this searches the wrong table ... */
441 if (data && !user_mode(regs))
442 fixup = search_dbe_tables(exception_epc(regs));
443
444 if (fixup)
445 action = MIPS_BE_FIXUP;
446
447 if (board_be_handler)
448 action = board_be_handler(regs, fixup != NULL);
449
450 switch (action) {
451 case MIPS_BE_DISCARD:
452 return;
453 case MIPS_BE_FIXUP:
454 if (fixup) {
455 regs->cp0_epc = fixup->nextinsn;
456 return;
457 }
458 break;
459 default:
460 break;
461 }
462
463 /*
464 * Assume it would be too dangerous to continue ...
465 */
466 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
467 data ? "Data" : "Instruction",
468 field, regs->cp0_epc, field, regs->regs[31]);
469 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS)
470 == NOTIFY_STOP)
471 return;
472
473 die_if_kernel("Oops", regs);
474 force_sig(SIGBUS, current);
475 }
476
477 /*
478 * ll/sc, rdhwr, sync emulation
479 */
480
481 #define OPCODE 0xfc000000
482 #define BASE 0x03e00000
483 #define RT 0x001f0000
484 #define OFFSET 0x0000ffff
485 #define LL 0xc0000000
486 #define SC 0xe0000000
487 #define SPEC0 0x00000000
488 #define SPEC3 0x7c000000
489 #define RD 0x0000f800
490 #define FUNC 0x0000003f
491 #define SYNC 0x0000000f
492 #define RDHWR 0x0000003b
493
494 /* microMIPS definitions */
495 #define MM_POOL32A_FUNC 0xfc00ffff
496 #define MM_RDHWR 0x00006b3c
497 #define MM_RS 0x001f0000
498 #define MM_RT 0x03e00000
499
500 /*
501 * The ll_bit is cleared by r*_switch.S
502 */
503
504 unsigned int ll_bit;
505 struct task_struct *ll_task;
506
507 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
508 {
509 unsigned long value, __user *vaddr;
510 long offset;
511
512 /*
513 * analyse the ll instruction that just caused a ri exception
514 * and put the referenced address to addr.
515 */
516
517 /* sign extend offset */
518 offset = opcode & OFFSET;
519 offset <<= 16;
520 offset >>= 16;
521
522 vaddr = (unsigned long __user *)
523 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
524
525 if ((unsigned long)vaddr & 3)
526 return SIGBUS;
527 if (get_user(value, vaddr))
528 return SIGSEGV;
529
530 preempt_disable();
531
532 if (ll_task == NULL || ll_task == current) {
533 ll_bit = 1;
534 } else {
535 ll_bit = 0;
536 }
537 ll_task = current;
538
539 preempt_enable();
540
541 regs->regs[(opcode & RT) >> 16] = value;
542
543 return 0;
544 }
545
546 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
547 {
548 unsigned long __user *vaddr;
549 unsigned long reg;
550 long offset;
551
552 /*
553 * analyse the sc instruction that just caused a ri exception
554 * and put the referenced address to addr.
555 */
556
557 /* sign extend offset */
558 offset = opcode & OFFSET;
559 offset <<= 16;
560 offset >>= 16;
561
562 vaddr = (unsigned long __user *)
563 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
564 reg = (opcode & RT) >> 16;
565
566 if ((unsigned long)vaddr & 3)
567 return SIGBUS;
568
569 preempt_disable();
570
571 if (ll_bit == 0 || ll_task != current) {
572 regs->regs[reg] = 0;
573 preempt_enable();
574 return 0;
575 }
576
577 preempt_enable();
578
579 if (put_user(regs->regs[reg], vaddr))
580 return SIGSEGV;
581
582 regs->regs[reg] = 1;
583
584 return 0;
585 }
586
587 /*
588 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
589 * opcodes are supposed to result in coprocessor unusable exceptions if
590 * executed on ll/sc-less processors. That's the theory. In practice a
591 * few processors such as NEC's VR4100 throw reserved instruction exceptions
592 * instead, so we're doing the emulation thing in both exception handlers.
593 */
594 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
595 {
596 if ((opcode & OPCODE) == LL) {
597 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
598 1, regs, 0);
599 return simulate_ll(regs, opcode);
600 }
601 if ((opcode & OPCODE) == SC) {
602 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
603 1, regs, 0);
604 return simulate_sc(regs, opcode);
605 }
606
607 return -1; /* Must be something else ... */
608 }
609
610 /*
611 * Simulate trapping 'rdhwr' instructions to provide user accessible
612 * registers not implemented in hardware.
613 */
614 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
615 {
616 struct thread_info *ti = task_thread_info(current);
617
618 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
619 1, regs, 0);
620 switch (rd) {
621 case 0: /* CPU number */
622 regs->regs[rt] = smp_processor_id();
623 return 0;
624 case 1: /* SYNCI length */
625 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
626 current_cpu_data.icache.linesz);
627 return 0;
628 case 2: /* Read count register */
629 regs->regs[rt] = read_c0_count();
630 return 0;
631 case 3: /* Count register resolution */
632 switch (current_cpu_data.cputype) {
633 case CPU_20KC:
634 case CPU_25KF:
635 regs->regs[rt] = 1;
636 break;
637 default:
638 regs->regs[rt] = 2;
639 }
640 return 0;
641 case 29:
642 regs->regs[rt] = ti->tp_value;
643 return 0;
644 default:
645 return -1;
646 }
647 }
648
649 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
650 {
651 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
652 int rd = (opcode & RD) >> 11;
653 int rt = (opcode & RT) >> 16;
654
655 simulate_rdhwr(regs, rd, rt);
656 return 0;
657 }
658
659 /* Not ours. */
660 return -1;
661 }
662
663 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode)
664 {
665 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
666 int rd = (opcode & MM_RS) >> 16;
667 int rt = (opcode & MM_RT) >> 21;
668 simulate_rdhwr(regs, rd, rt);
669 return 0;
670 }
671
672 /* Not ours. */
673 return -1;
674 }
675
676 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
677 {
678 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
679 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
680 1, regs, 0);
681 return 0;
682 }
683
684 return -1; /* Must be something else ... */
685 }
686
687 asmlinkage void do_ov(struct pt_regs *regs)
688 {
689 siginfo_t info;
690
691 die_if_kernel("Integer overflow", regs);
692
693 info.si_code = FPE_INTOVF;
694 info.si_signo = SIGFPE;
695 info.si_errno = 0;
696 info.si_addr = (void __user *) regs->cp0_epc;
697 force_sig_info(SIGFPE, &info, current);
698 }
699
700 int process_fpemu_return(int sig, void __user *fault_addr)
701 {
702 if (sig == SIGSEGV || sig == SIGBUS) {
703 struct siginfo si = {0};
704 si.si_addr = fault_addr;
705 si.si_signo = sig;
706 if (sig == SIGSEGV) {
707 if (find_vma(current->mm, (unsigned long)fault_addr))
708 si.si_code = SEGV_ACCERR;
709 else
710 si.si_code = SEGV_MAPERR;
711 } else {
712 si.si_code = BUS_ADRERR;
713 }
714 force_sig_info(sig, &si, current);
715 return 1;
716 } else if (sig) {
717 force_sig(sig, current);
718 return 1;
719 } else {
720 return 0;
721 }
722 }
723
724 /*
725 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
726 */
727 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
728 {
729 siginfo_t info = {0};
730
731 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE)
732 == NOTIFY_STOP)
733 return;
734 die_if_kernel("FP exception in kernel code", regs);
735
736 if (fcr31 & FPU_CSR_UNI_X) {
737 int sig;
738 void __user *fault_addr = NULL;
739
740 /*
741 * Unimplemented operation exception. If we've got the full
742 * software emulator on-board, let's use it...
743 *
744 * Force FPU to dump state into task/thread context. We're
745 * moving a lot of data here for what is probably a single
746 * instruction, but the alternative is to pre-decode the FP
747 * register operands before invoking the emulator, which seems
748 * a bit extreme for what should be an infrequent event.
749 */
750 /* Ensure 'resume' not overwrite saved fp context again. */
751 lose_fpu(1);
752
753 /* Run the emulator */
754 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
755 &fault_addr);
756
757 /*
758 * We can't allow the emulated instruction to leave any of
759 * the cause bit set in $fcr31.
760 */
761 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
762
763 /* Restore the hardware register state */
764 own_fpu(1); /* Using the FPU again. */
765
766 /* If something went wrong, signal */
767 process_fpemu_return(sig, fault_addr);
768
769 return;
770 } else if (fcr31 & FPU_CSR_INV_X)
771 info.si_code = FPE_FLTINV;
772 else if (fcr31 & FPU_CSR_DIV_X)
773 info.si_code = FPE_FLTDIV;
774 else if (fcr31 & FPU_CSR_OVF_X)
775 info.si_code = FPE_FLTOVF;
776 else if (fcr31 & FPU_CSR_UDF_X)
777 info.si_code = FPE_FLTUND;
778 else if (fcr31 & FPU_CSR_INE_X)
779 info.si_code = FPE_FLTRES;
780 else
781 info.si_code = __SI_FAULT;
782 info.si_signo = SIGFPE;
783 info.si_errno = 0;
784 info.si_addr = (void __user *) regs->cp0_epc;
785 force_sig_info(SIGFPE, &info, current);
786 }
787
788 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
789 const char *str)
790 {
791 siginfo_t info;
792 char b[40];
793
794 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
795 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
796 return;
797 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
798
799 if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
800 return;
801
802 /*
803 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
804 * insns, even for trap and break codes that indicate arithmetic
805 * failures. Weird ...
806 * But should we continue the brokenness??? --macro
807 */
808 switch (code) {
809 case BRK_OVERFLOW:
810 case BRK_DIVZERO:
811 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
812 die_if_kernel(b, regs);
813 if (code == BRK_DIVZERO)
814 info.si_code = FPE_INTDIV;
815 else
816 info.si_code = FPE_INTOVF;
817 info.si_signo = SIGFPE;
818 info.si_errno = 0;
819 info.si_addr = (void __user *) regs->cp0_epc;
820 force_sig_info(SIGFPE, &info, current);
821 break;
822 case BRK_BUG:
823 die_if_kernel("Kernel bug detected", regs);
824 force_sig(SIGTRAP, current);
825 break;
826 case BRK_MEMU:
827 /*
828 * Address errors may be deliberately induced by the FPU
829 * emulator to retake control of the CPU after executing the
830 * instruction in the delay slot of an emulated branch.
831 *
832 * Terminate if exception was recognized as a delay slot return
833 * otherwise handle as normal.
834 */
835 if (do_dsemulret(regs))
836 return;
837
838 die_if_kernel("Math emu break/trap", regs);
839 force_sig(SIGTRAP, current);
840 break;
841 default:
842 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
843 die_if_kernel(b, regs);
844 force_sig(SIGTRAP, current);
845 }
846 }
847
848 asmlinkage void do_bp(struct pt_regs *regs)
849 {
850 unsigned int opcode, bcode;
851 unsigned long epc;
852 u16 instr[2];
853
854 if (get_isa16_mode(regs->cp0_epc)) {
855 /* Calculate EPC. */
856 epc = exception_epc(regs);
857 if (cpu_has_mmips) {
858 if ((__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)) ||
859 (__get_user(instr[1], (u16 __user *)msk_isa16_mode(epc + 2)))))
860 goto out_sigsegv;
861 opcode = (instr[0] << 16) | instr[1];
862 } else {
863 /* MIPS16e mode */
864 if (__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)))
865 goto out_sigsegv;
866 bcode = (instr[0] >> 6) & 0x3f;
867 do_trap_or_bp(regs, bcode, "Break");
868 return;
869 }
870 } else {
871 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
872 goto out_sigsegv;
873 }
874
875 /*
876 * There is the ancient bug in the MIPS assemblers that the break
877 * code starts left to bit 16 instead to bit 6 in the opcode.
878 * Gas is bug-compatible, but not always, grrr...
879 * We handle both cases with a simple heuristics. --macro
880 */
881 bcode = ((opcode >> 6) & ((1 << 20) - 1));
882 if (bcode >= (1 << 10))
883 bcode >>= 10;
884
885 /*
886 * notify the kprobe handlers, if instruction is likely to
887 * pertain to them.
888 */
889 switch (bcode) {
890 case BRK_KPROBE_BP:
891 if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
892 return;
893 else
894 break;
895 case BRK_KPROBE_SSTEPBP:
896 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
897 return;
898 else
899 break;
900 default:
901 break;
902 }
903
904 do_trap_or_bp(regs, bcode, "Break");
905 return;
906
907 out_sigsegv:
908 force_sig(SIGSEGV, current);
909 }
910
911 asmlinkage void do_tr(struct pt_regs *regs)
912 {
913 unsigned int opcode, tcode = 0;
914 u16 instr[2];
915 unsigned long epc = exception_epc(regs);
916
917 if ((__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc))) ||
918 (__get_user(instr[1], (u16 __user *)msk_isa16_mode(epc + 2))))
919 goto out_sigsegv;
920 opcode = (instr[0] << 16) | instr[1];
921
922 /* Immediate versions don't provide a code. */
923 if (!(opcode & OPCODE)) {
924 if (get_isa16_mode(regs->cp0_epc))
925 /* microMIPS */
926 tcode = (opcode >> 12) & 0x1f;
927 else
928 tcode = ((opcode >> 6) & ((1 << 10) - 1));
929 }
930
931 do_trap_or_bp(regs, tcode, "Trap");
932 return;
933
934 out_sigsegv:
935 force_sig(SIGSEGV, current);
936 }
937
938 asmlinkage void do_ri(struct pt_regs *regs)
939 {
940 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
941 unsigned long old_epc = regs->cp0_epc;
942 unsigned long old31 = regs->regs[31];
943 unsigned int opcode = 0;
944 int status = -1;
945
946 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL)
947 == NOTIFY_STOP)
948 return;
949
950 die_if_kernel("Reserved instruction in kernel code", regs);
951
952 if (unlikely(compute_return_epc(regs) < 0))
953 return;
954
955 if (get_isa16_mode(regs->cp0_epc)) {
956 unsigned short mmop[2] = { 0 };
957
958 if (unlikely(get_user(mmop[0], epc) < 0))
959 status = SIGSEGV;
960 if (unlikely(get_user(mmop[1], epc) < 0))
961 status = SIGSEGV;
962 opcode = (mmop[0] << 16) | mmop[1];
963
964 if (status < 0)
965 status = simulate_rdhwr_mm(regs, opcode);
966 } else {
967 if (unlikely(get_user(opcode, epc) < 0))
968 status = SIGSEGV;
969
970 if (!cpu_has_llsc && status < 0)
971 status = simulate_llsc(regs, opcode);
972
973 if (status < 0)
974 status = simulate_rdhwr_normal(regs, opcode);
975
976 if (status < 0)
977 status = simulate_sync(regs, opcode);
978 }
979
980 if (status < 0)
981 status = SIGILL;
982
983 if (unlikely(status > 0)) {
984 regs->cp0_epc = old_epc; /* Undo skip-over. */
985 regs->regs[31] = old31;
986 force_sig(status, current);
987 }
988 }
989
990 /*
991 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
992 * emulated more than some threshold number of instructions, force migration to
993 * a "CPU" that has FP support.
994 */
995 static void mt_ase_fp_affinity(void)
996 {
997 #ifdef CONFIG_MIPS_MT_FPAFF
998 if (mt_fpemul_threshold > 0 &&
999 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
1000 /*
1001 * If there's no FPU present, or if the application has already
1002 * restricted the allowed set to exclude any CPUs with FPUs,
1003 * we'll skip the procedure.
1004 */
1005 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
1006 cpumask_t tmask;
1007
1008 current->thread.user_cpus_allowed
1009 = current->cpus_allowed;
1010 cpus_and(tmask, current->cpus_allowed,
1011 mt_fpu_cpumask);
1012 set_cpus_allowed_ptr(current, &tmask);
1013 set_thread_flag(TIF_FPUBOUND);
1014 }
1015 }
1016 #endif /* CONFIG_MIPS_MT_FPAFF */
1017 }
1018
1019 /*
1020 * No lock; only written during early bootup by CPU 0.
1021 */
1022 static RAW_NOTIFIER_HEAD(cu2_chain);
1023
1024 int __ref register_cu2_notifier(struct notifier_block *nb)
1025 {
1026 return raw_notifier_chain_register(&cu2_chain, nb);
1027 }
1028
1029 int cu2_notifier_call_chain(unsigned long val, void *v)
1030 {
1031 return raw_notifier_call_chain(&cu2_chain, val, v);
1032 }
1033
1034 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
1035 void *data)
1036 {
1037 struct pt_regs *regs = data;
1038
1039 switch (action) {
1040 default:
1041 die_if_kernel("Unhandled kernel unaligned access or invalid "
1042 "instruction", regs);
1043 /* Fall through */
1044
1045 case CU2_EXCEPTION:
1046 force_sig(SIGILL, current);
1047 }
1048
1049 return NOTIFY_OK;
1050 }
1051
1052 asmlinkage void do_cpu(struct pt_regs *regs)
1053 {
1054 unsigned int __user *epc;
1055 unsigned long old_epc, old31;
1056 unsigned int opcode;
1057 unsigned int cpid;
1058 int status;
1059 unsigned long __maybe_unused flags;
1060
1061 die_if_kernel("do_cpu invoked from kernel context!", regs);
1062
1063 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1064
1065 switch (cpid) {
1066 case 0:
1067 epc = (unsigned int __user *)exception_epc(regs);
1068 old_epc = regs->cp0_epc;
1069 old31 = regs->regs[31];
1070 opcode = 0;
1071 status = -1;
1072
1073 if (unlikely(compute_return_epc(regs) < 0))
1074 return;
1075
1076 if (get_isa16_mode(regs->cp0_epc)) {
1077 unsigned short mmop[2] = { 0 };
1078
1079 if (unlikely(get_user(mmop[0], epc) < 0))
1080 status = SIGSEGV;
1081 if (unlikely(get_user(mmop[1], epc) < 0))
1082 status = SIGSEGV;
1083 opcode = (mmop[0] << 16) | mmop[1];
1084
1085 if (status < 0)
1086 status = simulate_rdhwr_mm(regs, opcode);
1087 } else {
1088 if (unlikely(get_user(opcode, epc) < 0))
1089 status = SIGSEGV;
1090
1091 if (!cpu_has_llsc && status < 0)
1092 status = simulate_llsc(regs, opcode);
1093
1094 if (status < 0)
1095 status = simulate_rdhwr_normal(regs, opcode);
1096 }
1097
1098 if (status < 0)
1099 status = SIGILL;
1100
1101 if (unlikely(status > 0)) {
1102 regs->cp0_epc = old_epc; /* Undo skip-over. */
1103 regs->regs[31] = old31;
1104 force_sig(status, current);
1105 }
1106
1107 return;
1108
1109 case 3:
1110 /*
1111 * Old (MIPS I and MIPS II) processors will set this code
1112 * for COP1X opcode instructions that replaced the original
1113 * COP3 space. We don't limit COP1 space instructions in
1114 * the emulator according to the CPU ISA, so we want to
1115 * treat COP1X instructions consistently regardless of which
1116 * code the CPU chose. Therefore we redirect this trap to
1117 * the FP emulator too.
1118 *
1119 * Then some newer FPU-less processors use this code
1120 * erroneously too, so they are covered by this choice
1121 * as well.
1122 */
1123 if (raw_cpu_has_fpu)
1124 break;
1125 /* Fall through. */
1126
1127 case 1:
1128 if (used_math()) /* Using the FPU again. */
1129 own_fpu(1);
1130 else { /* First time FPU user. */
1131 init_fpu();
1132 set_used_math();
1133 }
1134
1135 if (!raw_cpu_has_fpu) {
1136 int sig;
1137 void __user *fault_addr = NULL;
1138 sig = fpu_emulator_cop1Handler(regs,
1139 &current->thread.fpu,
1140 0, &fault_addr);
1141 if (!process_fpemu_return(sig, fault_addr))
1142 mt_ase_fp_affinity();
1143 }
1144
1145 return;
1146
1147 case 2:
1148 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1149 return;
1150 }
1151
1152 force_sig(SIGILL, current);
1153 }
1154
1155 asmlinkage void do_mdmx(struct pt_regs *regs)
1156 {
1157 force_sig(SIGILL, current);
1158 }
1159
1160 /*
1161 * Called with interrupts disabled.
1162 */
1163 asmlinkage void do_watch(struct pt_regs *regs)
1164 {
1165 u32 cause;
1166
1167 /*
1168 * Clear WP (bit 22) bit of cause register so we don't loop
1169 * forever.
1170 */
1171 cause = read_c0_cause();
1172 cause &= ~(1 << 22);
1173 write_c0_cause(cause);
1174
1175 /*
1176 * If the current thread has the watch registers loaded, save
1177 * their values and send SIGTRAP. Otherwise another thread
1178 * left the registers set, clear them and continue.
1179 */
1180 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1181 mips_read_watch_registers();
1182 local_irq_enable();
1183 force_sig(SIGTRAP, current);
1184 } else {
1185 mips_clear_watch_registers();
1186 local_irq_enable();
1187 }
1188 }
1189
1190 asmlinkage void do_mcheck(struct pt_regs *regs)
1191 {
1192 const int field = 2 * sizeof(unsigned long);
1193 int multi_match = regs->cp0_status & ST0_TS;
1194
1195 show_regs(regs);
1196
1197 if (multi_match) {
1198 printk("Index : %0x\n", read_c0_index());
1199 printk("Pagemask: %0x\n", read_c0_pagemask());
1200 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
1201 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
1202 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
1203 printk("\n");
1204 dump_tlb_all();
1205 }
1206
1207 show_code((unsigned int __user *) regs->cp0_epc);
1208
1209 /*
1210 * Some chips may have other causes of machine check (e.g. SB1
1211 * graduation timer)
1212 */
1213 panic("Caught Machine Check exception - %scaused by multiple "
1214 "matching entries in the TLB.",
1215 (multi_match) ? "" : "not ");
1216 }
1217
1218 asmlinkage void do_mt(struct pt_regs *regs)
1219 {
1220 int subcode;
1221
1222 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1223 >> VPECONTROL_EXCPT_SHIFT;
1224 switch (subcode) {
1225 case 0:
1226 printk(KERN_DEBUG "Thread Underflow\n");
1227 break;
1228 case 1:
1229 printk(KERN_DEBUG "Thread Overflow\n");
1230 break;
1231 case 2:
1232 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1233 break;
1234 case 3:
1235 printk(KERN_DEBUG "Gating Storage Exception\n");
1236 break;
1237 case 4:
1238 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1239 break;
1240 case 5:
1241 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
1242 break;
1243 default:
1244 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1245 subcode);
1246 break;
1247 }
1248 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1249
1250 force_sig(SIGILL, current);
1251 }
1252
1253
1254 asmlinkage void do_dsp(struct pt_regs *regs)
1255 {
1256 if (cpu_has_dsp)
1257 panic("Unexpected DSP exception");
1258
1259 force_sig(SIGILL, current);
1260 }
1261
1262 asmlinkage void do_reserved(struct pt_regs *regs)
1263 {
1264 /*
1265 * Game over - no way to handle this if it ever occurs. Most probably
1266 * caused by a new unknown cpu type or after another deadly
1267 * hard/software error.
1268 */
1269 show_regs(regs);
1270 panic("Caught reserved exception %ld - should not happen.",
1271 (regs->cp0_cause & 0x7f) >> 2);
1272 }
1273
1274 static int __initdata l1parity = 1;
1275 static int __init nol1parity(char *s)
1276 {
1277 l1parity = 0;
1278 return 1;
1279 }
1280 __setup("nol1par", nol1parity);
1281 static int __initdata l2parity = 1;
1282 static int __init nol2parity(char *s)
1283 {
1284 l2parity = 0;
1285 return 1;
1286 }
1287 __setup("nol2par", nol2parity);
1288
1289 /*
1290 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1291 * it different ways.
1292 */
1293 static inline void parity_protection_init(void)
1294 {
1295 switch (current_cpu_type()) {
1296 case CPU_24K:
1297 case CPU_34K:
1298 case CPU_74K:
1299 case CPU_1004K:
1300 {
1301 #define ERRCTL_PE 0x80000000
1302 #define ERRCTL_L2P 0x00800000
1303 unsigned long errctl;
1304 unsigned int l1parity_present, l2parity_present;
1305
1306 errctl = read_c0_ecc();
1307 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1308
1309 /* probe L1 parity support */
1310 write_c0_ecc(errctl | ERRCTL_PE);
1311 back_to_back_c0_hazard();
1312 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1313
1314 /* probe L2 parity support */
1315 write_c0_ecc(errctl|ERRCTL_L2P);
1316 back_to_back_c0_hazard();
1317 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1318
1319 if (l1parity_present && l2parity_present) {
1320 if (l1parity)
1321 errctl |= ERRCTL_PE;
1322 if (l1parity ^ l2parity)
1323 errctl |= ERRCTL_L2P;
1324 } else if (l1parity_present) {
1325 if (l1parity)
1326 errctl |= ERRCTL_PE;
1327 } else if (l2parity_present) {
1328 if (l2parity)
1329 errctl |= ERRCTL_L2P;
1330 } else {
1331 /* No parity available */
1332 }
1333
1334 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1335
1336 write_c0_ecc(errctl);
1337 back_to_back_c0_hazard();
1338 errctl = read_c0_ecc();
1339 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1340
1341 if (l1parity_present)
1342 printk(KERN_INFO "Cache parity protection %sabled\n",
1343 (errctl & ERRCTL_PE) ? "en" : "dis");
1344
1345 if (l2parity_present) {
1346 if (l1parity_present && l1parity)
1347 errctl ^= ERRCTL_L2P;
1348 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1349 (errctl & ERRCTL_L2P) ? "en" : "dis");
1350 }
1351 }
1352 break;
1353
1354 case CPU_5KC:
1355 case CPU_5KE:
1356 case CPU_LOONGSON1:
1357 write_c0_ecc(0x80000000);
1358 back_to_back_c0_hazard();
1359 /* Set the PE bit (bit 31) in the c0_errctl register. */
1360 printk(KERN_INFO "Cache parity protection %sabled\n",
1361 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1362 break;
1363 case CPU_20KC:
1364 case CPU_25KF:
1365 /* Clear the DE bit (bit 16) in the c0_status register. */
1366 printk(KERN_INFO "Enable cache parity protection for "
1367 "MIPS 20KC/25KF CPUs.\n");
1368 clear_c0_status(ST0_DE);
1369 break;
1370 default:
1371 break;
1372 }
1373 }
1374
1375 asmlinkage void cache_parity_error(void)
1376 {
1377 const int field = 2 * sizeof(unsigned long);
1378 unsigned int reg_val;
1379
1380 /* For the moment, report the problem and hang. */
1381 printk("Cache error exception:\n");
1382 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1383 reg_val = read_c0_cacheerr();
1384 printk("c0_cacheerr == %08x\n", reg_val);
1385
1386 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1387 reg_val & (1<<30) ? "secondary" : "primary",
1388 reg_val & (1<<31) ? "data" : "insn");
1389 printk("Error bits: %s%s%s%s%s%s%s\n",
1390 reg_val & (1<<29) ? "ED " : "",
1391 reg_val & (1<<28) ? "ET " : "",
1392 reg_val & (1<<26) ? "EE " : "",
1393 reg_val & (1<<25) ? "EB " : "",
1394 reg_val & (1<<24) ? "EI " : "",
1395 reg_val & (1<<23) ? "E1 " : "",
1396 reg_val & (1<<22) ? "E0 " : "");
1397 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1398
1399 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1400 if (reg_val & (1<<22))
1401 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1402
1403 if (reg_val & (1<<23))
1404 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1405 #endif
1406
1407 panic("Can't handle the cache error!");
1408 }
1409
1410 /*
1411 * SDBBP EJTAG debug exception handler.
1412 * We skip the instruction and return to the next instruction.
1413 */
1414 void ejtag_exception_handler(struct pt_regs *regs)
1415 {
1416 const int field = 2 * sizeof(unsigned long);
1417 unsigned long depc, old_epc, old_ra;
1418 unsigned int debug;
1419
1420 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1421 depc = read_c0_depc();
1422 debug = read_c0_debug();
1423 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1424 if (debug & 0x80000000) {
1425 /*
1426 * In branch delay slot.
1427 * We cheat a little bit here and use EPC to calculate the
1428 * debug return address (DEPC). EPC is restored after the
1429 * calculation.
1430 */
1431 old_epc = regs->cp0_epc;
1432 old_ra = regs->regs[31];
1433 regs->cp0_epc = depc;
1434 compute_return_epc(regs);
1435 depc = regs->cp0_epc;
1436 regs->cp0_epc = old_epc;
1437 regs->regs[31] = old_ra;
1438 } else
1439 depc += 4;
1440 write_c0_depc(depc);
1441
1442 #if 0
1443 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1444 write_c0_debug(debug | 0x100);
1445 #endif
1446 }
1447
1448 /*
1449 * NMI exception handler.
1450 * No lock; only written during early bootup by CPU 0.
1451 */
1452 static RAW_NOTIFIER_HEAD(nmi_chain);
1453
1454 int register_nmi_notifier(struct notifier_block *nb)
1455 {
1456 return raw_notifier_chain_register(&nmi_chain, nb);
1457 }
1458
1459 void __noreturn nmi_exception_handler(struct pt_regs *regs)
1460 {
1461 raw_notifier_call_chain(&nmi_chain, 0, regs);
1462 bust_spinlocks(1);
1463 printk("NMI taken!!!!\n");
1464 die("NMI", regs);
1465 }
1466
1467 #define VECTORSPACING 0x100 /* for EI/VI mode */
1468
1469 unsigned long ebase;
1470 unsigned long exception_handlers[32];
1471 unsigned long vi_handlers[64];
1472
1473 void __init *set_except_vector(int n, void *addr)
1474 {
1475 unsigned long handler = (unsigned long) addr;
1476 unsigned long old_handler = exception_handlers[n];
1477
1478 #ifdef CONFIG_CPU_MICROMIPS
1479 /*
1480 * Only the TLB handlers are cache aligned with an even
1481 * address. All other handlers are on an odd address and
1482 * require no modification. Otherwise, MIPS32 mode will
1483 * be entered when handling any TLB exceptions. That
1484 * would be bad...since we must stay in microMIPS mode.
1485 */
1486 if (!(handler & 0x1))
1487 handler |= 1;
1488 #endif
1489 exception_handlers[n] = handler;
1490 if (n == 0 && cpu_has_divec) {
1491 #ifdef CONFIG_CPU_MICROMIPS
1492 unsigned long jump_mask = ~((1 << 27) - 1);
1493 #else
1494 unsigned long jump_mask = ~((1 << 28) - 1);
1495 #endif
1496 u32 *buf = (u32 *)(ebase + 0x200);
1497 unsigned int k0 = 26;
1498 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1499 uasm_i_j(&buf, handler & ~jump_mask);
1500 uasm_i_nop(&buf);
1501 } else {
1502 UASM_i_LA(&buf, k0, handler);
1503 uasm_i_jr(&buf, k0);
1504 uasm_i_nop(&buf);
1505 }
1506 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1507 }
1508 return (void *)old_handler;
1509 }
1510
1511 static asmlinkage void do_default_vi(void)
1512 {
1513 show_regs(get_irq_regs());
1514 panic("Caught unexpected vectored interrupt.");
1515 }
1516
1517 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1518 {
1519 unsigned long handler;
1520 unsigned long old_handler = vi_handlers[n];
1521 int srssets = current_cpu_data.srsets;
1522 u16 *h;
1523 unsigned char *b;
1524
1525 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1526 BUG_ON((n < 0) && (n > 9));
1527
1528 if (addr == NULL) {
1529 handler = (unsigned long) do_default_vi;
1530 srs = 0;
1531 } else
1532 handler = (unsigned long) addr;
1533 vi_handlers[n] = handler;
1534
1535 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1536
1537 if (srs >= srssets)
1538 panic("Shadow register set %d not supported", srs);
1539
1540 if (cpu_has_veic) {
1541 if (board_bind_eic_interrupt)
1542 board_bind_eic_interrupt(n, srs);
1543 } else if (cpu_has_vint) {
1544 /* SRSMap is only defined if shadow sets are implemented */
1545 if (srssets > 1)
1546 change_c0_srsmap(0xf << n*4, srs << n*4);
1547 }
1548
1549 if (srs == 0) {
1550 /*
1551 * If no shadow set is selected then use the default handler
1552 * that does normal register saving and standard interrupt exit
1553 */
1554 extern char except_vec_vi, except_vec_vi_lui;
1555 extern char except_vec_vi_ori, except_vec_vi_end;
1556 extern char rollback_except_vec_vi;
1557 char *vec_start = (cpu_wait == r4k_wait) ?
1558 &rollback_except_vec_vi : &except_vec_vi;
1559 #ifdef CONFIG_MIPS_MT_SMTC
1560 /*
1561 * We need to provide the SMTC vectored interrupt handler
1562 * not only with the address of the handler, but with the
1563 * Status.IM bit to be masked before going there.
1564 */
1565 extern char except_vec_vi_mori;
1566 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1567 const int mori_offset = &except_vec_vi_mori - vec_start + 2;
1568 #else
1569 const int mori_offset = &except_vec_vi_mori - vec_start;
1570 #endif
1571 #endif /* CONFIG_MIPS_MT_SMTC */
1572 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1573 const int lui_offset = &except_vec_vi_lui - vec_start + 2;
1574 const int ori_offset = &except_vec_vi_ori - vec_start + 2;
1575 #else
1576 const int lui_offset = &except_vec_vi_lui - vec_start;
1577 const int ori_offset = &except_vec_vi_ori - vec_start;
1578 #endif
1579 const int handler_len = &except_vec_vi_end - vec_start;
1580
1581 if (handler_len > VECTORSPACING) {
1582 /*
1583 * Sigh... panicing won't help as the console
1584 * is probably not configured :(
1585 */
1586 panic("VECTORSPACING too small");
1587 }
1588
1589 set_handler(((unsigned long)b - ebase), vec_start,
1590 #ifdef CONFIG_CPU_MICROMIPS
1591 (handler_len - 1));
1592 #else
1593 handler_len);
1594 #endif
1595 #ifdef CONFIG_MIPS_MT_SMTC
1596 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */
1597
1598 h = (u16 *)(b + mori_offset);
1599 *h = (0x100 << n);
1600 #endif /* CONFIG_MIPS_MT_SMTC */
1601 h = (u16 *)(b + lui_offset);
1602 *h = (handler >> 16) & 0xffff;
1603 h = (u16 *)(b + ori_offset);
1604 *h = (handler & 0xffff);
1605 local_flush_icache_range((unsigned long)b,
1606 (unsigned long)(b+handler_len));
1607 }
1608 else {
1609 /*
1610 * In other cases jump directly to the interrupt handler. It
1611 * is the handler's responsibility to save registers if required
1612 * (eg hi/lo) and return from the exception using "eret".
1613 */
1614 u32 insn;
1615
1616 h = (u16 *)b;
1617 /* j handler */
1618 #ifdef CONFIG_CPU_MICROMIPS
1619 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
1620 #else
1621 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
1622 #endif
1623 h[0] = (insn >> 16) & 0xffff;
1624 h[1] = insn & 0xffff;
1625 h[2] = 0;
1626 h[3] = 0;
1627 local_flush_icache_range((unsigned long)b,
1628 (unsigned long)(b+8));
1629 }
1630
1631 return (void *)old_handler;
1632 }
1633
1634 void *set_vi_handler(int n, vi_handler_t addr)
1635 {
1636 return set_vi_srs_handler(n, addr, 0);
1637 }
1638
1639 extern void tlb_init(void);
1640 extern void flush_tlb_handlers(void);
1641
1642 /*
1643 * Timer interrupt
1644 */
1645 int cp0_compare_irq;
1646 EXPORT_SYMBOL_GPL(cp0_compare_irq);
1647 int cp0_compare_irq_shift;
1648
1649 /*
1650 * Performance counter IRQ or -1 if shared with timer
1651 */
1652 int cp0_perfcount_irq;
1653 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
1654
1655 static int __cpuinitdata noulri;
1656
1657 static int __init ulri_disable(char *s)
1658 {
1659 pr_info("Disabling ulri\n");
1660 noulri = 1;
1661
1662 return 1;
1663 }
1664 __setup("noulri", ulri_disable);
1665
1666 void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
1667 {
1668 unsigned int cpu = smp_processor_id();
1669 unsigned int status_set = ST0_CU0;
1670 unsigned int hwrena = cpu_hwrena_impl_bits;
1671 unsigned long asid = 0;
1672 #ifdef CONFIG_MIPS_MT_SMTC
1673 int secondaryTC = 0;
1674 int bootTC = (cpu == 0);
1675
1676 /*
1677 * Only do per_cpu_trap_init() for first TC of Each VPE.
1678 * Note that this hack assumes that the SMTC init code
1679 * assigns TCs consecutively and in ascending order.
1680 */
1681
1682 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1683 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1684 secondaryTC = 1;
1685 #endif /* CONFIG_MIPS_MT_SMTC */
1686
1687 /*
1688 * Disable coprocessors and select 32-bit or 64-bit addressing
1689 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1690 * flag that some firmware may have left set and the TS bit (for
1691 * IP27). Set XX for ISA IV code to work.
1692 */
1693 #ifdef CONFIG_64BIT
1694 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1695 #endif
1696 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
1697 status_set |= ST0_XX;
1698 if (cpu_has_dsp)
1699 status_set |= ST0_MX;
1700
1701 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1702 status_set);
1703
1704 if (cpu_has_mips_r2)
1705 hwrena |= 0x0000000f;
1706
1707 if (!noulri && cpu_has_userlocal)
1708 hwrena |= (1 << 29);
1709
1710 if (hwrena)
1711 write_c0_hwrena(hwrena);
1712
1713 #ifdef CONFIG_MIPS_MT_SMTC
1714 if (!secondaryTC) {
1715 #endif /* CONFIG_MIPS_MT_SMTC */
1716
1717 if (cpu_has_veic || cpu_has_vint) {
1718 unsigned long sr = set_c0_status(ST0_BEV);
1719 write_c0_ebase(ebase);
1720 write_c0_status(sr);
1721 /* Setting vector spacing enables EI/VI mode */
1722 change_c0_intctl(0x3e0, VECTORSPACING);
1723 }
1724 if (cpu_has_divec) {
1725 if (cpu_has_mipsmt) {
1726 unsigned int vpflags = dvpe();
1727 set_c0_cause(CAUSEF_IV);
1728 evpe(vpflags);
1729 } else
1730 set_c0_cause(CAUSEF_IV);
1731 }
1732
1733 /*
1734 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
1735 *
1736 * o read IntCtl.IPTI to determine the timer interrupt
1737 * o read IntCtl.IPPCI to determine the performance counter interrupt
1738 */
1739 if (cpu_has_mips_r2) {
1740 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
1741 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
1742 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
1743 if (cp0_perfcount_irq == cp0_compare_irq)
1744 cp0_perfcount_irq = -1;
1745 } else {
1746 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
1747 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
1748 cp0_perfcount_irq = -1;
1749 }
1750
1751 #ifdef CONFIG_MIPS_MT_SMTC
1752 }
1753 #endif /* CONFIG_MIPS_MT_SMTC */
1754
1755 asid = ASID_FIRST_VERSION;
1756 cpu_data[cpu].asid_cache = asid;
1757 TLBMISS_HANDLER_SETUP();
1758
1759 atomic_inc(&init_mm.mm_count);
1760 current->active_mm = &init_mm;
1761 BUG_ON(current->mm);
1762 enter_lazy_tlb(&init_mm, current);
1763
1764 #ifdef CONFIG_MIPS_MT_SMTC
1765 if (bootTC) {
1766 #endif /* CONFIG_MIPS_MT_SMTC */
1767 /* Boot CPU's cache setup in setup_arch(). */
1768 if (!is_boot_cpu)
1769 cpu_cache_init();
1770 tlb_init();
1771 #ifdef CONFIG_MIPS_MT_SMTC
1772 } else if (!secondaryTC) {
1773 /*
1774 * First TC in non-boot VPE must do subset of tlb_init()
1775 * for MMU countrol registers.
1776 */
1777 write_c0_pagemask(PM_DEFAULT_MASK);
1778 write_c0_wired(0);
1779 }
1780 #endif /* CONFIG_MIPS_MT_SMTC */
1781 TLBMISS_HANDLER_SETUP();
1782 }
1783
1784 /* Install CPU exception handler */
1785 void __cpuinit set_handler(unsigned long offset, void *addr, unsigned long size)
1786 {
1787 #ifdef CONFIG_CPU_MICROMIPS
1788 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
1789 #else
1790 memcpy((void *)(ebase + offset), addr, size);
1791 #endif
1792 local_flush_icache_range(ebase + offset, ebase + offset + size);
1793 }
1794
1795 static char panic_null_cerr[] __cpuinitdata =
1796 "Trying to set NULL cache error exception handler";
1797
1798 /*
1799 * Install uncached CPU exception handler.
1800 * This is suitable only for the cache error exception which is the only
1801 * exception handler that is being run uncached.
1802 */
1803 void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
1804 unsigned long size)
1805 {
1806 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
1807
1808 if (!addr)
1809 panic(panic_null_cerr);
1810
1811 memcpy((void *)(uncached_ebase + offset), addr, size);
1812 }
1813
1814 static int __initdata rdhwr_noopt;
1815 static int __init set_rdhwr_noopt(char *str)
1816 {
1817 rdhwr_noopt = 1;
1818 return 1;
1819 }
1820
1821 __setup("rdhwr_noopt", set_rdhwr_noopt);
1822
1823 void __init trap_init(void)
1824 {
1825 extern char except_vec3_generic;
1826 extern char except_vec4;
1827 extern char except_vec3_r4000;
1828 unsigned long i;
1829 int rollback;
1830
1831 check_wait();
1832 rollback = (cpu_wait == r4k_wait);
1833
1834 #if defined(CONFIG_KGDB)
1835 if (kgdb_early_setup)
1836 return; /* Already done */
1837 #endif
1838
1839 if (cpu_has_veic || cpu_has_vint) {
1840 unsigned long size = 0x200 + VECTORSPACING*64;
1841 ebase = (unsigned long)
1842 __alloc_bootmem(size, 1 << fls(size), 0);
1843 } else {
1844 ebase = CKSEG0;
1845 if (cpu_has_mips_r2)
1846 ebase += (read_c0_ebase() & 0x3ffff000);
1847 }
1848
1849 if (board_ebase_setup)
1850 board_ebase_setup();
1851 per_cpu_trap_init(true);
1852
1853 /*
1854 * Copy the generic exception handlers to their final destination.
1855 * This will be overriden later as suitable for a particular
1856 * configuration.
1857 */
1858 set_handler(0x180, &except_vec3_generic, 0x80);
1859
1860 /*
1861 * Setup default vectors
1862 */
1863 for (i = 0; i <= 31; i++)
1864 set_except_vector(i, handle_reserved);
1865
1866 /*
1867 * Copy the EJTAG debug exception vector handler code to it's final
1868 * destination.
1869 */
1870 if (cpu_has_ejtag && board_ejtag_handler_setup)
1871 board_ejtag_handler_setup();
1872
1873 /*
1874 * Only some CPUs have the watch exceptions.
1875 */
1876 if (cpu_has_watch)
1877 set_except_vector(23, handle_watch);
1878
1879 /*
1880 * Initialise interrupt handlers
1881 */
1882 if (cpu_has_veic || cpu_has_vint) {
1883 int nvec = cpu_has_veic ? 64 : 8;
1884 for (i = 0; i < nvec; i++)
1885 set_vi_handler(i, NULL);
1886 }
1887 else if (cpu_has_divec)
1888 set_handler(0x200, &except_vec4, 0x8);
1889
1890 /*
1891 * Some CPUs can enable/disable for cache parity detection, but does
1892 * it different ways.
1893 */
1894 parity_protection_init();
1895
1896 /*
1897 * The Data Bus Errors / Instruction Bus Errors are signaled
1898 * by external hardware. Therefore these two exceptions
1899 * may have board specific handlers.
1900 */
1901 if (board_be_init)
1902 board_be_init();
1903
1904 set_except_vector(0, rollback ? rollback_handle_int : handle_int);
1905 set_except_vector(1, handle_tlbm);
1906 set_except_vector(2, handle_tlbl);
1907 set_except_vector(3, handle_tlbs);
1908
1909 set_except_vector(4, handle_adel);
1910 set_except_vector(5, handle_ades);
1911
1912 set_except_vector(6, handle_ibe);
1913 set_except_vector(7, handle_dbe);
1914
1915 set_except_vector(8, handle_sys);
1916 set_except_vector(9, handle_bp);
1917 set_except_vector(10, rdhwr_noopt ? handle_ri :
1918 (cpu_has_vtag_icache ?
1919 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
1920 set_except_vector(11, handle_cpu);
1921 set_except_vector(12, handle_ov);
1922 set_except_vector(13, handle_tr);
1923
1924 if (current_cpu_type() == CPU_R6000 ||
1925 current_cpu_type() == CPU_R6000A) {
1926 /*
1927 * The R6000 is the only R-series CPU that features a machine
1928 * check exception (similar to the R4000 cache error) and
1929 * unaligned ldc1/sdc1 exception. The handlers have not been
1930 * written yet. Well, anyway there is no R6000 machine on the
1931 * current list of targets for Linux/MIPS.
1932 * (Duh, crap, there is someone with a triple R6k machine)
1933 */
1934 //set_except_vector(14, handle_mc);
1935 //set_except_vector(15, handle_ndc);
1936 }
1937
1938
1939 if (board_nmi_handler_setup)
1940 board_nmi_handler_setup();
1941
1942 if (cpu_has_fpu && !cpu_has_nofpuex)
1943 set_except_vector(15, handle_fpe);
1944
1945 set_except_vector(22, handle_mdmx);
1946
1947 if (cpu_has_mcheck)
1948 set_except_vector(24, handle_mcheck);
1949
1950 if (cpu_has_mipsmt)
1951 set_except_vector(25, handle_mt);
1952
1953 set_except_vector(26, handle_dsp);
1954
1955 if (board_cache_error_setup)
1956 board_cache_error_setup();
1957
1958 if (cpu_has_vce)
1959 /* Special exception: R4[04]00 uses also the divec space. */
1960 set_handler(0x180, &except_vec3_r4000, 0x100);
1961 else if (cpu_has_4kex)
1962 set_handler(0x180, &except_vec3_generic, 0x80);
1963 else
1964 set_handler(0x080, &except_vec3_generic, 0x80);
1965
1966 local_flush_icache_range(ebase, ebase + 0x400);
1967 flush_tlb_handlers();
1968
1969 sort_extable(__start___dbe_table, __stop___dbe_table);
1970
1971 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
1972 }
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