2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
13 * Copyright (C) 2014, Imagination Technologies Ltd.
15 #include <linux/bug.h>
16 #include <linux/compiler.h>
17 #include <linux/context_tracking.h>
18 #include <linux/kexec.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
23 #include <linux/sched.h>
24 #include <linux/smp.h>
25 #include <linux/spinlock.h>
26 #include <linux/kallsyms.h>
27 #include <linux/bootmem.h>
28 #include <linux/interrupt.h>
29 #include <linux/ptrace.h>
30 #include <linux/kgdb.h>
31 #include <linux/kdebug.h>
32 #include <linux/kprobes.h>
33 #include <linux/notifier.h>
34 #include <linux/kdb.h>
35 #include <linux/irq.h>
36 #include <linux/perf_event.h>
38 #include <asm/bootinfo.h>
39 #include <asm/branch.h>
40 #include <asm/break.h>
43 #include <asm/cpu-type.h>
46 #include <asm/fpu_emulator.h>
48 #include <asm/mipsregs.h>
49 #include <asm/mipsmtregs.h>
50 #include <asm/module.h>
52 #include <asm/pgtable.h>
53 #include <asm/ptrace.h>
54 #include <asm/sections.h>
55 #include <asm/tlbdebug.h>
56 #include <asm/traps.h>
57 #include <asm/uaccess.h>
58 #include <asm/watch.h>
59 #include <asm/mmu_context.h>
60 #include <asm/types.h>
61 #include <asm/stacktrace.h>
64 extern void check_wait(void);
65 extern asmlinkage
void rollback_handle_int(void);
66 extern asmlinkage
void handle_int(void);
67 extern u32 handle_tlbl
[];
68 extern u32 handle_tlbs
[];
69 extern u32 handle_tlbm
[];
70 extern asmlinkage
void handle_adel(void);
71 extern asmlinkage
void handle_ades(void);
72 extern asmlinkage
void handle_ibe(void);
73 extern asmlinkage
void handle_dbe(void);
74 extern asmlinkage
void handle_sys(void);
75 extern asmlinkage
void handle_bp(void);
76 extern asmlinkage
void handle_ri(void);
77 extern asmlinkage
void handle_ri_rdhwr_vivt(void);
78 extern asmlinkage
void handle_ri_rdhwr(void);
79 extern asmlinkage
void handle_cpu(void);
80 extern asmlinkage
void handle_ov(void);
81 extern asmlinkage
void handle_tr(void);
82 extern asmlinkage
void handle_msa_fpe(void);
83 extern asmlinkage
void handle_fpe(void);
84 extern asmlinkage
void handle_ftlb(void);
85 extern asmlinkage
void handle_msa(void);
86 extern asmlinkage
void handle_mdmx(void);
87 extern asmlinkage
void handle_watch(void);
88 extern asmlinkage
void handle_mt(void);
89 extern asmlinkage
void handle_dsp(void);
90 extern asmlinkage
void handle_mcheck(void);
91 extern asmlinkage
void handle_reserved(void);
93 void (*board_be_init
)(void);
94 int (*board_be_handler
)(struct pt_regs
*regs
, int is_fixup
);
95 void (*board_nmi_handler_setup
)(void);
96 void (*board_ejtag_handler_setup
)(void);
97 void (*board_bind_eic_interrupt
)(int irq
, int regset
);
98 void (*board_ebase_setup
)(void);
99 void(*board_cache_error_setup
)(void);
101 static void show_raw_backtrace(unsigned long reg29
)
103 unsigned long *sp
= (unsigned long *)(reg29
& ~3);
106 printk("Call Trace:");
107 #ifdef CONFIG_KALLSYMS
110 while (!kstack_end(sp
)) {
111 unsigned long __user
*p
=
112 (unsigned long __user
*)(unsigned long)sp
++;
113 if (__get_user(addr
, p
)) {
114 printk(" (Bad stack address)");
117 if (__kernel_text_address(addr
))
123 #ifdef CONFIG_KALLSYMS
125 static int __init
set_raw_show_trace(char *str
)
130 __setup("raw_show_trace", set_raw_show_trace
);
133 static void show_backtrace(struct task_struct
*task
, const struct pt_regs
*regs
)
135 unsigned long sp
= regs
->regs
[29];
136 unsigned long ra
= regs
->regs
[31];
137 unsigned long pc
= regs
->cp0_epc
;
142 if (raw_show_trace
|| !__kernel_text_address(pc
)) {
143 show_raw_backtrace(sp
);
146 printk("Call Trace:\n");
149 pc
= unwind_stack(task
, &sp
, pc
, &ra
);
155 * This routine abuses get_user()/put_user() to reference pointers
156 * with at least a bit of error checking ...
158 static void show_stacktrace(struct task_struct
*task
,
159 const struct pt_regs
*regs
)
161 const int field
= 2 * sizeof(unsigned long);
164 unsigned long __user
*sp
= (unsigned long __user
*)regs
->regs
[29];
168 while ((unsigned long) sp
& (PAGE_SIZE
- 1)) {
169 if (i
&& ((i
% (64 / field
)) == 0))
176 if (__get_user(stackdata
, sp
++)) {
177 printk(" (Bad stack address)");
181 printk(" %0*lx", field
, stackdata
);
185 show_backtrace(task
, regs
);
188 void show_stack(struct task_struct
*task
, unsigned long *sp
)
192 regs
.regs
[29] = (unsigned long)sp
;
196 if (task
&& task
!= current
) {
197 regs
.regs
[29] = task
->thread
.reg29
;
199 regs
.cp0_epc
= task
->thread
.reg31
;
200 #ifdef CONFIG_KGDB_KDB
201 } else if (atomic_read(&kgdb_active
) != -1 &&
203 memcpy(®s
, kdb_current_regs
, sizeof(regs
));
204 #endif /* CONFIG_KGDB_KDB */
206 prepare_frametrace(®s
);
209 show_stacktrace(task
, ®s
);
212 static void show_code(unsigned int __user
*pc
)
215 unsigned short __user
*pc16
= NULL
;
219 if ((unsigned long)pc
& 1)
220 pc16
= (unsigned short __user
*)((unsigned long)pc
& ~1);
221 for(i
= -3 ; i
< 6 ; i
++) {
223 if (pc16
? __get_user(insn
, pc16
+ i
) : __get_user(insn
, pc
+ i
)) {
224 printk(" (Bad address in epc)\n");
227 printk("%c%0*x%c", (i
?' ':'<'), pc16
? 4 : 8, insn
, (i
?' ':'>'));
231 static void __show_regs(const struct pt_regs
*regs
)
233 const int field
= 2 * sizeof(unsigned long);
234 unsigned int cause
= regs
->cp0_cause
;
237 show_regs_print_info(KERN_DEFAULT
);
240 * Saved main processor registers
242 for (i
= 0; i
< 32; ) {
246 printk(" %0*lx", field
, 0UL);
247 else if (i
== 26 || i
== 27)
248 printk(" %*s", field
, "");
250 printk(" %0*lx", field
, regs
->regs
[i
]);
257 #ifdef CONFIG_CPU_HAS_SMARTMIPS
258 printk("Acx : %0*lx\n", field
, regs
->acx
);
260 printk("Hi : %0*lx\n", field
, regs
->hi
);
261 printk("Lo : %0*lx\n", field
, regs
->lo
);
264 * Saved cp0 registers
266 printk("epc : %0*lx %pS\n", field
, regs
->cp0_epc
,
267 (void *) regs
->cp0_epc
);
268 printk(" %s\n", print_tainted());
269 printk("ra : %0*lx %pS\n", field
, regs
->regs
[31],
270 (void *) regs
->regs
[31]);
272 printk("Status: %08x ", (uint32_t) regs
->cp0_status
);
275 if (regs
->cp0_status
& ST0_KUO
)
277 if (regs
->cp0_status
& ST0_IEO
)
279 if (regs
->cp0_status
& ST0_KUP
)
281 if (regs
->cp0_status
& ST0_IEP
)
283 if (regs
->cp0_status
& ST0_KUC
)
285 if (regs
->cp0_status
& ST0_IEC
)
287 } else if (cpu_has_4kex
) {
288 if (regs
->cp0_status
& ST0_KX
)
290 if (regs
->cp0_status
& ST0_SX
)
292 if (regs
->cp0_status
& ST0_UX
)
294 switch (regs
->cp0_status
& ST0_KSU
) {
299 printk("SUPERVISOR ");
308 if (regs
->cp0_status
& ST0_ERL
)
310 if (regs
->cp0_status
& ST0_EXL
)
312 if (regs
->cp0_status
& ST0_IE
)
317 printk("Cause : %08x\n", cause
);
319 cause
= (cause
& CAUSEF_EXCCODE
) >> CAUSEB_EXCCODE
;
320 if (1 <= cause
&& cause
<= 5)
321 printk("BadVA : %0*lx\n", field
, regs
->cp0_badvaddr
);
323 printk("PrId : %08x (%s)\n", read_c0_prid(),
328 * FIXME: really the generic show_regs should take a const pointer argument.
330 void show_regs(struct pt_regs
*regs
)
332 __show_regs((struct pt_regs
*)regs
);
335 void show_registers(struct pt_regs
*regs
)
337 const int field
= 2 * sizeof(unsigned long);
338 mm_segment_t old_fs
= get_fs();
342 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
343 current
->comm
, current
->pid
, current_thread_info(), current
,
344 field
, current_thread_info()->tp_value
);
345 if (cpu_has_userlocal
) {
348 tls
= read_c0_userlocal();
349 if (tls
!= current_thread_info()->tp_value
)
350 printk("*HwTLS: %0*lx\n", field
, tls
);
353 if (!user_mode(regs
))
354 /* Necessary for getting the correct stack content */
356 show_stacktrace(current
, regs
);
357 show_code((unsigned int __user
*) regs
->cp0_epc
);
362 static int regs_to_trapnr(struct pt_regs
*regs
)
364 return (regs
->cp0_cause
>> 2) & 0x1f;
367 static DEFINE_RAW_SPINLOCK(die_lock
);
369 void __noreturn
die(const char *str
, struct pt_regs
*regs
)
371 static int die_counter
;
376 if (notify_die(DIE_OOPS
, str
, regs
, 0, regs_to_trapnr(regs
),
377 SIGSEGV
) == NOTIFY_STOP
)
381 raw_spin_lock_irq(&die_lock
);
384 printk("%s[#%d]:\n", str
, ++die_counter
);
385 show_registers(regs
);
386 add_taint(TAINT_DIE
, LOCKDEP_NOW_UNRELIABLE
);
387 raw_spin_unlock_irq(&die_lock
);
392 panic("Fatal exception in interrupt");
395 printk(KERN_EMERG
"Fatal exception: panic in 5 seconds");
397 panic("Fatal exception");
400 if (regs
&& kexec_should_crash(current
))
406 extern struct exception_table_entry __start___dbe_table
[];
407 extern struct exception_table_entry __stop___dbe_table
[];
410 " .section __dbe_table, \"a\"\n"
413 /* Given an address, look for it in the exception tables. */
414 static const struct exception_table_entry
*search_dbe_tables(unsigned long addr
)
416 const struct exception_table_entry
*e
;
418 e
= search_extable(__start___dbe_table
, __stop___dbe_table
- 1, addr
);
420 e
= search_module_dbetables(addr
);
424 asmlinkage
void do_be(struct pt_regs
*regs
)
426 const int field
= 2 * sizeof(unsigned long);
427 const struct exception_table_entry
*fixup
= NULL
;
428 int data
= regs
->cp0_cause
& 4;
429 int action
= MIPS_BE_FATAL
;
430 enum ctx_state prev_state
;
432 prev_state
= exception_enter();
433 /* XXX For now. Fixme, this searches the wrong table ... */
434 if (data
&& !user_mode(regs
))
435 fixup
= search_dbe_tables(exception_epc(regs
));
438 action
= MIPS_BE_FIXUP
;
440 if (board_be_handler
)
441 action
= board_be_handler(regs
, fixup
!= NULL
);
444 case MIPS_BE_DISCARD
:
448 regs
->cp0_epc
= fixup
->nextinsn
;
457 * Assume it would be too dangerous to continue ...
459 printk(KERN_ALERT
"%s bus error, epc == %0*lx, ra == %0*lx\n",
460 data
? "Data" : "Instruction",
461 field
, regs
->cp0_epc
, field
, regs
->regs
[31]);
462 if (notify_die(DIE_OOPS
, "bus error", regs
, 0, regs_to_trapnr(regs
),
463 SIGBUS
) == NOTIFY_STOP
)
466 die_if_kernel("Oops", regs
);
467 force_sig(SIGBUS
, current
);
470 exception_exit(prev_state
);
474 * ll/sc, rdhwr, sync emulation
477 #define OPCODE 0xfc000000
478 #define BASE 0x03e00000
479 #define RT 0x001f0000
480 #define OFFSET 0x0000ffff
481 #define LL 0xc0000000
482 #define SC 0xe0000000
483 #define SPEC0 0x00000000
484 #define SPEC3 0x7c000000
485 #define RD 0x0000f800
486 #define FUNC 0x0000003f
487 #define SYNC 0x0000000f
488 #define RDHWR 0x0000003b
490 /* microMIPS definitions */
491 #define MM_POOL32A_FUNC 0xfc00ffff
492 #define MM_RDHWR 0x00006b3c
493 #define MM_RS 0x001f0000
494 #define MM_RT 0x03e00000
497 * The ll_bit is cleared by r*_switch.S
501 struct task_struct
*ll_task
;
503 static inline int simulate_ll(struct pt_regs
*regs
, unsigned int opcode
)
505 unsigned long value
, __user
*vaddr
;
509 * analyse the ll instruction that just caused a ri exception
510 * and put the referenced address to addr.
513 /* sign extend offset */
514 offset
= opcode
& OFFSET
;
518 vaddr
= (unsigned long __user
*)
519 ((unsigned long)(regs
->regs
[(opcode
& BASE
) >> 21]) + offset
);
521 if ((unsigned long)vaddr
& 3)
523 if (get_user(value
, vaddr
))
528 if (ll_task
== NULL
|| ll_task
== current
) {
537 regs
->regs
[(opcode
& RT
) >> 16] = value
;
542 static inline int simulate_sc(struct pt_regs
*regs
, unsigned int opcode
)
544 unsigned long __user
*vaddr
;
549 * analyse the sc instruction that just caused a ri exception
550 * and put the referenced address to addr.
553 /* sign extend offset */
554 offset
= opcode
& OFFSET
;
558 vaddr
= (unsigned long __user
*)
559 ((unsigned long)(regs
->regs
[(opcode
& BASE
) >> 21]) + offset
);
560 reg
= (opcode
& RT
) >> 16;
562 if ((unsigned long)vaddr
& 3)
567 if (ll_bit
== 0 || ll_task
!= current
) {
575 if (put_user(regs
->regs
[reg
], vaddr
))
584 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
585 * opcodes are supposed to result in coprocessor unusable exceptions if
586 * executed on ll/sc-less processors. That's the theory. In practice a
587 * few processors such as NEC's VR4100 throw reserved instruction exceptions
588 * instead, so we're doing the emulation thing in both exception handlers.
590 static int simulate_llsc(struct pt_regs
*regs
, unsigned int opcode
)
592 if ((opcode
& OPCODE
) == LL
) {
593 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS
,
595 return simulate_ll(regs
, opcode
);
597 if ((opcode
& OPCODE
) == SC
) {
598 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS
,
600 return simulate_sc(regs
, opcode
);
603 return -1; /* Must be something else ... */
607 * Simulate trapping 'rdhwr' instructions to provide user accessible
608 * registers not implemented in hardware.
610 static int simulate_rdhwr(struct pt_regs
*regs
, int rd
, int rt
)
612 struct thread_info
*ti
= task_thread_info(current
);
614 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS
,
617 case 0: /* CPU number */
618 regs
->regs
[rt
] = smp_processor_id();
620 case 1: /* SYNCI length */
621 regs
->regs
[rt
] = min(current_cpu_data
.dcache
.linesz
,
622 current_cpu_data
.icache
.linesz
);
624 case 2: /* Read count register */
625 regs
->regs
[rt
] = read_c0_count();
627 case 3: /* Count register resolution */
628 switch (current_cpu_type()) {
638 regs
->regs
[rt
] = ti
->tp_value
;
645 static int simulate_rdhwr_normal(struct pt_regs
*regs
, unsigned int opcode
)
647 if ((opcode
& OPCODE
) == SPEC3
&& (opcode
& FUNC
) == RDHWR
) {
648 int rd
= (opcode
& RD
) >> 11;
649 int rt
= (opcode
& RT
) >> 16;
651 simulate_rdhwr(regs
, rd
, rt
);
659 static int simulate_rdhwr_mm(struct pt_regs
*regs
, unsigned short opcode
)
661 if ((opcode
& MM_POOL32A_FUNC
) == MM_RDHWR
) {
662 int rd
= (opcode
& MM_RS
) >> 16;
663 int rt
= (opcode
& MM_RT
) >> 21;
664 simulate_rdhwr(regs
, rd
, rt
);
672 static int simulate_sync(struct pt_regs
*regs
, unsigned int opcode
)
674 if ((opcode
& OPCODE
) == SPEC0
&& (opcode
& FUNC
) == SYNC
) {
675 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS
,
680 return -1; /* Must be something else ... */
683 asmlinkage
void do_ov(struct pt_regs
*regs
)
685 enum ctx_state prev_state
;
688 prev_state
= exception_enter();
689 die_if_kernel("Integer overflow", regs
);
691 info
.si_code
= FPE_INTOVF
;
692 info
.si_signo
= SIGFPE
;
694 info
.si_addr
= (void __user
*) regs
->cp0_epc
;
695 force_sig_info(SIGFPE
, &info
, current
);
696 exception_exit(prev_state
);
699 int process_fpemu_return(int sig
, void __user
*fault_addr
)
701 if (sig
== SIGSEGV
|| sig
== SIGBUS
) {
702 struct siginfo si
= {0};
703 si
.si_addr
= fault_addr
;
705 if (sig
== SIGSEGV
) {
706 if (find_vma(current
->mm
, (unsigned long)fault_addr
))
707 si
.si_code
= SEGV_ACCERR
;
709 si
.si_code
= SEGV_MAPERR
;
711 si
.si_code
= BUS_ADRERR
;
713 force_sig_info(sig
, &si
, current
);
716 force_sig(sig
, current
);
724 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
726 asmlinkage
void do_fpe(struct pt_regs
*regs
, unsigned long fcr31
)
728 enum ctx_state prev_state
;
729 siginfo_t info
= {0};
731 prev_state
= exception_enter();
732 if (notify_die(DIE_FP
, "FP exception", regs
, 0, regs_to_trapnr(regs
),
733 SIGFPE
) == NOTIFY_STOP
)
735 die_if_kernel("FP exception in kernel code", regs
);
737 if (fcr31
& FPU_CSR_UNI_X
) {
739 void __user
*fault_addr
= NULL
;
742 * Unimplemented operation exception. If we've got the full
743 * software emulator on-board, let's use it...
745 * Force FPU to dump state into task/thread context. We're
746 * moving a lot of data here for what is probably a single
747 * instruction, but the alternative is to pre-decode the FP
748 * register operands before invoking the emulator, which seems
749 * a bit extreme for what should be an infrequent event.
751 /* Ensure 'resume' not overwrite saved fp context again. */
754 /* Run the emulator */
755 sig
= fpu_emulator_cop1Handler(regs
, ¤t
->thread
.fpu
, 1,
759 * We can't allow the emulated instruction to leave any of
760 * the cause bit set in $fcr31.
762 current
->thread
.fpu
.fcr31
&= ~FPU_CSR_ALL_X
;
764 /* Restore the hardware register state */
765 own_fpu(1); /* Using the FPU again. */
767 /* If something went wrong, signal */
768 process_fpemu_return(sig
, fault_addr
);
771 } else if (fcr31
& FPU_CSR_INV_X
)
772 info
.si_code
= FPE_FLTINV
;
773 else if (fcr31
& FPU_CSR_DIV_X
)
774 info
.si_code
= FPE_FLTDIV
;
775 else if (fcr31
& FPU_CSR_OVF_X
)
776 info
.si_code
= FPE_FLTOVF
;
777 else if (fcr31
& FPU_CSR_UDF_X
)
778 info
.si_code
= FPE_FLTUND
;
779 else if (fcr31
& FPU_CSR_INE_X
)
780 info
.si_code
= FPE_FLTRES
;
782 info
.si_code
= __SI_FAULT
;
783 info
.si_signo
= SIGFPE
;
785 info
.si_addr
= (void __user
*) regs
->cp0_epc
;
786 force_sig_info(SIGFPE
, &info
, current
);
789 exception_exit(prev_state
);
792 static void do_trap_or_bp(struct pt_regs
*regs
, unsigned int code
,
798 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
799 if (kgdb_ll_trap(DIE_TRAP
, str
, regs
, code
, regs_to_trapnr(regs
), SIGTRAP
) == NOTIFY_STOP
)
801 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
803 if (notify_die(DIE_TRAP
, str
, regs
, code
, regs_to_trapnr(regs
),
804 SIGTRAP
) == NOTIFY_STOP
)
808 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
809 * insns, even for trap and break codes that indicate arithmetic
810 * failures. Weird ...
811 * But should we continue the brokenness??? --macro
816 scnprintf(b
, sizeof(b
), "%s instruction in kernel code", str
);
817 die_if_kernel(b
, regs
);
818 if (code
== BRK_DIVZERO
)
819 info
.si_code
= FPE_INTDIV
;
821 info
.si_code
= FPE_INTOVF
;
822 info
.si_signo
= SIGFPE
;
824 info
.si_addr
= (void __user
*) regs
->cp0_epc
;
825 force_sig_info(SIGFPE
, &info
, current
);
828 die_if_kernel("Kernel bug detected", regs
);
829 force_sig(SIGTRAP
, current
);
833 * Address errors may be deliberately induced by the FPU
834 * emulator to retake control of the CPU after executing the
835 * instruction in the delay slot of an emulated branch.
837 * Terminate if exception was recognized as a delay slot return
838 * otherwise handle as normal.
840 if (do_dsemulret(regs
))
843 die_if_kernel("Math emu break/trap", regs
);
844 force_sig(SIGTRAP
, current
);
847 scnprintf(b
, sizeof(b
), "%s instruction in kernel code", str
);
848 die_if_kernel(b
, regs
);
849 force_sig(SIGTRAP
, current
);
853 asmlinkage
void do_bp(struct pt_regs
*regs
)
855 unsigned int opcode
, bcode
;
856 enum ctx_state prev_state
;
862 if (!user_mode(regs
))
865 prev_state
= exception_enter();
866 if (get_isa16_mode(regs
->cp0_epc
)) {
868 epc
= exception_epc(regs
);
870 if ((__get_user(instr
[0], (u16 __user
*)msk_isa16_mode(epc
)) ||
871 (__get_user(instr
[1], (u16 __user
*)msk_isa16_mode(epc
+ 2)))))
873 opcode
= (instr
[0] << 16) | instr
[1];
876 if (__get_user(instr
[0],
877 (u16 __user
*)msk_isa16_mode(epc
)))
879 bcode
= (instr
[0] >> 6) & 0x3f;
880 do_trap_or_bp(regs
, bcode
, "Break");
884 if (__get_user(opcode
,
885 (unsigned int __user
*) exception_epc(regs
)))
890 * There is the ancient bug in the MIPS assemblers that the break
891 * code starts left to bit 16 instead to bit 6 in the opcode.
892 * Gas is bug-compatible, but not always, grrr...
893 * We handle both cases with a simple heuristics. --macro
895 bcode
= ((opcode
>> 6) & ((1 << 20) - 1));
896 if (bcode
>= (1 << 10))
900 * notify the kprobe handlers, if instruction is likely to
905 if (notify_die(DIE_BREAK
, "debug", regs
, bcode
,
906 regs_to_trapnr(regs
), SIGTRAP
) == NOTIFY_STOP
)
910 case BRK_KPROBE_SSTEPBP
:
911 if (notify_die(DIE_SSTEPBP
, "single_step", regs
, bcode
,
912 regs_to_trapnr(regs
), SIGTRAP
) == NOTIFY_STOP
)
920 do_trap_or_bp(regs
, bcode
, "Break");
924 exception_exit(prev_state
);
928 force_sig(SIGSEGV
, current
);
932 asmlinkage
void do_tr(struct pt_regs
*regs
)
934 u32 opcode
, tcode
= 0;
935 enum ctx_state prev_state
;
938 unsigned long epc
= msk_isa16_mode(exception_epc(regs
));
941 if (!user_mode(regs
))
944 prev_state
= exception_enter();
945 if (get_isa16_mode(regs
->cp0_epc
)) {
946 if (__get_user(instr
[0], (u16 __user
*)(epc
+ 0)) ||
947 __get_user(instr
[1], (u16 __user
*)(epc
+ 2)))
949 opcode
= (instr
[0] << 16) | instr
[1];
950 /* Immediate versions don't provide a code. */
951 if (!(opcode
& OPCODE
))
952 tcode
= (opcode
>> 12) & ((1 << 4) - 1);
954 if (__get_user(opcode
, (u32 __user
*)epc
))
956 /* Immediate versions don't provide a code. */
957 if (!(opcode
& OPCODE
))
958 tcode
= (opcode
>> 6) & ((1 << 10) - 1);
961 do_trap_or_bp(regs
, tcode
, "Trap");
965 exception_exit(prev_state
);
969 force_sig(SIGSEGV
, current
);
973 asmlinkage
void do_ri(struct pt_regs
*regs
)
975 unsigned int __user
*epc
= (unsigned int __user
*)exception_epc(regs
);
976 unsigned long old_epc
= regs
->cp0_epc
;
977 unsigned long old31
= regs
->regs
[31];
978 enum ctx_state prev_state
;
979 unsigned int opcode
= 0;
982 prev_state
= exception_enter();
983 if (notify_die(DIE_RI
, "RI Fault", regs
, 0, regs_to_trapnr(regs
),
984 SIGILL
) == NOTIFY_STOP
)
987 die_if_kernel("Reserved instruction in kernel code", regs
);
989 if (unlikely(compute_return_epc(regs
) < 0))
992 if (get_isa16_mode(regs
->cp0_epc
)) {
993 unsigned short mmop
[2] = { 0 };
995 if (unlikely(get_user(mmop
[0], epc
) < 0))
997 if (unlikely(get_user(mmop
[1], epc
) < 0))
999 opcode
= (mmop
[0] << 16) | mmop
[1];
1002 status
= simulate_rdhwr_mm(regs
, opcode
);
1004 if (unlikely(get_user(opcode
, epc
) < 0))
1007 if (!cpu_has_llsc
&& status
< 0)
1008 status
= simulate_llsc(regs
, opcode
);
1011 status
= simulate_rdhwr_normal(regs
, opcode
);
1014 status
= simulate_sync(regs
, opcode
);
1020 if (unlikely(status
> 0)) {
1021 regs
->cp0_epc
= old_epc
; /* Undo skip-over. */
1022 regs
->regs
[31] = old31
;
1023 force_sig(status
, current
);
1027 exception_exit(prev_state
);
1031 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
1032 * emulated more than some threshold number of instructions, force migration to
1033 * a "CPU" that has FP support.
1035 static void mt_ase_fp_affinity(void)
1037 #ifdef CONFIG_MIPS_MT_FPAFF
1038 if (mt_fpemul_threshold
> 0 &&
1039 ((current
->thread
.emulated_fp
++ > mt_fpemul_threshold
))) {
1041 * If there's no FPU present, or if the application has already
1042 * restricted the allowed set to exclude any CPUs with FPUs,
1043 * we'll skip the procedure.
1045 if (cpus_intersects(current
->cpus_allowed
, mt_fpu_cpumask
)) {
1048 current
->thread
.user_cpus_allowed
1049 = current
->cpus_allowed
;
1050 cpus_and(tmask
, current
->cpus_allowed
,
1052 set_cpus_allowed_ptr(current
, &tmask
);
1053 set_thread_flag(TIF_FPUBOUND
);
1056 #endif /* CONFIG_MIPS_MT_FPAFF */
1060 * No lock; only written during early bootup by CPU 0.
1062 static RAW_NOTIFIER_HEAD(cu2_chain
);
1064 int __ref
register_cu2_notifier(struct notifier_block
*nb
)
1066 return raw_notifier_chain_register(&cu2_chain
, nb
);
1069 int cu2_notifier_call_chain(unsigned long val
, void *v
)
1071 return raw_notifier_call_chain(&cu2_chain
, val
, v
);
1074 static int default_cu2_call(struct notifier_block
*nfb
, unsigned long action
,
1077 struct pt_regs
*regs
= data
;
1079 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
1080 "instruction", regs
);
1081 force_sig(SIGILL
, current
);
1086 static int enable_restore_fp_context(int msa
)
1088 int err
, was_fpu_owner
;
1091 /* First time FP context user. */
1101 * This task has formerly used the FP context.
1103 * If this thread has no live MSA vector context then we can simply
1104 * restore the scalar FP context. If it has live MSA vector context
1105 * (that is, it has or may have used MSA since last performing a
1106 * function call) then we'll need to restore the vector context. This
1107 * applies even if we're currently only executing a scalar FP
1108 * instruction. This is because if we were to later execute an MSA
1109 * instruction then we'd either have to:
1111 * - Restore the vector context & clobber any registers modified by
1112 * scalar FP instructions between now & then.
1116 * - Not restore the vector context & lose the most significant bits
1117 * of all vector registers.
1119 * Neither of those options is acceptable. We cannot restore the least
1120 * significant bits of the registers now & only restore the most
1121 * significant bits later because the most significant bits of any
1122 * vector registers whose aliased FP register is modified now will have
1123 * been zeroed. We'd have no way to know that when restoring the vector
1124 * context & thus may load an outdated value for the most significant
1125 * bits of a vector register.
1127 if (!msa
&& !thread_msa_context_live())
1131 * This task is using or has previously used MSA. Thus we require
1132 * that Status.FR == 1.
1134 was_fpu_owner
= is_fpu_owner();
1140 write_msa_csr(current
->thread
.fpu
.msacsr
);
1141 set_thread_flag(TIF_USEDMSA
);
1144 * If this is the first time that the task is using MSA and it has
1145 * previously used scalar FP in this time slice then we already nave
1146 * FP context which we shouldn't clobber.
1148 if (!test_and_set_thread_flag(TIF_MSA_CTX_LIVE
) && was_fpu_owner
)
1151 /* We need to restore the vector context. */
1152 restore_msa(current
);
1156 asmlinkage
void do_cpu(struct pt_regs
*regs
)
1158 enum ctx_state prev_state
;
1159 unsigned int __user
*epc
;
1160 unsigned long old_epc
, old31
;
1161 unsigned int opcode
;
1164 unsigned long __maybe_unused flags
;
1166 prev_state
= exception_enter();
1167 cpid
= (regs
->cp0_cause
>> CAUSEB_CE
) & 3;
1170 die_if_kernel("do_cpu invoked from kernel context!", regs
);
1174 epc
= (unsigned int __user
*)exception_epc(regs
);
1175 old_epc
= regs
->cp0_epc
;
1176 old31
= regs
->regs
[31];
1180 if (unlikely(compute_return_epc(regs
) < 0))
1183 if (get_isa16_mode(regs
->cp0_epc
)) {
1184 unsigned short mmop
[2] = { 0 };
1186 if (unlikely(get_user(mmop
[0], epc
) < 0))
1188 if (unlikely(get_user(mmop
[1], epc
) < 0))
1190 opcode
= (mmop
[0] << 16) | mmop
[1];
1193 status
= simulate_rdhwr_mm(regs
, opcode
);
1195 if (unlikely(get_user(opcode
, epc
) < 0))
1198 if (!cpu_has_llsc
&& status
< 0)
1199 status
= simulate_llsc(regs
, opcode
);
1202 status
= simulate_rdhwr_normal(regs
, opcode
);
1208 if (unlikely(status
> 0)) {
1209 regs
->cp0_epc
= old_epc
; /* Undo skip-over. */
1210 regs
->regs
[31] = old31
;
1211 force_sig(status
, current
);
1218 * Old (MIPS I and MIPS II) processors will set this code
1219 * for COP1X opcode instructions that replaced the original
1220 * COP3 space. We don't limit COP1 space instructions in
1221 * the emulator according to the CPU ISA, so we want to
1222 * treat COP1X instructions consistently regardless of which
1223 * code the CPU chose. Therefore we redirect this trap to
1224 * the FP emulator too.
1226 * Then some newer FPU-less processors use this code
1227 * erroneously too, so they are covered by this choice
1230 if (raw_cpu_has_fpu
)
1235 err
= enable_restore_fp_context(0);
1237 if (!raw_cpu_has_fpu
|| err
) {
1239 void __user
*fault_addr
= NULL
;
1240 sig
= fpu_emulator_cop1Handler(regs
,
1241 ¤t
->thread
.fpu
,
1243 if (!process_fpemu_return(sig
, fault_addr
) && !err
)
1244 mt_ase_fp_affinity();
1250 raw_notifier_call_chain(&cu2_chain
, CU2_EXCEPTION
, regs
);
1254 force_sig(SIGILL
, current
);
1257 exception_exit(prev_state
);
1260 asmlinkage
void do_msa_fpe(struct pt_regs
*regs
)
1262 enum ctx_state prev_state
;
1264 prev_state
= exception_enter();
1265 die_if_kernel("do_msa_fpe invoked from kernel context!", regs
);
1266 force_sig(SIGFPE
, current
);
1267 exception_exit(prev_state
);
1270 asmlinkage
void do_msa(struct pt_regs
*regs
)
1272 enum ctx_state prev_state
;
1275 prev_state
= exception_enter();
1277 if (!cpu_has_msa
|| test_thread_flag(TIF_32BIT_FPREGS
)) {
1278 force_sig(SIGILL
, current
);
1282 die_if_kernel("do_msa invoked from kernel context!", regs
);
1284 err
= enable_restore_fp_context(1);
1286 force_sig(SIGILL
, current
);
1288 exception_exit(prev_state
);
1291 asmlinkage
void do_mdmx(struct pt_regs
*regs
)
1293 enum ctx_state prev_state
;
1295 prev_state
= exception_enter();
1296 force_sig(SIGILL
, current
);
1297 exception_exit(prev_state
);
1301 * Called with interrupts disabled.
1303 asmlinkage
void do_watch(struct pt_regs
*regs
)
1305 enum ctx_state prev_state
;
1308 prev_state
= exception_enter();
1310 * Clear WP (bit 22) bit of cause register so we don't loop
1313 cause
= read_c0_cause();
1314 cause
&= ~(1 << 22);
1315 write_c0_cause(cause
);
1318 * If the current thread has the watch registers loaded, save
1319 * their values and send SIGTRAP. Otherwise another thread
1320 * left the registers set, clear them and continue.
1322 if (test_tsk_thread_flag(current
, TIF_LOAD_WATCH
)) {
1323 mips_read_watch_registers();
1325 force_sig(SIGTRAP
, current
);
1327 mips_clear_watch_registers();
1330 exception_exit(prev_state
);
1333 asmlinkage
void do_mcheck(struct pt_regs
*regs
)
1335 const int field
= 2 * sizeof(unsigned long);
1336 int multi_match
= regs
->cp0_status
& ST0_TS
;
1337 enum ctx_state prev_state
;
1339 prev_state
= exception_enter();
1343 printk("Index : %0x\n", read_c0_index());
1344 printk("Pagemask: %0x\n", read_c0_pagemask());
1345 printk("EntryHi : %0*lx\n", field
, read_c0_entryhi());
1346 printk("EntryLo0: %0*lx\n", field
, read_c0_entrylo0());
1347 printk("EntryLo1: %0*lx\n", field
, read_c0_entrylo1());
1352 show_code((unsigned int __user
*) regs
->cp0_epc
);
1355 * Some chips may have other causes of machine check (e.g. SB1
1358 panic("Caught Machine Check exception - %scaused by multiple "
1359 "matching entries in the TLB.",
1360 (multi_match
) ? "" : "not ");
1363 asmlinkage
void do_mt(struct pt_regs
*regs
)
1367 subcode
= (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT
)
1368 >> VPECONTROL_EXCPT_SHIFT
;
1371 printk(KERN_DEBUG
"Thread Underflow\n");
1374 printk(KERN_DEBUG
"Thread Overflow\n");
1377 printk(KERN_DEBUG
"Invalid YIELD Qualifier\n");
1380 printk(KERN_DEBUG
"Gating Storage Exception\n");
1383 printk(KERN_DEBUG
"YIELD Scheduler Exception\n");
1386 printk(KERN_DEBUG
"Gating Storage Scheduler Exception\n");
1389 printk(KERN_DEBUG
"*** UNKNOWN THREAD EXCEPTION %d ***\n",
1393 die_if_kernel("MIPS MT Thread exception in kernel", regs
);
1395 force_sig(SIGILL
, current
);
1399 asmlinkage
void do_dsp(struct pt_regs
*regs
)
1402 panic("Unexpected DSP exception");
1404 force_sig(SIGILL
, current
);
1407 asmlinkage
void do_reserved(struct pt_regs
*regs
)
1410 * Game over - no way to handle this if it ever occurs. Most probably
1411 * caused by a new unknown cpu type or after another deadly
1412 * hard/software error.
1415 panic("Caught reserved exception %ld - should not happen.",
1416 (regs
->cp0_cause
& 0x7f) >> 2);
1419 static int __initdata l1parity
= 1;
1420 static int __init
nol1parity(char *s
)
1425 __setup("nol1par", nol1parity
);
1426 static int __initdata l2parity
= 1;
1427 static int __init
nol2parity(char *s
)
1432 __setup("nol2par", nol2parity
);
1435 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1436 * it different ways.
1438 static inline void parity_protection_init(void)
1440 switch (current_cpu_type()) {
1446 case CPU_INTERAPTIV
:
1450 #define ERRCTL_PE 0x80000000
1451 #define ERRCTL_L2P 0x00800000
1452 unsigned long errctl
;
1453 unsigned int l1parity_present
, l2parity_present
;
1455 errctl
= read_c0_ecc();
1456 errctl
&= ~(ERRCTL_PE
|ERRCTL_L2P
);
1458 /* probe L1 parity support */
1459 write_c0_ecc(errctl
| ERRCTL_PE
);
1460 back_to_back_c0_hazard();
1461 l1parity_present
= (read_c0_ecc() & ERRCTL_PE
);
1463 /* probe L2 parity support */
1464 write_c0_ecc(errctl
|ERRCTL_L2P
);
1465 back_to_back_c0_hazard();
1466 l2parity_present
= (read_c0_ecc() & ERRCTL_L2P
);
1468 if (l1parity_present
&& l2parity_present
) {
1470 errctl
|= ERRCTL_PE
;
1471 if (l1parity
^ l2parity
)
1472 errctl
|= ERRCTL_L2P
;
1473 } else if (l1parity_present
) {
1475 errctl
|= ERRCTL_PE
;
1476 } else if (l2parity_present
) {
1478 errctl
|= ERRCTL_L2P
;
1480 /* No parity available */
1483 printk(KERN_INFO
"Writing ErrCtl register=%08lx\n", errctl
);
1485 write_c0_ecc(errctl
);
1486 back_to_back_c0_hazard();
1487 errctl
= read_c0_ecc();
1488 printk(KERN_INFO
"Readback ErrCtl register=%08lx\n", errctl
);
1490 if (l1parity_present
)
1491 printk(KERN_INFO
"Cache parity protection %sabled\n",
1492 (errctl
& ERRCTL_PE
) ? "en" : "dis");
1494 if (l2parity_present
) {
1495 if (l1parity_present
&& l1parity
)
1496 errctl
^= ERRCTL_L2P
;
1497 printk(KERN_INFO
"L2 cache parity protection %sabled\n",
1498 (errctl
& ERRCTL_L2P
) ? "en" : "dis");
1506 write_c0_ecc(0x80000000);
1507 back_to_back_c0_hazard();
1508 /* Set the PE bit (bit 31) in the c0_errctl register. */
1509 printk(KERN_INFO
"Cache parity protection %sabled\n",
1510 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1514 /* Clear the DE bit (bit 16) in the c0_status register. */
1515 printk(KERN_INFO
"Enable cache parity protection for "
1516 "MIPS 20KC/25KF CPUs.\n");
1517 clear_c0_status(ST0_DE
);
1524 asmlinkage
void cache_parity_error(void)
1526 const int field
= 2 * sizeof(unsigned long);
1527 unsigned int reg_val
;
1529 /* For the moment, report the problem and hang. */
1530 printk("Cache error exception:\n");
1531 printk("cp0_errorepc == %0*lx\n", field
, read_c0_errorepc());
1532 reg_val
= read_c0_cacheerr();
1533 printk("c0_cacheerr == %08x\n", reg_val
);
1535 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1536 reg_val
& (1<<30) ? "secondary" : "primary",
1537 reg_val
& (1<<31) ? "data" : "insn");
1538 if (cpu_has_mips_r2
&&
1539 ((current_cpu_data
.processor_id
&& 0xff0000) == PRID_COMP_MIPS
)) {
1540 pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1541 reg_val
& (1<<29) ? "ED " : "",
1542 reg_val
& (1<<28) ? "ET " : "",
1543 reg_val
& (1<<27) ? "ES " : "",
1544 reg_val
& (1<<26) ? "EE " : "",
1545 reg_val
& (1<<25) ? "EB " : "",
1546 reg_val
& (1<<24) ? "EI " : "",
1547 reg_val
& (1<<23) ? "E1 " : "",
1548 reg_val
& (1<<22) ? "E0 " : "");
1550 pr_err("Error bits: %s%s%s%s%s%s%s\n",
1551 reg_val
& (1<<29) ? "ED " : "",
1552 reg_val
& (1<<28) ? "ET " : "",
1553 reg_val
& (1<<26) ? "EE " : "",
1554 reg_val
& (1<<25) ? "EB " : "",
1555 reg_val
& (1<<24) ? "EI " : "",
1556 reg_val
& (1<<23) ? "E1 " : "",
1557 reg_val
& (1<<22) ? "E0 " : "");
1559 printk("IDX: 0x%08x\n", reg_val
& ((1<<22)-1));
1561 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1562 if (reg_val
& (1<<22))
1563 printk("DErrAddr0: 0x%0*lx\n", field
, read_c0_derraddr0());
1565 if (reg_val
& (1<<23))
1566 printk("DErrAddr1: 0x%0*lx\n", field
, read_c0_derraddr1());
1569 panic("Can't handle the cache error!");
1572 asmlinkage
void do_ftlb(void)
1574 const int field
= 2 * sizeof(unsigned long);
1575 unsigned int reg_val
;
1577 /* For the moment, report the problem and hang. */
1578 if (cpu_has_mips_r2
&&
1579 ((current_cpu_data
.processor_id
&& 0xff0000) == PRID_COMP_MIPS
)) {
1580 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1582 pr_err("cp0_errorepc == %0*lx\n", field
, read_c0_errorepc());
1583 reg_val
= read_c0_cacheerr();
1584 pr_err("c0_cacheerr == %08x\n", reg_val
);
1586 if ((reg_val
& 0xc0000000) == 0xc0000000) {
1587 pr_err("Decoded c0_cacheerr: FTLB parity error\n");
1589 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1590 reg_val
& (1<<30) ? "secondary" : "primary",
1591 reg_val
& (1<<31) ? "data" : "insn");
1594 pr_err("FTLB error exception\n");
1596 /* Just print the cacheerr bits for now */
1597 cache_parity_error();
1601 * SDBBP EJTAG debug exception handler.
1602 * We skip the instruction and return to the next instruction.
1604 void ejtag_exception_handler(struct pt_regs
*regs
)
1606 const int field
= 2 * sizeof(unsigned long);
1607 unsigned long depc
, old_epc
, old_ra
;
1610 printk(KERN_DEBUG
"SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1611 depc
= read_c0_depc();
1612 debug
= read_c0_debug();
1613 printk(KERN_DEBUG
"c0_depc = %0*lx, DEBUG = %08x\n", field
, depc
, debug
);
1614 if (debug
& 0x80000000) {
1616 * In branch delay slot.
1617 * We cheat a little bit here and use EPC to calculate the
1618 * debug return address (DEPC). EPC is restored after the
1621 old_epc
= regs
->cp0_epc
;
1622 old_ra
= regs
->regs
[31];
1623 regs
->cp0_epc
= depc
;
1624 compute_return_epc(regs
);
1625 depc
= regs
->cp0_epc
;
1626 regs
->cp0_epc
= old_epc
;
1627 regs
->regs
[31] = old_ra
;
1630 write_c0_depc(depc
);
1633 printk(KERN_DEBUG
"\n\n----- Enable EJTAG single stepping ----\n\n");
1634 write_c0_debug(debug
| 0x100);
1639 * NMI exception handler.
1640 * No lock; only written during early bootup by CPU 0.
1642 static RAW_NOTIFIER_HEAD(nmi_chain
);
1644 int register_nmi_notifier(struct notifier_block
*nb
)
1646 return raw_notifier_chain_register(&nmi_chain
, nb
);
1649 void __noreturn
nmi_exception_handler(struct pt_regs
*regs
)
1653 raw_notifier_call_chain(&nmi_chain
, 0, regs
);
1655 snprintf(str
, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1656 smp_processor_id(), regs
->cp0_epc
);
1657 regs
->cp0_epc
= read_c0_errorepc();
1661 #define VECTORSPACING 0x100 /* for EI/VI mode */
1663 unsigned long ebase
;
1664 unsigned long exception_handlers
[32];
1665 unsigned long vi_handlers
[64];
1667 void __init
*set_except_vector(int n
, void *addr
)
1669 unsigned long handler
= (unsigned long) addr
;
1670 unsigned long old_handler
;
1672 #ifdef CONFIG_CPU_MICROMIPS
1674 * Only the TLB handlers are cache aligned with an even
1675 * address. All other handlers are on an odd address and
1676 * require no modification. Otherwise, MIPS32 mode will
1677 * be entered when handling any TLB exceptions. That
1678 * would be bad...since we must stay in microMIPS mode.
1680 if (!(handler
& 0x1))
1683 old_handler
= xchg(&exception_handlers
[n
], handler
);
1685 if (n
== 0 && cpu_has_divec
) {
1686 #ifdef CONFIG_CPU_MICROMIPS
1687 unsigned long jump_mask
= ~((1 << 27) - 1);
1689 unsigned long jump_mask
= ~((1 << 28) - 1);
1691 u32
*buf
= (u32
*)(ebase
+ 0x200);
1692 unsigned int k0
= 26;
1693 if ((handler
& jump_mask
) == ((ebase
+ 0x200) & jump_mask
)) {
1694 uasm_i_j(&buf
, handler
& ~jump_mask
);
1697 UASM_i_LA(&buf
, k0
, handler
);
1698 uasm_i_jr(&buf
, k0
);
1701 local_flush_icache_range(ebase
+ 0x200, (unsigned long)buf
);
1703 return (void *)old_handler
;
1706 static void do_default_vi(void)
1708 show_regs(get_irq_regs());
1709 panic("Caught unexpected vectored interrupt.");
1712 static void *set_vi_srs_handler(int n
, vi_handler_t addr
, int srs
)
1714 unsigned long handler
;
1715 unsigned long old_handler
= vi_handlers
[n
];
1716 int srssets
= current_cpu_data
.srsets
;
1720 BUG_ON(!cpu_has_veic
&& !cpu_has_vint
);
1723 handler
= (unsigned long) do_default_vi
;
1726 handler
= (unsigned long) addr
;
1727 vi_handlers
[n
] = handler
;
1729 b
= (unsigned char *)(ebase
+ 0x200 + n
*VECTORSPACING
);
1732 panic("Shadow register set %d not supported", srs
);
1735 if (board_bind_eic_interrupt
)
1736 board_bind_eic_interrupt(n
, srs
);
1737 } else if (cpu_has_vint
) {
1738 /* SRSMap is only defined if shadow sets are implemented */
1740 change_c0_srsmap(0xf << n
*4, srs
<< n
*4);
1745 * If no shadow set is selected then use the default handler
1746 * that does normal register saving and standard interrupt exit
1748 extern char except_vec_vi
, except_vec_vi_lui
;
1749 extern char except_vec_vi_ori
, except_vec_vi_end
;
1750 extern char rollback_except_vec_vi
;
1751 char *vec_start
= using_rollback_handler() ?
1752 &rollback_except_vec_vi
: &except_vec_vi
;
1753 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1754 const int lui_offset
= &except_vec_vi_lui
- vec_start
+ 2;
1755 const int ori_offset
= &except_vec_vi_ori
- vec_start
+ 2;
1757 const int lui_offset
= &except_vec_vi_lui
- vec_start
;
1758 const int ori_offset
= &except_vec_vi_ori
- vec_start
;
1760 const int handler_len
= &except_vec_vi_end
- vec_start
;
1762 if (handler_len
> VECTORSPACING
) {
1764 * Sigh... panicing won't help as the console
1765 * is probably not configured :(
1767 panic("VECTORSPACING too small");
1770 set_handler(((unsigned long)b
- ebase
), vec_start
,
1771 #ifdef CONFIG_CPU_MICROMIPS
1776 h
= (u16
*)(b
+ lui_offset
);
1777 *h
= (handler
>> 16) & 0xffff;
1778 h
= (u16
*)(b
+ ori_offset
);
1779 *h
= (handler
& 0xffff);
1780 local_flush_icache_range((unsigned long)b
,
1781 (unsigned long)(b
+handler_len
));
1785 * In other cases jump directly to the interrupt handler. It
1786 * is the handler's responsibility to save registers if required
1787 * (eg hi/lo) and return from the exception using "eret".
1793 #ifdef CONFIG_CPU_MICROMIPS
1794 insn
= 0xd4000000 | (((u32
)handler
& 0x07ffffff) >> 1);
1796 insn
= 0x08000000 | (((u32
)handler
& 0x0fffffff) >> 2);
1798 h
[0] = (insn
>> 16) & 0xffff;
1799 h
[1] = insn
& 0xffff;
1802 local_flush_icache_range((unsigned long)b
,
1803 (unsigned long)(b
+8));
1806 return (void *)old_handler
;
1809 void *set_vi_handler(int n
, vi_handler_t addr
)
1811 return set_vi_srs_handler(n
, addr
, 0);
1814 extern void tlb_init(void);
1819 int cp0_compare_irq
;
1820 EXPORT_SYMBOL_GPL(cp0_compare_irq
);
1821 int cp0_compare_irq_shift
;
1824 * Performance counter IRQ or -1 if shared with timer
1826 int cp0_perfcount_irq
;
1827 EXPORT_SYMBOL_GPL(cp0_perfcount_irq
);
1831 static int __init
ulri_disable(char *s
)
1833 pr_info("Disabling ulri\n");
1838 __setup("noulri", ulri_disable
);
1840 void per_cpu_trap_init(bool is_boot_cpu
)
1842 unsigned int cpu
= smp_processor_id();
1843 unsigned int status_set
= ST0_CU0
;
1844 unsigned int hwrena
= cpu_hwrena_impl_bits
;
1847 * Disable coprocessors and select 32-bit or 64-bit addressing
1848 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1849 * flag that some firmware may have left set and the TS bit (for
1850 * IP27). Set XX for ISA IV code to work.
1853 status_set
|= ST0_FR
|ST0_KX
|ST0_SX
|ST0_UX
;
1855 if (current_cpu_data
.isa_level
& MIPS_CPU_ISA_IV
)
1856 status_set
|= ST0_XX
;
1858 status_set
|= ST0_MX
;
1860 change_c0_status(ST0_CU
|ST0_MX
|ST0_RE
|ST0_FR
|ST0_BEV
|ST0_TS
|ST0_KX
|ST0_SX
|ST0_UX
,
1863 if (cpu_has_mips_r2
)
1864 hwrena
|= 0x0000000f;
1866 if (!noulri
&& cpu_has_userlocal
)
1867 hwrena
|= (1 << 29);
1870 write_c0_hwrena(hwrena
);
1872 if (cpu_has_veic
|| cpu_has_vint
) {
1873 unsigned long sr
= set_c0_status(ST0_BEV
);
1874 write_c0_ebase(ebase
);
1875 write_c0_status(sr
);
1876 /* Setting vector spacing enables EI/VI mode */
1877 change_c0_intctl(0x3e0, VECTORSPACING
);
1879 if (cpu_has_divec
) {
1880 if (cpu_has_mipsmt
) {
1881 unsigned int vpflags
= dvpe();
1882 set_c0_cause(CAUSEF_IV
);
1885 set_c0_cause(CAUSEF_IV
);
1889 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
1891 * o read IntCtl.IPTI to determine the timer interrupt
1892 * o read IntCtl.IPPCI to determine the performance counter interrupt
1894 if (cpu_has_mips_r2
) {
1895 cp0_compare_irq_shift
= CAUSEB_TI
- CAUSEB_IP
;
1896 cp0_compare_irq
= (read_c0_intctl() >> INTCTLB_IPTI
) & 7;
1897 cp0_perfcount_irq
= (read_c0_intctl() >> INTCTLB_IPPCI
) & 7;
1898 if (cp0_perfcount_irq
== cp0_compare_irq
)
1899 cp0_perfcount_irq
= -1;
1901 cp0_compare_irq
= CP0_LEGACY_COMPARE_IRQ
;
1902 cp0_compare_irq_shift
= CP0_LEGACY_PERFCNT_IRQ
;
1903 cp0_perfcount_irq
= -1;
1906 if (!cpu_data
[cpu
].asid_cache
)
1907 cpu_data
[cpu
].asid_cache
= ASID_FIRST_VERSION
;
1909 atomic_inc(&init_mm
.mm_count
);
1910 current
->active_mm
= &init_mm
;
1911 BUG_ON(current
->mm
);
1912 enter_lazy_tlb(&init_mm
, current
);
1914 /* Boot CPU's cache setup in setup_arch(). */
1918 TLBMISS_HANDLER_SETUP();
1921 /* Install CPU exception handler */
1922 void set_handler(unsigned long offset
, void *addr
, unsigned long size
)
1924 #ifdef CONFIG_CPU_MICROMIPS
1925 memcpy((void *)(ebase
+ offset
), ((unsigned char *)addr
- 1), size
);
1927 memcpy((void *)(ebase
+ offset
), addr
, size
);
1929 local_flush_icache_range(ebase
+ offset
, ebase
+ offset
+ size
);
1932 static char panic_null_cerr
[] =
1933 "Trying to set NULL cache error exception handler";
1936 * Install uncached CPU exception handler.
1937 * This is suitable only for the cache error exception which is the only
1938 * exception handler that is being run uncached.
1940 void set_uncached_handler(unsigned long offset
, void *addr
,
1943 unsigned long uncached_ebase
= CKSEG1ADDR(ebase
);
1946 panic(panic_null_cerr
);
1948 memcpy((void *)(uncached_ebase
+ offset
), addr
, size
);
1951 static int __initdata rdhwr_noopt
;
1952 static int __init
set_rdhwr_noopt(char *str
)
1958 __setup("rdhwr_noopt", set_rdhwr_noopt
);
1960 void __init
trap_init(void)
1962 extern char except_vec3_generic
;
1963 extern char except_vec4
;
1964 extern char except_vec3_r4000
;
1969 #if defined(CONFIG_KGDB)
1970 if (kgdb_early_setup
)
1971 return; /* Already done */
1974 if (cpu_has_veic
|| cpu_has_vint
) {
1975 unsigned long size
= 0x200 + VECTORSPACING
*64;
1976 ebase
= (unsigned long)
1977 __alloc_bootmem(size
, 1 << fls(size
), 0);
1979 #ifdef CONFIG_KVM_GUEST
1980 #define KVM_GUEST_KSEG0 0x40000000
1981 ebase
= KVM_GUEST_KSEG0
;
1985 if (cpu_has_mips_r2
)
1986 ebase
+= (read_c0_ebase() & 0x3ffff000);
1989 if (cpu_has_mmips
) {
1990 unsigned int config3
= read_c0_config3();
1992 if (IS_ENABLED(CONFIG_CPU_MICROMIPS
))
1993 write_c0_config3(config3
| MIPS_CONF3_ISA_OE
);
1995 write_c0_config3(config3
& ~MIPS_CONF3_ISA_OE
);
1998 if (board_ebase_setup
)
1999 board_ebase_setup();
2000 per_cpu_trap_init(true);
2003 * Copy the generic exception handlers to their final destination.
2004 * This will be overriden later as suitable for a particular
2007 set_handler(0x180, &except_vec3_generic
, 0x80);
2010 * Setup default vectors
2012 for (i
= 0; i
<= 31; i
++)
2013 set_except_vector(i
, handle_reserved
);
2016 * Copy the EJTAG debug exception vector handler code to it's final
2019 if (cpu_has_ejtag
&& board_ejtag_handler_setup
)
2020 board_ejtag_handler_setup();
2023 * Only some CPUs have the watch exceptions.
2026 set_except_vector(23, handle_watch
);
2029 * Initialise interrupt handlers
2031 if (cpu_has_veic
|| cpu_has_vint
) {
2032 int nvec
= cpu_has_veic
? 64 : 8;
2033 for (i
= 0; i
< nvec
; i
++)
2034 set_vi_handler(i
, NULL
);
2036 else if (cpu_has_divec
)
2037 set_handler(0x200, &except_vec4
, 0x8);
2040 * Some CPUs can enable/disable for cache parity detection, but does
2041 * it different ways.
2043 parity_protection_init();
2046 * The Data Bus Errors / Instruction Bus Errors are signaled
2047 * by external hardware. Therefore these two exceptions
2048 * may have board specific handlers.
2053 set_except_vector(0, using_rollback_handler() ? rollback_handle_int
2055 set_except_vector(1, handle_tlbm
);
2056 set_except_vector(2, handle_tlbl
);
2057 set_except_vector(3, handle_tlbs
);
2059 set_except_vector(4, handle_adel
);
2060 set_except_vector(5, handle_ades
);
2062 set_except_vector(6, handle_ibe
);
2063 set_except_vector(7, handle_dbe
);
2065 set_except_vector(8, handle_sys
);
2066 set_except_vector(9, handle_bp
);
2067 set_except_vector(10, rdhwr_noopt
? handle_ri
:
2068 (cpu_has_vtag_icache
?
2069 handle_ri_rdhwr_vivt
: handle_ri_rdhwr
));
2070 set_except_vector(11, handle_cpu
);
2071 set_except_vector(12, handle_ov
);
2072 set_except_vector(13, handle_tr
);
2073 set_except_vector(14, handle_msa_fpe
);
2075 if (current_cpu_type() == CPU_R6000
||
2076 current_cpu_type() == CPU_R6000A
) {
2078 * The R6000 is the only R-series CPU that features a machine
2079 * check exception (similar to the R4000 cache error) and
2080 * unaligned ldc1/sdc1 exception. The handlers have not been
2081 * written yet. Well, anyway there is no R6000 machine on the
2082 * current list of targets for Linux/MIPS.
2083 * (Duh, crap, there is someone with a triple R6k machine)
2085 //set_except_vector(14, handle_mc);
2086 //set_except_vector(15, handle_ndc);
2090 if (board_nmi_handler_setup
)
2091 board_nmi_handler_setup();
2093 if (cpu_has_fpu
&& !cpu_has_nofpuex
)
2094 set_except_vector(15, handle_fpe
);
2096 set_except_vector(16, handle_ftlb
);
2097 set_except_vector(21, handle_msa
);
2098 set_except_vector(22, handle_mdmx
);
2101 set_except_vector(24, handle_mcheck
);
2104 set_except_vector(25, handle_mt
);
2106 set_except_vector(26, handle_dsp
);
2108 if (board_cache_error_setup
)
2109 board_cache_error_setup();
2112 /* Special exception: R4[04]00 uses also the divec space. */
2113 set_handler(0x180, &except_vec3_r4000
, 0x100);
2114 else if (cpu_has_4kex
)
2115 set_handler(0x180, &except_vec3_generic
, 0x80);
2117 set_handler(0x080, &except_vec3_generic
, 0x80);
2119 local_flush_icache_range(ebase
, ebase
+ 0x400);
2121 sort_extable(__start___dbe_table
, __stop___dbe_table
);
2123 cu2_notifier(default_cu2_call
, 0x80000000); /* Run last */