arch/mips/lantiq/prom.c

   1 /*
   2  *  This program is free software; you can redistribute it and/or modify it
   3  *  under the terms of the GNU General Public License version 2 as published
   4  *  by the Free Software Foundation.
   5  *
   6  * Copyright (C) 2010 John Crispin <john@phrozen.org>
   7  */
   8
   9 #include <linux/export.h>
  10 #include <linux/clk.h>
  11 #include <linux/bootmem.h>
  12 #include <linux/of_platform.h>
  13 #include <linux/of_fdt.h>
  14
  15 #include <asm/bootinfo.h>
  16 #include <asm/time.h>
  17 #include <asm/prom.h>
  18
  19 #include <lantiq.h>
  20
  21 #include "prom.h"
  22 #include "clk.h"
  23
  24 /* access to the ebu needs to be locked between different drivers */
  25 DEFINE_SPINLOCK(ebu_lock);
  26 EXPORT_SYMBOL_GPL(ebu_lock);
  27
  28 /*
  29  * this struct is filled by the soc specific detection code and holds
  30  * information about the specific soc type, revision and name
  31  */
  32 static struct ltq_soc_info soc_info;
  33
  34 const char *get_system_type(void)
  35 {
  36         return soc_info.sys_type;
  37 }
  38
  39 int ltq_soc_type(void)
  40 {
  41         return soc_info.type;
  42 }
  43
  44 void __init prom_free_prom_memory(void)
  45 {
  46 }
  47
  48 static void __init prom_init_cmdline(void)
  49 {
  50         int argc = fw_arg0;
  51         char **argv = (char **) KSEG1ADDR(fw_arg1);
  52         int i;
  53
  54         arcs_cmdline[0] = '\0';
  55
  56         for (i = 0; i < argc; i++) {
  57                 char *p = (char *) KSEG1ADDR(argv[i]);
  58
  59                 if (CPHYSADDR(p) && *p) {
  60                         strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
  61                         strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
  62                 }
  63         }
  64 }
  65
  66 void __init plat_mem_setup(void)
  67 {
  68         void *dtb;
  69
  70         ioport_resource.start = IOPORT_RESOURCE_START;
  71         ioport_resource.end = IOPORT_RESOURCE_END;
  72         iomem_resource.start = IOMEM_RESOURCE_START;
  73         iomem_resource.end = IOMEM_RESOURCE_END;
  74
  75         set_io_port_base((unsigned long) KSEG1);
  76
  77         if (fw_passed_dtb) /* UHI interface */
  78                 dtb = (void *)fw_passed_dtb;
  79         else if (__dtb_start != __dtb_end)
  80                 dtb = (void *)__dtb_start;
  81         else
  82                 panic("no dtb found");
  83
  84         /*
  85          * Load the devicetree. This causes the chosen node to be
  86          * parsed resulting in our memory appearing
  87          */
  88         __dt_setup_arch(dtb);
  89 }
  90
  91 void __init device_tree_init(void)
  92 {
  93         unflatten_and_copy_device_tree();
  94 }
  95
  96 void __init prom_init(void)
  97 {
  98         /* call the soc specific detetcion code and get it to fill soc_info */
  99         ltq_soc_detect(&soc_info);
 100         snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s",
 101                 soc_info.name, soc_info.rev_type);
 102         soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
 103         pr_info("SoC: %s\n", soc_info.sys_type);
 104         prom_init_cmdline();
 105
 106 #if defined(CONFIG_MIPS_MT_SMP)
 107         if (register_vsmp_smp_ops())
 108                 panic("failed to register_vsmp_smp_ops()");
 109 #endif
 110 }
 111
 112 int __init plat_of_setup(void)
 113 {
 114         return __dt_register_buses(soc_info.compatible, "simple-bus");
 115 }
 116
 117 arch_initcall(plat_of_setup);