1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * the IDE Virtual Support Module of AMD CS5536
5 * Copyright (C) 2007 Lemote, Inc.
6 * Author : jlliu, liujl@lemote.com
8 * Copyright (C) 2009 Lemote, Inc.
9 * Author: Wu Zhangjin, wuzhangjin@gmail.com
12 #include <cs5536/cs5536.h>
13 #include <cs5536/cs5536_pci.h>
15 void pci_ide_write_reg(int reg
, u32 value
)
17 u32 hi
= 0, lo
= value
;
21 _rdmsr(GLIU_MSR_REG(GLIU_PAE
), &hi
, &lo
);
22 if (value
& PCI_COMMAND_MASTER
)
26 _wrmsr(GLIU_MSR_REG(GLIU_PAE
), hi
, lo
);
29 if (value
& PCI_STATUS_PARITY
) {
30 _rdmsr(SB_MSR_REG(SB_ERROR
), &hi
, &lo
);
31 if (lo
& SB_PARE_ERR_FLAG
) {
32 lo
= (lo
& 0x0000ffff) | SB_PARE_ERR_FLAG
;
33 _wrmsr(SB_MSR_REG(SB_ERROR
), hi
, lo
);
37 case PCI_CACHE_LINE_SIZE
:
39 _rdmsr(SB_MSR_REG(SB_CTRL
), &hi
, &lo
);
42 _wrmsr(SB_MSR_REG(SB_CTRL
), hi
, lo
);
45 if (value
== PCI_BAR_RANGE_MASK
) {
46 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM
), &hi
, &lo
);
47 lo
|= SOFT_BAR_IDE_FLAG
;
48 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM
), hi
, lo
);
49 } else if (value
& 0x01) {
50 _rdmsr(IDE_MSR_REG(IDE_IO_BAR
), &hi
, &lo
);
51 lo
= (value
& 0xfffffff0) | 0x1;
52 _wrmsr(IDE_MSR_REG(IDE_IO_BAR
), hi
, lo
);
55 hi
= 0x60000000 | ((value
& 0x000ff000) >> 12);
56 lo
= 0x000ffff0 | ((value
& 0x00000fff) << 20);
57 _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM2
), hi
, lo
);
61 if (value
== CS5536_IDE_FLASH_SIGNATURE
) {
62 _rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS
), &hi
, &lo
);
64 _wrmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS
), hi
, lo
);
66 _rdmsr(IDE_MSR_REG(IDE_CFG
), &hi
, &lo
);
68 _wrmsr(IDE_MSR_REG(IDE_CFG
), hi
, lo
);
72 _rdmsr(IDE_MSR_REG(IDE_DTC
), &hi
, &lo
);
74 _wrmsr(IDE_MSR_REG(IDE_DTC
), hi
, lo
);
76 case PCI_IDE_CAST_REG
:
77 _rdmsr(IDE_MSR_REG(IDE_CAST
), &hi
, &lo
);
79 _wrmsr(IDE_MSR_REG(IDE_CAST
), hi
, lo
);
82 _rdmsr(IDE_MSR_REG(IDE_ETC
), &hi
, &lo
);
84 _wrmsr(IDE_MSR_REG(IDE_ETC
), hi
, lo
);
87 _rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM
), &hi
, &lo
);
89 _wrmsr(IDE_MSR_REG(IDE_INTERNAL_PM
), hi
, lo
);
96 u32
pci_ide_read_reg(int reg
)
104 CFG_PCI_VENDOR_ID(CS5536_IDE_DEVICE_ID
, CS5536_VENDOR_ID
);
107 _rdmsr(IDE_MSR_REG(IDE_IO_BAR
), &hi
, &lo
);
109 conf_data
|= PCI_COMMAND_IO
;
110 _rdmsr(GLIU_MSR_REG(GLIU_PAE
), &hi
, &lo
);
111 if ((lo
& 0x30) == 0x30)
112 conf_data
|= PCI_COMMAND_MASTER
;
115 conf_data
|= PCI_STATUS_66MHZ
;
116 conf_data
|= PCI_STATUS_FAST_BACK
;
117 _rdmsr(SB_MSR_REG(SB_ERROR
), &hi
, &lo
);
118 if (lo
& SB_PARE_ERR_FLAG
)
119 conf_data
|= PCI_STATUS_PARITY
;
120 conf_data
|= PCI_STATUS_DEVSEL_MEDIUM
;
122 case PCI_CLASS_REVISION
:
123 _rdmsr(IDE_MSR_REG(IDE_CAP
), &hi
, &lo
);
124 conf_data
= lo
& 0x000000ff;
125 conf_data
|= (CS5536_IDE_CLASS_CODE
<< 8);
127 case PCI_CACHE_LINE_SIZE
:
128 _rdmsr(SB_MSR_REG(SB_CTRL
), &hi
, &lo
);
130 conf_data
= CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE
, hi
);
133 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM
), &hi
, &lo
);
134 if (lo
& SOFT_BAR_IDE_FLAG
) {
135 conf_data
= CS5536_IDE_RANGE
|
136 PCI_BASE_ADDRESS_SPACE_IO
;
137 lo
&= ~SOFT_BAR_IDE_FLAG
;
138 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM
), hi
, lo
);
140 _rdmsr(IDE_MSR_REG(IDE_IO_BAR
), &hi
, &lo
);
141 conf_data
= lo
& 0xfffffff0;
146 case PCI_CARDBUS_CIS
:
147 conf_data
= PCI_CARDBUS_CIS_POINTER
;
149 case PCI_SUBSYSTEM_VENDOR_ID
:
151 CFG_PCI_VENDOR_ID(CS5536_IDE_SUB_ID
, CS5536_SUB_VENDOR_ID
);
153 case PCI_ROM_ADDRESS
:
154 conf_data
= PCI_EXPANSION_ROM_BAR
;
156 case PCI_CAPABILITY_LIST
:
157 conf_data
= PCI_CAPLIST_POINTER
;
159 case PCI_INTERRUPT_LINE
:
161 CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN
, CS5536_IDE_INTR
);
163 case PCI_IDE_CFG_REG
:
164 _rdmsr(IDE_MSR_REG(IDE_CFG
), &hi
, &lo
);
167 case PCI_IDE_DTC_REG
:
168 _rdmsr(IDE_MSR_REG(IDE_DTC
), &hi
, &lo
);
171 case PCI_IDE_CAST_REG
:
172 _rdmsr(IDE_MSR_REG(IDE_CAST
), &hi
, &lo
);
175 case PCI_IDE_ETC_REG
:
176 _rdmsr(IDE_MSR_REG(IDE_ETC
), &hi
, &lo
);
180 _rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM
), &hi
, &lo
);