]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - arch/mips/loongson64/loongson-3/smp.c
projects / mirror_ubuntu-artful-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'efi-urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/efi/efi into...
[mirror_ubuntu-artful-kernel.git] / arch / mips / loongson64 / loongson-3 / smp.c
1 /*
2 * Copyright (C) 2010, 2011, 2012, Lemote, Inc.
3 * Author: Chen Huacai, chenhc@lemote.com
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17 #include <linux/init.h>
18 #include <linux/cpu.h>
19 #include <linux/sched.h>
20 #include <linux/sched/hotplug.h>
21 #include <linux/sched/task_stack.h>
22 #include <linux/smp.h>
23 #include <linux/cpufreq.h>
24 #include <asm/processor.h>
25 #include <asm/time.h>
26 #include <asm/clock.h>
27 #include <asm/tlbflush.h>
28 #include <asm/cacheflush.h>
29 #include <loongson.h>
30 #include <workarounds.h>
31
32 #include "smp.h"
33
34 DEFINE_PER_CPU(int, cpu_state);
35
36 static void *ipi_set0_regs[16];
37 static void *ipi_clear0_regs[16];
38 static void *ipi_status0_regs[16];
39 static void *ipi_en0_regs[16];
40 static void *ipi_mailbox_buf[16];
41 static uint32_t core0_c0count[NR_CPUS];
42
43 /* read a 32bit value from ipi register */
44 #define loongson3_ipi_read32(addr) readl(addr)
45 /* read a 64bit value from ipi register */
46 #define loongson3_ipi_read64(addr) readq(addr)
47 /* write a 32bit value to ipi register */
48 #define loongson3_ipi_write32(action, addr) \
49 do { \
50 writel(action, addr); \
51 __wbflush(); \
52 } while (0)
53 /* write a 64bit value to ipi register */
54 #define loongson3_ipi_write64(action, addr) \
55 do { \
56 writeq(action, addr); \
57 __wbflush(); \
58 } while (0)
59
60 static void ipi_set0_regs_init(void)
61 {
62 ipi_set0_regs[0] = (void *)
63 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + SET0);
64 ipi_set0_regs[1] = (void *)
65 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + SET0);
66 ipi_set0_regs[2] = (void *)
67 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + SET0);
68 ipi_set0_regs[3] = (void *)
69 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + SET0);
70 ipi_set0_regs[4] = (void *)
71 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + SET0);
72 ipi_set0_regs[5] = (void *)
73 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + SET0);
74 ipi_set0_regs[6] = (void *)
75 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + SET0);
76 ipi_set0_regs[7] = (void *)
77 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + SET0);
78 ipi_set0_regs[8] = (void *)
79 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + SET0);
80 ipi_set0_regs[9] = (void *)
81 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + SET0);
82 ipi_set0_regs[10] = (void *)
83 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + SET0);
84 ipi_set0_regs[11] = (void *)
85 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + SET0);
86 ipi_set0_regs[12] = (void *)
87 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + SET0);
88 ipi_set0_regs[13] = (void *)
89 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + SET0);
90 ipi_set0_regs[14] = (void *)
91 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + SET0);
92 ipi_set0_regs[15] = (void *)
93 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + SET0);
94 }
95
96 static void ipi_clear0_regs_init(void)
97 {
98 ipi_clear0_regs[0] = (void *)
99 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + CLEAR0);
100 ipi_clear0_regs[1] = (void *)
101 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + CLEAR0);
102 ipi_clear0_regs[2] = (void *)
103 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + CLEAR0);
104 ipi_clear0_regs[3] = (void *)
105 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + CLEAR0);
106 ipi_clear0_regs[4] = (void *)
107 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + CLEAR0);
108 ipi_clear0_regs[5] = (void *)
109 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + CLEAR0);
110 ipi_clear0_regs[6] = (void *)
111 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + CLEAR0);
112 ipi_clear0_regs[7] = (void *)
113 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + CLEAR0);
114 ipi_clear0_regs[8] = (void *)
115 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + CLEAR0);
116 ipi_clear0_regs[9] = (void *)
117 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + CLEAR0);
118 ipi_clear0_regs[10] = (void *)
119 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + CLEAR0);
120 ipi_clear0_regs[11] = (void *)
121 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + CLEAR0);
122 ipi_clear0_regs[12] = (void *)
123 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + CLEAR0);
124 ipi_clear0_regs[13] = (void *)
125 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + CLEAR0);
126 ipi_clear0_regs[14] = (void *)
127 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + CLEAR0);
128 ipi_clear0_regs[15] = (void *)
129 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + CLEAR0);
130 }
131
132 static void ipi_status0_regs_init(void)
133 {
134 ipi_status0_regs[0] = (void *)
135 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + STATUS0);
136 ipi_status0_regs[1] = (void *)
137 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + STATUS0);
138 ipi_status0_regs[2] = (void *)
139 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + STATUS0);
140 ipi_status0_regs[3] = (void *)
141 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + STATUS0);
142 ipi_status0_regs[4] = (void *)
143 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + STATUS0);
144 ipi_status0_regs[5] = (void *)
145 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + STATUS0);
146 ipi_status0_regs[6] = (void *)
147 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + STATUS0);
148 ipi_status0_regs[7] = (void *)
149 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + STATUS0);
150 ipi_status0_regs[8] = (void *)
151 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + STATUS0);
152 ipi_status0_regs[9] = (void *)
153 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + STATUS0);
154 ipi_status0_regs[10] = (void *)
155 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + STATUS0);
156 ipi_status0_regs[11] = (void *)
157 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + STATUS0);
158 ipi_status0_regs[12] = (void *)
159 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + STATUS0);
160 ipi_status0_regs[13] = (void *)
161 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + STATUS0);
162 ipi_status0_regs[14] = (void *)
163 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + STATUS0);
164 ipi_status0_regs[15] = (void *)
165 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + STATUS0);
166 }
167
168 static void ipi_en0_regs_init(void)
169 {
170 ipi_en0_regs[0] = (void *)
171 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + EN0);
172 ipi_en0_regs[1] = (void *)
173 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + EN0);
174 ipi_en0_regs[2] = (void *)
175 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + EN0);
176 ipi_en0_regs[3] = (void *)
177 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + EN0);
178 ipi_en0_regs[4] = (void *)
179 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + EN0);
180 ipi_en0_regs[5] = (void *)
181 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + EN0);
182 ipi_en0_regs[6] = (void *)
183 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + EN0);
184 ipi_en0_regs[7] = (void *)
185 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + EN0);
186 ipi_en0_regs[8] = (void *)
187 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + EN0);
188 ipi_en0_regs[9] = (void *)
189 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + EN0);
190 ipi_en0_regs[10] = (void *)
191 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + EN0);
192 ipi_en0_regs[11] = (void *)
193 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + EN0);
194 ipi_en0_regs[12] = (void *)
195 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + EN0);
196 ipi_en0_regs[13] = (void *)
197 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + EN0);
198 ipi_en0_regs[14] = (void *)
199 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + EN0);
200 ipi_en0_regs[15] = (void *)
201 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + EN0);
202 }
203
204 static void ipi_mailbox_buf_init(void)
205 {
206 ipi_mailbox_buf[0] = (void *)
207 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + BUF);
208 ipi_mailbox_buf[1] = (void *)
209 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + BUF);
210 ipi_mailbox_buf[2] = (void *)
211 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + BUF);
212 ipi_mailbox_buf[3] = (void *)
213 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + BUF);
214 ipi_mailbox_buf[4] = (void *)
215 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + BUF);
216 ipi_mailbox_buf[5] = (void *)
217 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + BUF);
218 ipi_mailbox_buf[6] = (void *)
219 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + BUF);
220 ipi_mailbox_buf[7] = (void *)
221 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + BUF);
222 ipi_mailbox_buf[8] = (void *)
223 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + BUF);
224 ipi_mailbox_buf[9] = (void *)
225 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + BUF);
226 ipi_mailbox_buf[10] = (void *)
227 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + BUF);
228 ipi_mailbox_buf[11] = (void *)
229 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + BUF);
230 ipi_mailbox_buf[12] = (void *)
231 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + BUF);
232 ipi_mailbox_buf[13] = (void *)
233 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + BUF);
234 ipi_mailbox_buf[14] = (void *)
235 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + BUF);
236 ipi_mailbox_buf[15] = (void *)
237 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + BUF);
238 }
239
240 /*
241 * Simple enough, just poke the appropriate ipi register
242 */
243 static void loongson3_send_ipi_single(int cpu, unsigned int action)
244 {
245 loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu_logical_map(cpu)]);
246 }
247
248 static void
249 loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action)
250 {
251 unsigned int i;
252
253 for_each_cpu(i, mask)
254 loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu_logical_map(i)]);
255 }
256
257 void loongson3_ipi_interrupt(struct pt_regs *regs)
258 {
259 int i, cpu = smp_processor_id();
260 unsigned int action, c0count;
261
262 /* Load the ipi register to figure out what we're supposed to do */
263 action = loongson3_ipi_read32(ipi_status0_regs[cpu_logical_map(cpu)]);
264
265 /* Clear the ipi register to clear the interrupt */
266 loongson3_ipi_write32((u32)action, ipi_clear0_regs[cpu_logical_map(cpu)]);
267
268 if (action & SMP_RESCHEDULE_YOURSELF)
269 scheduler_ipi();
270
271 if (action & SMP_CALL_FUNCTION) {
272 irq_enter();
273 generic_smp_call_function_interrupt();
274 irq_exit();
275 }
276
277 if (action & SMP_ASK_C0COUNT) {
278 BUG_ON(cpu != 0);
279 c0count = read_c0_count();
280 c0count = c0count ? c0count : 1;
281 for (i = 1; i < nr_cpu_ids; i++)
282 core0_c0count[i] = c0count;
283 __wbflush(); /* Let others see the result ASAP */
284 }
285 }
286
287 #define MAX_LOOPS 800
288 /*
289 * SMP init and finish on secondary CPUs
290 */
291 static void loongson3_init_secondary(void)
292 {
293 int i;
294 uint32_t initcount;
295 unsigned int cpu = smp_processor_id();
296 unsigned int imask = STATUSF_IP7 | STATUSF_IP6 |
297 STATUSF_IP3 | STATUSF_IP2;
298
299 /* Set interrupt mask, but don't enable */
300 change_c0_status(ST0_IM, imask);
301
302 for (i = 0; i < num_possible_cpus(); i++)
303 loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(i)]);
304
305 per_cpu(cpu_state, cpu) = CPU_ONLINE;
306 cpu_data[cpu].core =
307 cpu_logical_map(cpu) % loongson_sysconf.cores_per_package;
308 cpu_data[cpu].package =
309 cpu_logical_map(cpu) / loongson_sysconf.cores_per_package;
310
311 i = 0;
312 core0_c0count[cpu] = 0;
313 loongson3_send_ipi_single(0, SMP_ASK_C0COUNT);
314 while (!core0_c0count[cpu]) {
315 i++;
316 cpu_relax();
317 }
318
319 if (i > MAX_LOOPS)
320 i = MAX_LOOPS;
321 if (cpu_data[cpu].package)
322 initcount = core0_c0count[cpu] + i;
323 else /* Local access is faster for loops */
324 initcount = core0_c0count[cpu] + i/2;
325
326 write_c0_count(initcount);
327 }
328
329 static void loongson3_smp_finish(void)
330 {
331 int cpu = smp_processor_id();
332
333 write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
334 local_irq_enable();
335 loongson3_ipi_write64(0,
336 (void *)(ipi_mailbox_buf[cpu_logical_map(cpu)]+0x0));
337 pr_info("CPU#%d finished, CP0_ST=%x\n",
338 smp_processor_id(), read_c0_status());
339 }
340
341 static void __init loongson3_smp_setup(void)
342 {
343 int i = 0, num = 0; /* i: physical id, num: logical id */
344
345 init_cpu_possible(cpu_none_mask);
346
347 /* For unified kernel, NR_CPUS is the maximum possible value,
348 * loongson_sysconf.nr_cpus is the really present value */
349 while (i < loongson_sysconf.nr_cpus) {
350 if (loongson_sysconf.reserved_cpus_mask & (1<<i)) {
351 /* Reserved physical CPU cores */
352 __cpu_number_map[i] = -1;
353 } else {
354 __cpu_number_map[i] = num;
355 __cpu_logical_map[num] = i;
356 set_cpu_possible(num, true);
357 num++;
358 }
359 i++;
360 }
361 pr_info("Detected %i available CPU(s)\n", num);
362
363 while (num < loongson_sysconf.nr_cpus) {
364 __cpu_logical_map[num] = -1;
365 num++;
366 }
367
368 ipi_set0_regs_init();
369 ipi_clear0_regs_init();
370 ipi_status0_regs_init();
371 ipi_en0_regs_init();
372 ipi_mailbox_buf_init();
373 cpu_data[0].core = cpu_logical_map(0) % loongson_sysconf.cores_per_package;
374 cpu_data[0].package = cpu_logical_map(0) / loongson_sysconf.cores_per_package;
375 }
376
377 static void __init loongson3_prepare_cpus(unsigned int max_cpus)
378 {
379 init_cpu_present(cpu_possible_mask);
380 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
381 }
382
383 /*
384 * Setup the PC, SP, and GP of a secondary processor and start it runing!
385 */
386 static void loongson3_boot_secondary(int cpu, struct task_struct *idle)
387 {
388 unsigned long startargs[4];
389
390 pr_info("Booting CPU#%d...\n", cpu);
391
392 /* startargs[] are initial PC, SP and GP for secondary CPU */
393 startargs[0] = (unsigned long)&smp_bootstrap;
394 startargs[1] = (unsigned long)__KSTK_TOS(idle);
395 startargs[2] = (unsigned long)task_thread_info(idle);
396 startargs[3] = 0;
397
398 pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n",
399 cpu, startargs[0], startargs[1], startargs[2]);
400
401 loongson3_ipi_write64(startargs[3],
402 (void *)(ipi_mailbox_buf[cpu_logical_map(cpu)]+0x18));
403 loongson3_ipi_write64(startargs[2],
404 (void *)(ipi_mailbox_buf[cpu_logical_map(cpu)]+0x10));
405 loongson3_ipi_write64(startargs[1],
406 (void *)(ipi_mailbox_buf[cpu_logical_map(cpu)]+0x8));
407 loongson3_ipi_write64(startargs[0],
408 (void *)(ipi_mailbox_buf[cpu_logical_map(cpu)]+0x0));
409 }
410
411 #ifdef CONFIG_HOTPLUG_CPU
412
413 static int loongson3_cpu_disable(void)
414 {
415 unsigned long flags;
416 unsigned int cpu = smp_processor_id();
417
418 if (cpu == 0)
419 return -EBUSY;
420
421 set_cpu_online(cpu, false);
422 calculate_cpu_foreign_map();
423 local_irq_save(flags);
424 fixup_irqs();
425 local_irq_restore(flags);
426 local_flush_tlb_all();
427
428 return 0;
429 }
430
431
432 static void loongson3_cpu_die(unsigned int cpu)
433 {
434 while (per_cpu(cpu_state, cpu) != CPU_DEAD)
435 cpu_relax();
436
437 mb();
438 }
439
440 /* To shutdown a core in Loongson 3, the target core should go to CKSEG1 and
441 * flush all L1 entries at first. Then, another core (usually Core 0) can
442 * safely disable the clock of the target core. loongson3_play_dead() is
443 * called via CKSEG1 (uncached and unmmaped) */
444 static void loongson3a_r1_play_dead(int *state_addr)
445 {
446 register int val;
447 register long cpuid, core, node, count;
448 register void *addr, *base, *initfunc;
449
450 __asm__ __volatile__(
451 " .set push \n"
452 " .set noreorder \n"
453 " li %[addr], 0x80000000 \n" /* KSEG0 */
454 "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */
455 " cache 0, 1(%[addr]) \n"
456 " cache 0, 2(%[addr]) \n"
457 " cache 0, 3(%[addr]) \n"
458 " cache 1, 0(%[addr]) \n" /* flush L1 DCache */
459 " cache 1, 1(%[addr]) \n"
460 " cache 1, 2(%[addr]) \n"
461 " cache 1, 3(%[addr]) \n"
462 " addiu %[sets], %[sets], -1 \n"
463 " bnez %[sets], 1b \n"
464 " addiu %[addr], %[addr], 0x20 \n"
465 " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */
466 " sw %[val], (%[state_addr]) \n"
467 " sync \n"
468 " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */
469 " .set pop \n"
470 : [addr] "=&r" (addr), [val] "=&r" (val)
471 : [state_addr] "r" (state_addr),
472 [sets] "r" (cpu_data[smp_processor_id()].dcache.sets));
473
474 __asm__ __volatile__(
475 " .set push \n"
476 " .set noreorder \n"
477 " .set mips64 \n"
478 " mfc0 %[cpuid], $15, 1 \n"
479 " andi %[cpuid], 0x3ff \n"
480 " dli %[base], 0x900000003ff01000 \n"
481 " andi %[core], %[cpuid], 0x3 \n"
482 " sll %[core], 8 \n" /* get core id */
483 " or %[base], %[base], %[core] \n"
484 " andi %[node], %[cpuid], 0xc \n"
485 " dsll %[node], 42 \n" /* get node id */
486 " or %[base], %[base], %[node] \n"
487 "1: li %[count], 0x100 \n" /* wait for init loop */
488 "2: bnez %[count], 2b \n" /* limit mailbox access */
489 " addiu %[count], -1 \n"
490 " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */
491 " beqz %[initfunc], 1b \n"
492 " nop \n"
493 " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */
494 " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */
495 " ld $a1, 0x38(%[base]) \n"
496 " jr %[initfunc] \n" /* jump to initial PC */
497 " nop \n"
498 " .set pop \n"
499 : [core] "=&r" (core), [node] "=&r" (node),
500 [base] "=&r" (base), [cpuid] "=&r" (cpuid),
501 [count] "=&r" (count), [initfunc] "=&r" (initfunc)
502 : /* No Input */
503 : "a1");
504 }
505
506 static void loongson3a_r2_play_dead(int *state_addr)
507 {
508 register int val;
509 register long cpuid, core, node, count;
510 register void *addr, *base, *initfunc;
511
512 __asm__ __volatile__(
513 " .set push \n"
514 " .set noreorder \n"
515 " li %[addr], 0x80000000 \n" /* KSEG0 */
516 "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */
517 " cache 0, 1(%[addr]) \n"
518 " cache 0, 2(%[addr]) \n"
519 " cache 0, 3(%[addr]) \n"
520 " cache 1, 0(%[addr]) \n" /* flush L1 DCache */
521 " cache 1, 1(%[addr]) \n"
522 " cache 1, 2(%[addr]) \n"
523 " cache 1, 3(%[addr]) \n"
524 " addiu %[sets], %[sets], -1 \n"
525 " bnez %[sets], 1b \n"
526 " addiu %[addr], %[addr], 0x40 \n"
527 " li %[addr], 0x80000000 \n" /* KSEG0 */
528 "2: cache 2, 0(%[addr]) \n" /* flush L1 VCache */
529 " cache 2, 1(%[addr]) \n"
530 " cache 2, 2(%[addr]) \n"
531 " cache 2, 3(%[addr]) \n"
532 " cache 2, 4(%[addr]) \n"
533 " cache 2, 5(%[addr]) \n"
534 " cache 2, 6(%[addr]) \n"
535 " cache 2, 7(%[addr]) \n"
536 " cache 2, 8(%[addr]) \n"
537 " cache 2, 9(%[addr]) \n"
538 " cache 2, 10(%[addr]) \n"
539 " cache 2, 11(%[addr]) \n"
540 " cache 2, 12(%[addr]) \n"
541 " cache 2, 13(%[addr]) \n"
542 " cache 2, 14(%[addr]) \n"
543 " cache 2, 15(%[addr]) \n"
544 " addiu %[vsets], %[vsets], -1 \n"
545 " bnez %[vsets], 2b \n"
546 " addiu %[addr], %[addr], 0x40 \n"
547 " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */
548 " sw %[val], (%[state_addr]) \n"
549 " sync \n"
550 " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */
551 " .set pop \n"
552 : [addr] "=&r" (addr), [val] "=&r" (val)
553 : [state_addr] "r" (state_addr),
554 [sets] "r" (cpu_data[smp_processor_id()].dcache.sets),
555 [vsets] "r" (cpu_data[smp_processor_id()].vcache.sets));
556
557 __asm__ __volatile__(
558 " .set push \n"
559 " .set noreorder \n"
560 " .set mips64 \n"
561 " mfc0 %[cpuid], $15, 1 \n"
562 " andi %[cpuid], 0x3ff \n"
563 " dli %[base], 0x900000003ff01000 \n"
564 " andi %[core], %[cpuid], 0x3 \n"
565 " sll %[core], 8 \n" /* get core id */
566 " or %[base], %[base], %[core] \n"
567 " andi %[node], %[cpuid], 0xc \n"
568 " dsll %[node], 42 \n" /* get node id */
569 " or %[base], %[base], %[node] \n"
570 "1: li %[count], 0x100 \n" /* wait for init loop */
571 "2: bnez %[count], 2b \n" /* limit mailbox access */
572 " addiu %[count], -1 \n"
573 " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */
574 " beqz %[initfunc], 1b \n"
575 " nop \n"
576 " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */
577 " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */
578 " ld $a1, 0x38(%[base]) \n"
579 " jr %[initfunc] \n" /* jump to initial PC */
580 " nop \n"
581 " .set pop \n"
582 : [core] "=&r" (core), [node] "=&r" (node),
583 [base] "=&r" (base), [cpuid] "=&r" (cpuid),
584 [count] "=&r" (count), [initfunc] "=&r" (initfunc)
585 : /* No Input */
586 : "a1");
587 }
588
589 static void loongson3b_play_dead(int *state_addr)
590 {
591 register int val;
592 register long cpuid, core, node, count;
593 register void *addr, *base, *initfunc;
594
595 __asm__ __volatile__(
596 " .set push \n"
597 " .set noreorder \n"
598 " li %[addr], 0x80000000 \n" /* KSEG0 */
599 "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */
600 " cache 0, 1(%[addr]) \n"
601 " cache 0, 2(%[addr]) \n"
602 " cache 0, 3(%[addr]) \n"
603 " cache 1, 0(%[addr]) \n" /* flush L1 DCache */
604 " cache 1, 1(%[addr]) \n"
605 " cache 1, 2(%[addr]) \n"
606 " cache 1, 3(%[addr]) \n"
607 " addiu %[sets], %[sets], -1 \n"
608 " bnez %[sets], 1b \n"
609 " addiu %[addr], %[addr], 0x20 \n"
610 " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */
611 " sw %[val], (%[state_addr]) \n"
612 " sync \n"
613 " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */
614 " .set pop \n"
615 : [addr] "=&r" (addr), [val] "=&r" (val)
616 : [state_addr] "r" (state_addr),
617 [sets] "r" (cpu_data[smp_processor_id()].dcache.sets));
618
619 __asm__ __volatile__(
620 " .set push \n"
621 " .set noreorder \n"
622 " .set mips64 \n"
623 " mfc0 %[cpuid], $15, 1 \n"
624 " andi %[cpuid], 0x3ff \n"
625 " dli %[base], 0x900000003ff01000 \n"
626 " andi %[core], %[cpuid], 0x3 \n"
627 " sll %[core], 8 \n" /* get core id */
628 " or %[base], %[base], %[core] \n"
629 " andi %[node], %[cpuid], 0xc \n"
630 " dsll %[node], 42 \n" /* get node id */
631 " or %[base], %[base], %[node] \n"
632 " dsrl %[node], 30 \n" /* 15:14 */
633 " or %[base], %[base], %[node] \n"
634 "1: li %[count], 0x100 \n" /* wait for init loop */
635 "2: bnez %[count], 2b \n" /* limit mailbox access */
636 " addiu %[count], -1 \n"
637 " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */
638 " beqz %[initfunc], 1b \n"
639 " nop \n"
640 " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */
641 " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */
642 " ld $a1, 0x38(%[base]) \n"
643 " jr %[initfunc] \n" /* jump to initial PC */
644 " nop \n"
645 " .set pop \n"
646 : [core] "=&r" (core), [node] "=&r" (node),
647 [base] "=&r" (base), [cpuid] "=&r" (cpuid),
648 [count] "=&r" (count), [initfunc] "=&r" (initfunc)
649 : /* No Input */
650 : "a1");
651 }
652
653 void play_dead(void)
654 {
655 int *state_addr;
656 unsigned int cpu = smp_processor_id();
657 void (*play_dead_at_ckseg1)(int *);
658
659 idle_task_exit();
660 switch (read_c0_prid() & PRID_REV_MASK) {
661 case PRID_REV_LOONGSON3A_R1:
662 default:
663 play_dead_at_ckseg1 =
664 (void *)CKSEG1ADDR((unsigned long)loongson3a_r1_play_dead);
665 break;
666 case PRID_REV_LOONGSON3A_R2:
667 play_dead_at_ckseg1 =
668 (void *)CKSEG1ADDR((unsigned long)loongson3a_r2_play_dead);
669 break;
670 case PRID_REV_LOONGSON3B_R1:
671 case PRID_REV_LOONGSON3B_R2:
672 play_dead_at_ckseg1 =
673 (void *)CKSEG1ADDR((unsigned long)loongson3b_play_dead);
674 break;
675 }
676 state_addr = &per_cpu(cpu_state, cpu);
677 mb();
678 play_dead_at_ckseg1(state_addr);
679 }
680
681 static int loongson3_disable_clock(unsigned int cpu)
682 {
683 uint64_t core_id = cpu_data[cpu].core;
684 uint64_t package_id = cpu_data[cpu].package;
685
686 if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1) {
687 LOONGSON_CHIPCFG(package_id) &= ~(1 << (12 + core_id));
688 } else {
689 if (!(loongson_sysconf.workarounds & WORKAROUND_CPUHOTPLUG))
690 LOONGSON_FREQCTRL(package_id) &= ~(1 << (core_id * 4 + 3));
691 }
692 return 0;
693 }
694
695 static int loongson3_enable_clock(unsigned int cpu)
696 {
697 uint64_t core_id = cpu_data[cpu].core;
698 uint64_t package_id = cpu_data[cpu].package;
699
700 if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1) {
701 LOONGSON_CHIPCFG(package_id) |= 1 << (12 + core_id);
702 } else {
703 if (!(loongson_sysconf.workarounds & WORKAROUND_CPUHOTPLUG))
704 LOONGSON_FREQCTRL(package_id) |= 1 << (core_id * 4 + 3);
705 }
706 return 0;
707 }
708
709 static int register_loongson3_notifier(void)
710 {
711 return cpuhp_setup_state_nocalls(CPUHP_MIPS_SOC_PREPARE,
712 "mips/loongson:prepare",
713 loongson3_enable_clock,
714 loongson3_disable_clock);
715 }
716 early_initcall(register_loongson3_notifier);
717
718 #endif
719
720 struct plat_smp_ops loongson3_smp_ops = {
721 .send_ipi_single = loongson3_send_ipi_single,
722 .send_ipi_mask = loongson3_send_ipi_mask,
723 .init_secondary = loongson3_init_secondary,
724 .smp_finish = loongson3_smp_finish,
725 .boot_secondary = loongson3_boot_secondary,
726 .smp_setup = loongson3_smp_setup,
727 .prepare_cpus = loongson3_prepare_cpus,
728 #ifdef CONFIG_HOTPLUG_CPU
729 .cpu_disable = loongson3_cpu_disable,
730 .cpu_die = loongson3_cpu_die,
731 #endif
732 };
Ubuntu Artful kernel mirror