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MIPS: math-emu: Fix BC1{EQ,NE}Z emulation
[mirror_ubuntu-artful-kernel.git] / arch / mips / math-emu / cp1emu.c
1 /*
2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
22 *
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
26 *
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware FPU at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
32 *
33 * Note if you know that you won't have an FPU, then you'll get much
34 * better performance by compiling with -msoft-float!
35 */
36 #include <linux/sched.h>
37 #include <linux/debugfs.h>
38 #include <linux/kconfig.h>
39 #include <linux/percpu-defs.h>
40 #include <linux/perf_event.h>
41
42 #include <asm/branch.h>
43 #include <asm/inst.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/uaccess.h>
47
48 #include <asm/cpu-info.h>
49 #include <asm/processor.h>
50 #include <asm/fpu_emulator.h>
51 #include <asm/fpu.h>
52 #include <asm/mips-r2-to-r6-emul.h>
53
54 #include "ieee754.h"
55
56 /* Function which emulates a floating point instruction. */
57
58 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
59 mips_instruction);
60
61 static int fpux_emu(struct pt_regs *,
62 struct mips_fpu_struct *, mips_instruction, void *__user *);
63
64 /* Control registers */
65
66 #define FPCREG_RID 0 /* $0 = revision id */
67 #define FPCREG_FCCR 25 /* $25 = fccr */
68 #define FPCREG_FEXR 26 /* $26 = fexr */
69 #define FPCREG_FENR 28 /* $28 = fenr */
70 #define FPCREG_CSR 31 /* $31 = csr */
71
72 /* convert condition code register number to csr bit */
73 const unsigned int fpucondbit[8] = {
74 FPU_CSR_COND,
75 FPU_CSR_COND1,
76 FPU_CSR_COND2,
77 FPU_CSR_COND3,
78 FPU_CSR_COND4,
79 FPU_CSR_COND5,
80 FPU_CSR_COND6,
81 FPU_CSR_COND7
82 };
83
84 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
85 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
86 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
87 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
88 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
89
90 /*
91 * This functions translates a 32-bit microMIPS instruction
92 * into a 32-bit MIPS32 instruction. Returns 0 on success
93 * and SIGILL otherwise.
94 */
95 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
96 {
97 union mips_instruction insn = *insn_ptr;
98 union mips_instruction mips32_insn = insn;
99 int func, fmt, op;
100
101 switch (insn.mm_i_format.opcode) {
102 case mm_ldc132_op:
103 mips32_insn.mm_i_format.opcode = ldc1_op;
104 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
105 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
106 break;
107 case mm_lwc132_op:
108 mips32_insn.mm_i_format.opcode = lwc1_op;
109 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
110 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
111 break;
112 case mm_sdc132_op:
113 mips32_insn.mm_i_format.opcode = sdc1_op;
114 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
115 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
116 break;
117 case mm_swc132_op:
118 mips32_insn.mm_i_format.opcode = swc1_op;
119 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
120 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
121 break;
122 case mm_pool32i_op:
123 /* NOTE: offset is << by 1 if in microMIPS mode. */
124 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
125 (insn.mm_i_format.rt == mm_bc1t_op)) {
126 mips32_insn.fb_format.opcode = cop1_op;
127 mips32_insn.fb_format.bc = bc_op;
128 mips32_insn.fb_format.flag =
129 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
130 } else
131 return SIGILL;
132 break;
133 case mm_pool32f_op:
134 switch (insn.mm_fp0_format.func) {
135 case mm_32f_01_op:
136 case mm_32f_11_op:
137 case mm_32f_02_op:
138 case mm_32f_12_op:
139 case mm_32f_41_op:
140 case mm_32f_51_op:
141 case mm_32f_42_op:
142 case mm_32f_52_op:
143 op = insn.mm_fp0_format.func;
144 if (op == mm_32f_01_op)
145 func = madd_s_op;
146 else if (op == mm_32f_11_op)
147 func = madd_d_op;
148 else if (op == mm_32f_02_op)
149 func = nmadd_s_op;
150 else if (op == mm_32f_12_op)
151 func = nmadd_d_op;
152 else if (op == mm_32f_41_op)
153 func = msub_s_op;
154 else if (op == mm_32f_51_op)
155 func = msub_d_op;
156 else if (op == mm_32f_42_op)
157 func = nmsub_s_op;
158 else
159 func = nmsub_d_op;
160 mips32_insn.fp6_format.opcode = cop1x_op;
161 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
162 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
163 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
164 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
165 mips32_insn.fp6_format.func = func;
166 break;
167 case mm_32f_10_op:
168 func = -1; /* Invalid */
169 op = insn.mm_fp5_format.op & 0x7;
170 if (op == mm_ldxc1_op)
171 func = ldxc1_op;
172 else if (op == mm_sdxc1_op)
173 func = sdxc1_op;
174 else if (op == mm_lwxc1_op)
175 func = lwxc1_op;
176 else if (op == mm_swxc1_op)
177 func = swxc1_op;
178
179 if (func != -1) {
180 mips32_insn.r_format.opcode = cop1x_op;
181 mips32_insn.r_format.rs =
182 insn.mm_fp5_format.base;
183 mips32_insn.r_format.rt =
184 insn.mm_fp5_format.index;
185 mips32_insn.r_format.rd = 0;
186 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
187 mips32_insn.r_format.func = func;
188 } else
189 return SIGILL;
190 break;
191 case mm_32f_40_op:
192 op = -1; /* Invalid */
193 if (insn.mm_fp2_format.op == mm_fmovt_op)
194 op = 1;
195 else if (insn.mm_fp2_format.op == mm_fmovf_op)
196 op = 0;
197 if (op != -1) {
198 mips32_insn.fp0_format.opcode = cop1_op;
199 mips32_insn.fp0_format.fmt =
200 sdps_format[insn.mm_fp2_format.fmt];
201 mips32_insn.fp0_format.ft =
202 (insn.mm_fp2_format.cc<<2) + op;
203 mips32_insn.fp0_format.fs =
204 insn.mm_fp2_format.fs;
205 mips32_insn.fp0_format.fd =
206 insn.mm_fp2_format.fd;
207 mips32_insn.fp0_format.func = fmovc_op;
208 } else
209 return SIGILL;
210 break;
211 case mm_32f_60_op:
212 func = -1; /* Invalid */
213 if (insn.mm_fp0_format.op == mm_fadd_op)
214 func = fadd_op;
215 else if (insn.mm_fp0_format.op == mm_fsub_op)
216 func = fsub_op;
217 else if (insn.mm_fp0_format.op == mm_fmul_op)
218 func = fmul_op;
219 else if (insn.mm_fp0_format.op == mm_fdiv_op)
220 func = fdiv_op;
221 if (func != -1) {
222 mips32_insn.fp0_format.opcode = cop1_op;
223 mips32_insn.fp0_format.fmt =
224 sdps_format[insn.mm_fp0_format.fmt];
225 mips32_insn.fp0_format.ft =
226 insn.mm_fp0_format.ft;
227 mips32_insn.fp0_format.fs =
228 insn.mm_fp0_format.fs;
229 mips32_insn.fp0_format.fd =
230 insn.mm_fp0_format.fd;
231 mips32_insn.fp0_format.func = func;
232 } else
233 return SIGILL;
234 break;
235 case mm_32f_70_op:
236 func = -1; /* Invalid */
237 if (insn.mm_fp0_format.op == mm_fmovn_op)
238 func = fmovn_op;
239 else if (insn.mm_fp0_format.op == mm_fmovz_op)
240 func = fmovz_op;
241 if (func != -1) {
242 mips32_insn.fp0_format.opcode = cop1_op;
243 mips32_insn.fp0_format.fmt =
244 sdps_format[insn.mm_fp0_format.fmt];
245 mips32_insn.fp0_format.ft =
246 insn.mm_fp0_format.ft;
247 mips32_insn.fp0_format.fs =
248 insn.mm_fp0_format.fs;
249 mips32_insn.fp0_format.fd =
250 insn.mm_fp0_format.fd;
251 mips32_insn.fp0_format.func = func;
252 } else
253 return SIGILL;
254 break;
255 case mm_32f_73_op: /* POOL32FXF */
256 switch (insn.mm_fp1_format.op) {
257 case mm_movf0_op:
258 case mm_movf1_op:
259 case mm_movt0_op:
260 case mm_movt1_op:
261 if ((insn.mm_fp1_format.op & 0x7f) ==
262 mm_movf0_op)
263 op = 0;
264 else
265 op = 1;
266 mips32_insn.r_format.opcode = spec_op;
267 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
268 mips32_insn.r_format.rt =
269 (insn.mm_fp4_format.cc << 2) + op;
270 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
271 mips32_insn.r_format.re = 0;
272 mips32_insn.r_format.func = movc_op;
273 break;
274 case mm_fcvtd0_op:
275 case mm_fcvtd1_op:
276 case mm_fcvts0_op:
277 case mm_fcvts1_op:
278 if ((insn.mm_fp1_format.op & 0x7f) ==
279 mm_fcvtd0_op) {
280 func = fcvtd_op;
281 fmt = swl_format[insn.mm_fp3_format.fmt];
282 } else {
283 func = fcvts_op;
284 fmt = dwl_format[insn.mm_fp3_format.fmt];
285 }
286 mips32_insn.fp0_format.opcode = cop1_op;
287 mips32_insn.fp0_format.fmt = fmt;
288 mips32_insn.fp0_format.ft = 0;
289 mips32_insn.fp0_format.fs =
290 insn.mm_fp3_format.fs;
291 mips32_insn.fp0_format.fd =
292 insn.mm_fp3_format.rt;
293 mips32_insn.fp0_format.func = func;
294 break;
295 case mm_fmov0_op:
296 case mm_fmov1_op:
297 case mm_fabs0_op:
298 case mm_fabs1_op:
299 case mm_fneg0_op:
300 case mm_fneg1_op:
301 if ((insn.mm_fp1_format.op & 0x7f) ==
302 mm_fmov0_op)
303 func = fmov_op;
304 else if ((insn.mm_fp1_format.op & 0x7f) ==
305 mm_fabs0_op)
306 func = fabs_op;
307 else
308 func = fneg_op;
309 mips32_insn.fp0_format.opcode = cop1_op;
310 mips32_insn.fp0_format.fmt =
311 sdps_format[insn.mm_fp3_format.fmt];
312 mips32_insn.fp0_format.ft = 0;
313 mips32_insn.fp0_format.fs =
314 insn.mm_fp3_format.fs;
315 mips32_insn.fp0_format.fd =
316 insn.mm_fp3_format.rt;
317 mips32_insn.fp0_format.func = func;
318 break;
319 case mm_ffloorl_op:
320 case mm_ffloorw_op:
321 case mm_fceill_op:
322 case mm_fceilw_op:
323 case mm_ftruncl_op:
324 case mm_ftruncw_op:
325 case mm_froundl_op:
326 case mm_froundw_op:
327 case mm_fcvtl_op:
328 case mm_fcvtw_op:
329 if (insn.mm_fp1_format.op == mm_ffloorl_op)
330 func = ffloorl_op;
331 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
332 func = ffloor_op;
333 else if (insn.mm_fp1_format.op == mm_fceill_op)
334 func = fceill_op;
335 else if (insn.mm_fp1_format.op == mm_fceilw_op)
336 func = fceil_op;
337 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
338 func = ftruncl_op;
339 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
340 func = ftrunc_op;
341 else if (insn.mm_fp1_format.op == mm_froundl_op)
342 func = froundl_op;
343 else if (insn.mm_fp1_format.op == mm_froundw_op)
344 func = fround_op;
345 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
346 func = fcvtl_op;
347 else
348 func = fcvtw_op;
349 mips32_insn.fp0_format.opcode = cop1_op;
350 mips32_insn.fp0_format.fmt =
351 sd_format[insn.mm_fp1_format.fmt];
352 mips32_insn.fp0_format.ft = 0;
353 mips32_insn.fp0_format.fs =
354 insn.mm_fp1_format.fs;
355 mips32_insn.fp0_format.fd =
356 insn.mm_fp1_format.rt;
357 mips32_insn.fp0_format.func = func;
358 break;
359 case mm_frsqrt_op:
360 case mm_fsqrt_op:
361 case mm_frecip_op:
362 if (insn.mm_fp1_format.op == mm_frsqrt_op)
363 func = frsqrt_op;
364 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
365 func = fsqrt_op;
366 else
367 func = frecip_op;
368 mips32_insn.fp0_format.opcode = cop1_op;
369 mips32_insn.fp0_format.fmt =
370 sdps_format[insn.mm_fp1_format.fmt];
371 mips32_insn.fp0_format.ft = 0;
372 mips32_insn.fp0_format.fs =
373 insn.mm_fp1_format.fs;
374 mips32_insn.fp0_format.fd =
375 insn.mm_fp1_format.rt;
376 mips32_insn.fp0_format.func = func;
377 break;
378 case mm_mfc1_op:
379 case mm_mtc1_op:
380 case mm_cfc1_op:
381 case mm_ctc1_op:
382 case mm_mfhc1_op:
383 case mm_mthc1_op:
384 if (insn.mm_fp1_format.op == mm_mfc1_op)
385 op = mfc_op;
386 else if (insn.mm_fp1_format.op == mm_mtc1_op)
387 op = mtc_op;
388 else if (insn.mm_fp1_format.op == mm_cfc1_op)
389 op = cfc_op;
390 else if (insn.mm_fp1_format.op == mm_ctc1_op)
391 op = ctc_op;
392 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
393 op = mfhc_op;
394 else
395 op = mthc_op;
396 mips32_insn.fp1_format.opcode = cop1_op;
397 mips32_insn.fp1_format.op = op;
398 mips32_insn.fp1_format.rt =
399 insn.mm_fp1_format.rt;
400 mips32_insn.fp1_format.fs =
401 insn.mm_fp1_format.fs;
402 mips32_insn.fp1_format.fd = 0;
403 mips32_insn.fp1_format.func = 0;
404 break;
405 default:
406 return SIGILL;
407 }
408 break;
409 case mm_32f_74_op: /* c.cond.fmt */
410 mips32_insn.fp0_format.opcode = cop1_op;
411 mips32_insn.fp0_format.fmt =
412 sdps_format[insn.mm_fp4_format.fmt];
413 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
414 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
415 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
416 mips32_insn.fp0_format.func =
417 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
418 break;
419 default:
420 return SIGILL;
421 }
422 break;
423 default:
424 return SIGILL;
425 }
426
427 *insn_ptr = mips32_insn;
428 return 0;
429 }
430
431 /*
432 * Redundant with logic already in kernel/branch.c,
433 * embedded in compute_return_epc. At some point,
434 * a single subroutine should be used across both
435 * modules.
436 */
437 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
438 unsigned long *contpc)
439 {
440 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
441 unsigned int fcr31;
442 unsigned int bit = 0;
443
444 switch (insn.i_format.opcode) {
445 case spec_op:
446 switch (insn.r_format.func) {
447 case jalr_op:
448 regs->regs[insn.r_format.rd] =
449 regs->cp0_epc + dec_insn.pc_inc +
450 dec_insn.next_pc_inc;
451 /* Fall through */
452 case jr_op:
453 /* For R6, JR already emulated in jalr_op */
454 if (NO_R6EMU && insn.r_format.func == jr_op)
455 break;
456 *contpc = regs->regs[insn.r_format.rs];
457 return 1;
458 }
459 break;
460 case bcond_op:
461 switch (insn.i_format.rt) {
462 case bltzal_op:
463 case bltzall_op:
464 if (NO_R6EMU && (insn.i_format.rs ||
465 insn.i_format.rt == bltzall_op))
466 break;
467
468 regs->regs[31] = regs->cp0_epc +
469 dec_insn.pc_inc +
470 dec_insn.next_pc_inc;
471 /* Fall through */
472 case bltzl_op:
473 if (NO_R6EMU)
474 break;
475 case bltz_op:
476 if ((long)regs->regs[insn.i_format.rs] < 0)
477 *contpc = regs->cp0_epc +
478 dec_insn.pc_inc +
479 (insn.i_format.simmediate << 2);
480 else
481 *contpc = regs->cp0_epc +
482 dec_insn.pc_inc +
483 dec_insn.next_pc_inc;
484 return 1;
485 case bgezal_op:
486 case bgezall_op:
487 if (NO_R6EMU && (insn.i_format.rs ||
488 insn.i_format.rt == bgezall_op))
489 break;
490
491 regs->regs[31] = regs->cp0_epc +
492 dec_insn.pc_inc +
493 dec_insn.next_pc_inc;
494 /* Fall through */
495 case bgezl_op:
496 if (NO_R6EMU)
497 break;
498 case bgez_op:
499 if ((long)regs->regs[insn.i_format.rs] >= 0)
500 *contpc = regs->cp0_epc +
501 dec_insn.pc_inc +
502 (insn.i_format.simmediate << 2);
503 else
504 *contpc = regs->cp0_epc +
505 dec_insn.pc_inc +
506 dec_insn.next_pc_inc;
507 return 1;
508 }
509 break;
510 case jalx_op:
511 set_isa16_mode(bit);
512 case jal_op:
513 regs->regs[31] = regs->cp0_epc +
514 dec_insn.pc_inc +
515 dec_insn.next_pc_inc;
516 /* Fall through */
517 case j_op:
518 *contpc = regs->cp0_epc + dec_insn.pc_inc;
519 *contpc >>= 28;
520 *contpc <<= 28;
521 *contpc |= (insn.j_format.target << 2);
522 /* Set microMIPS mode bit: XOR for jalx. */
523 *contpc ^= bit;
524 return 1;
525 case beql_op:
526 if (NO_R6EMU)
527 break;
528 case beq_op:
529 if (regs->regs[insn.i_format.rs] ==
530 regs->regs[insn.i_format.rt])
531 *contpc = regs->cp0_epc +
532 dec_insn.pc_inc +
533 (insn.i_format.simmediate << 2);
534 else
535 *contpc = regs->cp0_epc +
536 dec_insn.pc_inc +
537 dec_insn.next_pc_inc;
538 return 1;
539 case bnel_op:
540 if (NO_R6EMU)
541 break;
542 case bne_op:
543 if (regs->regs[insn.i_format.rs] !=
544 regs->regs[insn.i_format.rt])
545 *contpc = regs->cp0_epc +
546 dec_insn.pc_inc +
547 (insn.i_format.simmediate << 2);
548 else
549 *contpc = regs->cp0_epc +
550 dec_insn.pc_inc +
551 dec_insn.next_pc_inc;
552 return 1;
553 case blezl_op:
554 if (!insn.i_format.rt && NO_R6EMU)
555 break;
556 case blez_op:
557
558 /*
559 * Compact branches for R6 for the
560 * blez and blezl opcodes.
561 * BLEZ | rs = 0 | rt != 0 == BLEZALC
562 * BLEZ | rs = rt != 0 == BGEZALC
563 * BLEZ | rs != 0 | rt != 0 == BGEUC
564 * BLEZL | rs = 0 | rt != 0 == BLEZC
565 * BLEZL | rs = rt != 0 == BGEZC
566 * BLEZL | rs != 0 | rt != 0 == BGEC
567 *
568 * For real BLEZ{,L}, rt is always 0.
569 */
570 if (cpu_has_mips_r6 && insn.i_format.rt) {
571 if ((insn.i_format.opcode == blez_op) &&
572 ((!insn.i_format.rs && insn.i_format.rt) ||
573 (insn.i_format.rs == insn.i_format.rt)))
574 regs->regs[31] = regs->cp0_epc +
575 dec_insn.pc_inc;
576 *contpc = regs->cp0_epc + dec_insn.pc_inc +
577 dec_insn.next_pc_inc;
578
579 return 1;
580 }
581 if ((long)regs->regs[insn.i_format.rs] <= 0)
582 *contpc = regs->cp0_epc +
583 dec_insn.pc_inc +
584 (insn.i_format.simmediate << 2);
585 else
586 *contpc = regs->cp0_epc +
587 dec_insn.pc_inc +
588 dec_insn.next_pc_inc;
589 return 1;
590 case bgtzl_op:
591 if (!insn.i_format.rt && NO_R6EMU)
592 break;
593 case bgtz_op:
594 /*
595 * Compact branches for R6 for the
596 * bgtz and bgtzl opcodes.
597 * BGTZ | rs = 0 | rt != 0 == BGTZALC
598 * BGTZ | rs = rt != 0 == BLTZALC
599 * BGTZ | rs != 0 | rt != 0 == BLTUC
600 * BGTZL | rs = 0 | rt != 0 == BGTZC
601 * BGTZL | rs = rt != 0 == BLTZC
602 * BGTZL | rs != 0 | rt != 0 == BLTC
603 *
604 * *ZALC varint for BGTZ &&& rt != 0
605 * For real GTZ{,L}, rt is always 0.
606 */
607 if (cpu_has_mips_r6 && insn.i_format.rt) {
608 if ((insn.i_format.opcode == blez_op) &&
609 ((!insn.i_format.rs && insn.i_format.rt) ||
610 (insn.i_format.rs == insn.i_format.rt)))
611 regs->regs[31] = regs->cp0_epc +
612 dec_insn.pc_inc;
613 *contpc = regs->cp0_epc + dec_insn.pc_inc +
614 dec_insn.next_pc_inc;
615
616 return 1;
617 }
618
619 if ((long)regs->regs[insn.i_format.rs] > 0)
620 *contpc = regs->cp0_epc +
621 dec_insn.pc_inc +
622 (insn.i_format.simmediate << 2);
623 else
624 *contpc = regs->cp0_epc +
625 dec_insn.pc_inc +
626 dec_insn.next_pc_inc;
627 return 1;
628 case cbcond0_op:
629 case cbcond1_op:
630 if (!cpu_has_mips_r6)
631 break;
632 if (insn.i_format.rt && !insn.i_format.rs)
633 regs->regs[31] = regs->cp0_epc + 4;
634 *contpc = regs->cp0_epc + dec_insn.pc_inc +
635 dec_insn.next_pc_inc;
636
637 return 1;
638 #ifdef CONFIG_CPU_CAVIUM_OCTEON
639 case lwc2_op: /* This is bbit0 on Octeon */
640 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
641 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
642 else
643 *contpc = regs->cp0_epc + 8;
644 return 1;
645 case ldc2_op: /* This is bbit032 on Octeon */
646 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
647 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
648 else
649 *contpc = regs->cp0_epc + 8;
650 return 1;
651 case swc2_op: /* This is bbit1 on Octeon */
652 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
653 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
654 else
655 *contpc = regs->cp0_epc + 8;
656 return 1;
657 case sdc2_op: /* This is bbit132 on Octeon */
658 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
659 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
660 else
661 *contpc = regs->cp0_epc + 8;
662 return 1;
663 #else
664 case bc6_op:
665 /*
666 * Only valid for MIPS R6 but we can still end up
667 * here from a broken userland so just tell emulator
668 * this is not a branch and let it break later on.
669 */
670 if (!cpu_has_mips_r6)
671 break;
672 *contpc = regs->cp0_epc + dec_insn.pc_inc +
673 dec_insn.next_pc_inc;
674
675 return 1;
676 case balc6_op:
677 if (!cpu_has_mips_r6)
678 break;
679 regs->regs[31] = regs->cp0_epc + 4;
680 *contpc = regs->cp0_epc + dec_insn.pc_inc +
681 dec_insn.next_pc_inc;
682
683 return 1;
684 case beqzcjic_op:
685 if (!cpu_has_mips_r6)
686 break;
687 *contpc = regs->cp0_epc + dec_insn.pc_inc +
688 dec_insn.next_pc_inc;
689
690 return 1;
691 case bnezcjialc_op:
692 if (!cpu_has_mips_r6)
693 break;
694 if (!insn.i_format.rs)
695 regs->regs[31] = regs->cp0_epc + 4;
696 *contpc = regs->cp0_epc + dec_insn.pc_inc +
697 dec_insn.next_pc_inc;
698
699 return 1;
700 #endif
701 case cop0_op:
702 case cop1_op:
703 /* Need to check for R6 bc1nez and bc1eqz branches */
704 if (cpu_has_mips_r6 &&
705 ((insn.i_format.rs == bc1eqz_op) ||
706 (insn.i_format.rs == bc1nez_op))) {
707 bit = 0;
708 switch (insn.i_format.rs) {
709 case bc1eqz_op:
710 if (get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)
711 bit = 1;
712 break;
713 case bc1nez_op:
714 if (!(get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1))
715 bit = 1;
716 break;
717 }
718 if (bit)
719 *contpc = regs->cp0_epc +
720 dec_insn.pc_inc +
721 (insn.i_format.simmediate << 2);
722 else
723 *contpc = regs->cp0_epc +
724 dec_insn.pc_inc +
725 dec_insn.next_pc_inc;
726
727 return 1;
728 }
729 /* R2/R6 compatible cop1 instruction. Fall through */
730 case cop2_op:
731 case cop1x_op:
732 if (insn.i_format.rs == bc_op) {
733 preempt_disable();
734 if (is_fpu_owner())
735 fcr31 = read_32bit_cp1_register(CP1_STATUS);
736 else
737 fcr31 = current->thread.fpu.fcr31;
738 preempt_enable();
739
740 bit = (insn.i_format.rt >> 2);
741 bit += (bit != 0);
742 bit += 23;
743 switch (insn.i_format.rt & 3) {
744 case 0: /* bc1f */
745 case 2: /* bc1fl */
746 if (~fcr31 & (1 << bit))
747 *contpc = regs->cp0_epc +
748 dec_insn.pc_inc +
749 (insn.i_format.simmediate << 2);
750 else
751 *contpc = regs->cp0_epc +
752 dec_insn.pc_inc +
753 dec_insn.next_pc_inc;
754 return 1;
755 case 1: /* bc1t */
756 case 3: /* bc1tl */
757 if (fcr31 & (1 << bit))
758 *contpc = regs->cp0_epc +
759 dec_insn.pc_inc +
760 (insn.i_format.simmediate << 2);
761 else
762 *contpc = regs->cp0_epc +
763 dec_insn.pc_inc +
764 dec_insn.next_pc_inc;
765 return 1;
766 }
767 }
768 break;
769 }
770 return 0;
771 }
772
773 /*
774 * In the Linux kernel, we support selection of FPR format on the
775 * basis of the Status.FR bit. If an FPU is not present, the FR bit
776 * is hardwired to zero, which would imply a 32-bit FPU even for
777 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
778 * FPU emu is slow and bulky and optimizing this function offers fairly
779 * sizeable benefits so we try to be clever and make this function return
780 * a constant whenever possible, that is on 64-bit kernels without O32
781 * compatibility enabled and on 32-bit without 64-bit FPU support.
782 */
783 static inline int cop1_64bit(struct pt_regs *xcp)
784 {
785 if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
786 return 1;
787 else if (config_enabled(CONFIG_32BIT) &&
788 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
789 return 0;
790
791 return !test_thread_flag(TIF_32BIT_FPREGS);
792 }
793
794 static inline bool hybrid_fprs(void)
795 {
796 return test_thread_flag(TIF_HYBRID_FPREGS);
797 }
798
799 #define SIFROMREG(si, x) \
800 do { \
801 if (cop1_64bit(xcp) && !hybrid_fprs()) \
802 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \
803 else \
804 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
805 } while (0)
806
807 #define SITOREG(si, x) \
808 do { \
809 if (cop1_64bit(xcp) && !hybrid_fprs()) { \
810 unsigned i; \
811 set_fpr32(&ctx->fpr[x], 0, si); \
812 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
813 set_fpr32(&ctx->fpr[x], i, 0); \
814 } else { \
815 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
816 } \
817 } while (0)
818
819 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
820
821 #define SITOHREG(si, x) \
822 do { \
823 unsigned i; \
824 set_fpr32(&ctx->fpr[x], 1, si); \
825 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
826 set_fpr32(&ctx->fpr[x], i, 0); \
827 } while (0)
828
829 #define DIFROMREG(di, x) \
830 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
831
832 #define DITOREG(di, x) \
833 do { \
834 unsigned fpr, i; \
835 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
836 set_fpr64(&ctx->fpr[fpr], 0, di); \
837 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
838 set_fpr64(&ctx->fpr[fpr], i, 0); \
839 } while (0)
840
841 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
842 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
843 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
844 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
845
846 /*
847 * Emulate a CFC1 instruction.
848 */
849 static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
850 mips_instruction ir)
851 {
852 u32 fcr31 = ctx->fcr31;
853 u32 value = 0;
854
855 switch (MIPSInst_RD(ir)) {
856 case FPCREG_CSR:
857 value = fcr31;
858 pr_debug("%p gpr[%d]<-csr=%08x\n",
859 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
860 break;
861
862 case FPCREG_FENR:
863 if (!cpu_has_mips_r)
864 break;
865 value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
866 MIPS_FENR_FS;
867 value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM);
868 pr_debug("%p gpr[%d]<-enr=%08x\n",
869 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
870 break;
871
872 case FPCREG_FEXR:
873 if (!cpu_has_mips_r)
874 break;
875 value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
876 pr_debug("%p gpr[%d]<-exr=%08x\n",
877 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
878 break;
879
880 case FPCREG_FCCR:
881 if (!cpu_has_mips_r)
882 break;
883 value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
884 MIPS_FCCR_COND0;
885 value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
886 (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0);
887 pr_debug("%p gpr[%d]<-ccr=%08x\n",
888 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
889 break;
890
891 case FPCREG_RID:
892 value = boot_cpu_data.fpu_id;
893 break;
894
895 default:
896 break;
897 }
898
899 if (MIPSInst_RT(ir))
900 xcp->regs[MIPSInst_RT(ir)] = value;
901 }
902
903 /*
904 * Emulate a CTC1 instruction.
905 */
906 static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
907 mips_instruction ir)
908 {
909 u32 fcr31 = ctx->fcr31;
910 u32 value;
911 u32 mask;
912
913 if (MIPSInst_RT(ir) == 0)
914 value = 0;
915 else
916 value = xcp->regs[MIPSInst_RT(ir)];
917
918 switch (MIPSInst_RD(ir)) {
919 case FPCREG_CSR:
920 pr_debug("%p gpr[%d]->csr=%08x\n",
921 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
922
923 /* Preserve read-only bits. */
924 mask = boot_cpu_data.fpu_msk31;
925 fcr31 = (value & ~mask) | (fcr31 & mask);
926 break;
927
928 case FPCREG_FENR:
929 if (!cpu_has_mips_r)
930 break;
931 pr_debug("%p gpr[%d]->enr=%08x\n",
932 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
933 fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM);
934 fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
935 FPU_CSR_FS;
936 fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM);
937 break;
938
939 case FPCREG_FEXR:
940 if (!cpu_has_mips_r)
941 break;
942 pr_debug("%p gpr[%d]->exr=%08x\n",
943 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
944 fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S);
945 fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
946 break;
947
948 case FPCREG_FCCR:
949 if (!cpu_has_mips_r)
950 break;
951 pr_debug("%p gpr[%d]->ccr=%08x\n",
952 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
953 fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND);
954 fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
955 FPU_CSR_COND;
956 fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
957 FPU_CSR_CONDX;
958 break;
959
960 default:
961 break;
962 }
963
964 ctx->fcr31 = fcr31;
965 }
966
967 /*
968 * Emulate the single floating point instruction pointed at by EPC.
969 * Two instructions if the instruction is in a branch delay slot.
970 */
971
972 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
973 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
974 {
975 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
976 unsigned int cond, cbit, bit0;
977 mips_instruction ir;
978 int likely, pc_inc;
979 union fpureg *fpr;
980 u32 __user *wva;
981 u64 __user *dva;
982 u32 wval;
983 u64 dval;
984 int sig;
985
986 /*
987 * These are giving gcc a gentle hint about what to expect in
988 * dec_inst in order to do better optimization.
989 */
990 if (!cpu_has_mmips && dec_insn.micro_mips_mode)
991 unreachable();
992
993 /* XXX NEC Vr54xx bug workaround */
994 if (delay_slot(xcp)) {
995 if (dec_insn.micro_mips_mode) {
996 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
997 clear_delay_slot(xcp);
998 } else {
999 if (!isBranchInstr(xcp, dec_insn, &contpc))
1000 clear_delay_slot(xcp);
1001 }
1002 }
1003
1004 if (delay_slot(xcp)) {
1005 /*
1006 * The instruction to be emulated is in a branch delay slot
1007 * which means that we have to emulate the branch instruction
1008 * BEFORE we do the cop1 instruction.
1009 *
1010 * This branch could be a COP1 branch, but in that case we
1011 * would have had a trap for that instruction, and would not
1012 * come through this route.
1013 *
1014 * Linux MIPS branch emulator operates on context, updating the
1015 * cp0_epc.
1016 */
1017 ir = dec_insn.next_insn; /* process delay slot instr */
1018 pc_inc = dec_insn.next_pc_inc;
1019 } else {
1020 ir = dec_insn.insn; /* process current instr */
1021 pc_inc = dec_insn.pc_inc;
1022 }
1023
1024 /*
1025 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
1026 * instructions, we want to convert microMIPS FPU instructions
1027 * into MIPS32 instructions so that we could reuse all of the
1028 * FPU emulation code.
1029 *
1030 * NOTE: We cannot do this for branch instructions since they
1031 * are not a subset. Example: Cannot emulate a 16-bit
1032 * aligned target address with a MIPS32 instruction.
1033 */
1034 if (dec_insn.micro_mips_mode) {
1035 /*
1036 * If next instruction is a 16-bit instruction, then it
1037 * it cannot be a FPU instruction. This could happen
1038 * since we can be called for non-FPU instructions.
1039 */
1040 if ((pc_inc == 2) ||
1041 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
1042 == SIGILL))
1043 return SIGILL;
1044 }
1045
1046 emul:
1047 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
1048 MIPS_FPU_EMU_INC_STATS(emulated);
1049 switch (MIPSInst_OPCODE(ir)) {
1050 case ldc1_op:
1051 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1052 MIPSInst_SIMM(ir));
1053 MIPS_FPU_EMU_INC_STATS(loads);
1054
1055 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
1056 MIPS_FPU_EMU_INC_STATS(errors);
1057 *fault_addr = dva;
1058 return SIGBUS;
1059 }
1060 if (__get_user(dval, dva)) {
1061 MIPS_FPU_EMU_INC_STATS(errors);
1062 *fault_addr = dva;
1063 return SIGSEGV;
1064 }
1065 DITOREG(dval, MIPSInst_RT(ir));
1066 break;
1067
1068 case sdc1_op:
1069 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1070 MIPSInst_SIMM(ir));
1071 MIPS_FPU_EMU_INC_STATS(stores);
1072 DIFROMREG(dval, MIPSInst_RT(ir));
1073 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
1074 MIPS_FPU_EMU_INC_STATS(errors);
1075 *fault_addr = dva;
1076 return SIGBUS;
1077 }
1078 if (__put_user(dval, dva)) {
1079 MIPS_FPU_EMU_INC_STATS(errors);
1080 *fault_addr = dva;
1081 return SIGSEGV;
1082 }
1083 break;
1084
1085 case lwc1_op:
1086 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1087 MIPSInst_SIMM(ir));
1088 MIPS_FPU_EMU_INC_STATS(loads);
1089 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
1090 MIPS_FPU_EMU_INC_STATS(errors);
1091 *fault_addr = wva;
1092 return SIGBUS;
1093 }
1094 if (__get_user(wval, wva)) {
1095 MIPS_FPU_EMU_INC_STATS(errors);
1096 *fault_addr = wva;
1097 return SIGSEGV;
1098 }
1099 SITOREG(wval, MIPSInst_RT(ir));
1100 break;
1101
1102 case swc1_op:
1103 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1104 MIPSInst_SIMM(ir));
1105 MIPS_FPU_EMU_INC_STATS(stores);
1106 SIFROMREG(wval, MIPSInst_RT(ir));
1107 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
1108 MIPS_FPU_EMU_INC_STATS(errors);
1109 *fault_addr = wva;
1110 return SIGBUS;
1111 }
1112 if (__put_user(wval, wva)) {
1113 MIPS_FPU_EMU_INC_STATS(errors);
1114 *fault_addr = wva;
1115 return SIGSEGV;
1116 }
1117 break;
1118
1119 case cop1_op:
1120 switch (MIPSInst_RS(ir)) {
1121 case dmfc_op:
1122 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1123 return SIGILL;
1124
1125 /* copregister fs -> gpr[rt] */
1126 if (MIPSInst_RT(ir) != 0) {
1127 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1128 MIPSInst_RD(ir));
1129 }
1130 break;
1131
1132 case dmtc_op:
1133 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1134 return SIGILL;
1135
1136 /* copregister fs <- rt */
1137 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1138 break;
1139
1140 case mfhc_op:
1141 if (!cpu_has_mips_r2_r6)
1142 goto sigill;
1143
1144 /* copregister rd -> gpr[rt] */
1145 if (MIPSInst_RT(ir) != 0) {
1146 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1147 MIPSInst_RD(ir));
1148 }
1149 break;
1150
1151 case mthc_op:
1152 if (!cpu_has_mips_r2_r6)
1153 goto sigill;
1154
1155 /* copregister rd <- gpr[rt] */
1156 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1157 break;
1158
1159 case mfc_op:
1160 /* copregister rd -> gpr[rt] */
1161 if (MIPSInst_RT(ir) != 0) {
1162 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1163 MIPSInst_RD(ir));
1164 }
1165 break;
1166
1167 case mtc_op:
1168 /* copregister rd <- rt */
1169 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1170 break;
1171
1172 case cfc_op:
1173 /* cop control register rd -> gpr[rt] */
1174 cop1_cfc(xcp, ctx, ir);
1175 break;
1176
1177 case ctc_op:
1178 /* copregister rd <- rt */
1179 cop1_ctc(xcp, ctx, ir);
1180 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1181 return SIGFPE;
1182 }
1183 break;
1184
1185 case bc1eqz_op:
1186 case bc1nez_op:
1187 if (!cpu_has_mips_r6 || delay_slot(xcp))
1188 return SIGILL;
1189
1190 cond = likely = 0;
1191 fpr = &current->thread.fpu.fpr[MIPSInst_RT(ir)];
1192 bit0 = get_fpr32(fpr, 0) & 0x1;
1193 switch (MIPSInst_RS(ir)) {
1194 case bc1eqz_op:
1195 cond = bit0 == 0;
1196 break;
1197 case bc1nez_op:
1198 cond = bit0 != 0;
1199 break;
1200 }
1201 goto branch_common;
1202
1203 case bc_op:
1204 if (delay_slot(xcp))
1205 return SIGILL;
1206
1207 if (cpu_has_mips_4_5_r)
1208 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1209 else
1210 cbit = FPU_CSR_COND;
1211 cond = ctx->fcr31 & cbit;
1212
1213 likely = 0;
1214 switch (MIPSInst_RT(ir) & 3) {
1215 case bcfl_op:
1216 if (cpu_has_mips_2_3_4_5_r)
1217 likely = 1;
1218 /* Fall through */
1219 case bcf_op:
1220 cond = !cond;
1221 break;
1222 case bctl_op:
1223 if (cpu_has_mips_2_3_4_5_r)
1224 likely = 1;
1225 /* Fall through */
1226 case bct_op:
1227 break;
1228 }
1229 branch_common:
1230 set_delay_slot(xcp);
1231 if (cond) {
1232 /*
1233 * Branch taken: emulate dslot instruction
1234 */
1235 unsigned long bcpc;
1236
1237 /*
1238 * Remember EPC at the branch to point back
1239 * at so that any delay-slot instruction
1240 * signal is not silently ignored.
1241 */
1242 bcpc = xcp->cp0_epc;
1243 xcp->cp0_epc += dec_insn.pc_inc;
1244
1245 contpc = MIPSInst_SIMM(ir);
1246 ir = dec_insn.next_insn;
1247 if (dec_insn.micro_mips_mode) {
1248 contpc = (xcp->cp0_epc + (contpc << 1));
1249
1250 /* If 16-bit instruction, not FPU. */
1251 if ((dec_insn.next_pc_inc == 2) ||
1252 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1253
1254 /*
1255 * Since this instruction will
1256 * be put on the stack with
1257 * 32-bit words, get around
1258 * this problem by putting a
1259 * NOP16 as the second one.
1260 */
1261 if (dec_insn.next_pc_inc == 2)
1262 ir = (ir & (~0xffff)) | MM_NOP16;
1263
1264 /*
1265 * Single step the non-CP1
1266 * instruction in the dslot.
1267 */
1268 sig = mips_dsemul(xcp, ir,
1269 contpc);
1270 if (sig < 0)
1271 break;
1272 if (sig)
1273 xcp->cp0_epc = bcpc;
1274 /*
1275 * SIGILL forces out of
1276 * the emulation loop.
1277 */
1278 return sig ? sig : SIGILL;
1279 }
1280 } else
1281 contpc = (xcp->cp0_epc + (contpc << 2));
1282
1283 switch (MIPSInst_OPCODE(ir)) {
1284 case lwc1_op:
1285 case swc1_op:
1286 goto emul;
1287
1288 case ldc1_op:
1289 case sdc1_op:
1290 if (cpu_has_mips_2_3_4_5_r)
1291 goto emul;
1292
1293 goto bc_sigill;
1294
1295 case cop1_op:
1296 goto emul;
1297
1298 case cop1x_op:
1299 if (cpu_has_mips_4_5_64_r2_r6)
1300 /* its one of ours */
1301 goto emul;
1302
1303 goto bc_sigill;
1304
1305 case spec_op:
1306 switch (MIPSInst_FUNC(ir)) {
1307 case movc_op:
1308 if (cpu_has_mips_4_5_r)
1309 goto emul;
1310
1311 goto bc_sigill;
1312 }
1313 break;
1314
1315 bc_sigill:
1316 xcp->cp0_epc = bcpc;
1317 return SIGILL;
1318 }
1319
1320 /*
1321 * Single step the non-cp1
1322 * instruction in the dslot
1323 */
1324 sig = mips_dsemul(xcp, ir, contpc);
1325 if (sig < 0)
1326 break;
1327 if (sig)
1328 xcp->cp0_epc = bcpc;
1329 /* SIGILL forces out of the emulation loop. */
1330 return sig ? sig : SIGILL;
1331 } else if (likely) { /* branch not taken */
1332 /*
1333 * branch likely nullifies
1334 * dslot if not taken
1335 */
1336 xcp->cp0_epc += dec_insn.pc_inc;
1337 contpc += dec_insn.pc_inc;
1338 /*
1339 * else continue & execute
1340 * dslot as normal insn
1341 */
1342 }
1343 break;
1344
1345 default:
1346 if (!(MIPSInst_RS(ir) & 0x10))
1347 return SIGILL;
1348
1349 /* a real fpu computation instruction */
1350 if ((sig = fpu_emu(xcp, ctx, ir)))
1351 return sig;
1352 }
1353 break;
1354
1355 case cop1x_op:
1356 if (!cpu_has_mips_4_5_64_r2_r6)
1357 return SIGILL;
1358
1359 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1360 if (sig)
1361 return sig;
1362 break;
1363
1364 case spec_op:
1365 if (!cpu_has_mips_4_5_r)
1366 return SIGILL;
1367
1368 if (MIPSInst_FUNC(ir) != movc_op)
1369 return SIGILL;
1370 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1371 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1372 xcp->regs[MIPSInst_RD(ir)] =
1373 xcp->regs[MIPSInst_RS(ir)];
1374 break;
1375 default:
1376 sigill:
1377 return SIGILL;
1378 }
1379
1380 /* we did it !! */
1381 xcp->cp0_epc = contpc;
1382 clear_delay_slot(xcp);
1383
1384 return 0;
1385 }
1386
1387 /*
1388 * Conversion table from MIPS compare ops 48-63
1389 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1390 */
1391 static const unsigned char cmptab[8] = {
1392 0, /* cmp_0 (sig) cmp_sf */
1393 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1394 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1395 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1396 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1397 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1398 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1399 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1400 };
1401
1402 static const unsigned char negative_cmptab[8] = {
1403 0, /* Reserved */
1404 IEEE754_CLT | IEEE754_CGT | IEEE754_CEQ,
1405 IEEE754_CLT | IEEE754_CGT | IEEE754_CUN,
1406 IEEE754_CLT | IEEE754_CGT,
1407 /* Reserved */
1408 };
1409
1410
1411 /*
1412 * Additional MIPS4 instructions
1413 */
1414
1415 #define DEF3OP(name, p, f1, f2, f3) \
1416 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1417 union ieee754##p s, union ieee754##p t) \
1418 { \
1419 struct _ieee754_csr ieee754_csr_save; \
1420 s = f1(s, t); \
1421 ieee754_csr_save = ieee754_csr; \
1422 s = f2(s, r); \
1423 ieee754_csr_save.cx |= ieee754_csr.cx; \
1424 ieee754_csr_save.sx |= ieee754_csr.sx; \
1425 s = f3(s); \
1426 ieee754_csr.cx |= ieee754_csr_save.cx; \
1427 ieee754_csr.sx |= ieee754_csr_save.sx; \
1428 return s; \
1429 }
1430
1431 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1432 {
1433 return ieee754dp_div(ieee754dp_one(0), d);
1434 }
1435
1436 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1437 {
1438 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1439 }
1440
1441 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1442 {
1443 return ieee754sp_div(ieee754sp_one(0), s);
1444 }
1445
1446 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1447 {
1448 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1449 }
1450
1451 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1452 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1453 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1454 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1455 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1456 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1457 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1458 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1459
1460 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1461 mips_instruction ir, void *__user *fault_addr)
1462 {
1463 unsigned rcsr = 0; /* resulting csr */
1464
1465 MIPS_FPU_EMU_INC_STATS(cp1xops);
1466
1467 switch (MIPSInst_FMA_FFMT(ir)) {
1468 case s_fmt:{ /* 0 */
1469
1470 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1471 union ieee754sp fd, fr, fs, ft;
1472 u32 __user *va;
1473 u32 val;
1474
1475 switch (MIPSInst_FUNC(ir)) {
1476 case lwxc1_op:
1477 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1478 xcp->regs[MIPSInst_FT(ir)]);
1479
1480 MIPS_FPU_EMU_INC_STATS(loads);
1481 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1482 MIPS_FPU_EMU_INC_STATS(errors);
1483 *fault_addr = va;
1484 return SIGBUS;
1485 }
1486 if (__get_user(val, va)) {
1487 MIPS_FPU_EMU_INC_STATS(errors);
1488 *fault_addr = va;
1489 return SIGSEGV;
1490 }
1491 SITOREG(val, MIPSInst_FD(ir));
1492 break;
1493
1494 case swxc1_op:
1495 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1496 xcp->regs[MIPSInst_FT(ir)]);
1497
1498 MIPS_FPU_EMU_INC_STATS(stores);
1499
1500 SIFROMREG(val, MIPSInst_FS(ir));
1501 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1502 MIPS_FPU_EMU_INC_STATS(errors);
1503 *fault_addr = va;
1504 return SIGBUS;
1505 }
1506 if (put_user(val, va)) {
1507 MIPS_FPU_EMU_INC_STATS(errors);
1508 *fault_addr = va;
1509 return SIGSEGV;
1510 }
1511 break;
1512
1513 case madd_s_op:
1514 handler = fpemu_sp_madd;
1515 goto scoptop;
1516 case msub_s_op:
1517 handler = fpemu_sp_msub;
1518 goto scoptop;
1519 case nmadd_s_op:
1520 handler = fpemu_sp_nmadd;
1521 goto scoptop;
1522 case nmsub_s_op:
1523 handler = fpemu_sp_nmsub;
1524 goto scoptop;
1525
1526 scoptop:
1527 SPFROMREG(fr, MIPSInst_FR(ir));
1528 SPFROMREG(fs, MIPSInst_FS(ir));
1529 SPFROMREG(ft, MIPSInst_FT(ir));
1530 fd = (*handler) (fr, fs, ft);
1531 SPTOREG(fd, MIPSInst_FD(ir));
1532
1533 copcsr:
1534 if (ieee754_cxtest(IEEE754_INEXACT)) {
1535 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1536 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1537 }
1538 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1539 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1540 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1541 }
1542 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1543 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1544 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1545 }
1546 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1547 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1548 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1549 }
1550
1551 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1552 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1553 /*printk ("SIGFPE: FPU csr = %08x\n",
1554 ctx->fcr31); */
1555 return SIGFPE;
1556 }
1557
1558 break;
1559
1560 default:
1561 return SIGILL;
1562 }
1563 break;
1564 }
1565
1566 case d_fmt:{ /* 1 */
1567 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1568 union ieee754dp fd, fr, fs, ft;
1569 u64 __user *va;
1570 u64 val;
1571
1572 switch (MIPSInst_FUNC(ir)) {
1573 case ldxc1_op:
1574 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1575 xcp->regs[MIPSInst_FT(ir)]);
1576
1577 MIPS_FPU_EMU_INC_STATS(loads);
1578 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1579 MIPS_FPU_EMU_INC_STATS(errors);
1580 *fault_addr = va;
1581 return SIGBUS;
1582 }
1583 if (__get_user(val, va)) {
1584 MIPS_FPU_EMU_INC_STATS(errors);
1585 *fault_addr = va;
1586 return SIGSEGV;
1587 }
1588 DITOREG(val, MIPSInst_FD(ir));
1589 break;
1590
1591 case sdxc1_op:
1592 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1593 xcp->regs[MIPSInst_FT(ir)]);
1594
1595 MIPS_FPU_EMU_INC_STATS(stores);
1596 DIFROMREG(val, MIPSInst_FS(ir));
1597 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1598 MIPS_FPU_EMU_INC_STATS(errors);
1599 *fault_addr = va;
1600 return SIGBUS;
1601 }
1602 if (__put_user(val, va)) {
1603 MIPS_FPU_EMU_INC_STATS(errors);
1604 *fault_addr = va;
1605 return SIGSEGV;
1606 }
1607 break;
1608
1609 case madd_d_op:
1610 handler = fpemu_dp_madd;
1611 goto dcoptop;
1612 case msub_d_op:
1613 handler = fpemu_dp_msub;
1614 goto dcoptop;
1615 case nmadd_d_op:
1616 handler = fpemu_dp_nmadd;
1617 goto dcoptop;
1618 case nmsub_d_op:
1619 handler = fpemu_dp_nmsub;
1620 goto dcoptop;
1621
1622 dcoptop:
1623 DPFROMREG(fr, MIPSInst_FR(ir));
1624 DPFROMREG(fs, MIPSInst_FS(ir));
1625 DPFROMREG(ft, MIPSInst_FT(ir));
1626 fd = (*handler) (fr, fs, ft);
1627 DPTOREG(fd, MIPSInst_FD(ir));
1628 goto copcsr;
1629
1630 default:
1631 return SIGILL;
1632 }
1633 break;
1634 }
1635
1636 case 0x3:
1637 if (MIPSInst_FUNC(ir) != pfetch_op)
1638 return SIGILL;
1639
1640 /* ignore prefx operation */
1641 break;
1642
1643 default:
1644 return SIGILL;
1645 }
1646
1647 return 0;
1648 }
1649
1650
1651
1652 /*
1653 * Emulate a single COP1 arithmetic instruction.
1654 */
1655 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1656 mips_instruction ir)
1657 {
1658 int rfmt; /* resulting format */
1659 unsigned rcsr = 0; /* resulting csr */
1660 unsigned int oldrm;
1661 unsigned int cbit;
1662 unsigned cond;
1663 union {
1664 union ieee754dp d;
1665 union ieee754sp s;
1666 int w;
1667 s64 l;
1668 } rv; /* resulting value */
1669 u64 bits;
1670
1671 MIPS_FPU_EMU_INC_STATS(cp1ops);
1672 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1673 case s_fmt: { /* 0 */
1674 union {
1675 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1676 union ieee754sp(*u) (union ieee754sp);
1677 } handler;
1678 union ieee754sp fs, ft;
1679
1680 switch (MIPSInst_FUNC(ir)) {
1681 /* binary ops */
1682 case fadd_op:
1683 handler.b = ieee754sp_add;
1684 goto scopbop;
1685 case fsub_op:
1686 handler.b = ieee754sp_sub;
1687 goto scopbop;
1688 case fmul_op:
1689 handler.b = ieee754sp_mul;
1690 goto scopbop;
1691 case fdiv_op:
1692 handler.b = ieee754sp_div;
1693 goto scopbop;
1694
1695 /* unary ops */
1696 case fsqrt_op:
1697 if (!cpu_has_mips_2_3_4_5_r)
1698 return SIGILL;
1699
1700 handler.u = ieee754sp_sqrt;
1701 goto scopuop;
1702
1703 /*
1704 * Note that on some MIPS IV implementations such as the
1705 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1706 * achieve full IEEE-754 accuracy - however this emulator does.
1707 */
1708 case frsqrt_op:
1709 if (!cpu_has_mips_4_5_64_r2_r6)
1710 return SIGILL;
1711
1712 handler.u = fpemu_sp_rsqrt;
1713 goto scopuop;
1714
1715 case frecip_op:
1716 if (!cpu_has_mips_4_5_64_r2_r6)
1717 return SIGILL;
1718
1719 handler.u = fpemu_sp_recip;
1720 goto scopuop;
1721
1722 case fmovc_op:
1723 if (!cpu_has_mips_4_5_r)
1724 return SIGILL;
1725
1726 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1727 if (((ctx->fcr31 & cond) != 0) !=
1728 ((MIPSInst_FT(ir) & 1) != 0))
1729 return 0;
1730 SPFROMREG(rv.s, MIPSInst_FS(ir));
1731 break;
1732
1733 case fmovz_op:
1734 if (!cpu_has_mips_4_5_r)
1735 return SIGILL;
1736
1737 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1738 return 0;
1739 SPFROMREG(rv.s, MIPSInst_FS(ir));
1740 break;
1741
1742 case fmovn_op:
1743 if (!cpu_has_mips_4_5_r)
1744 return SIGILL;
1745
1746 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1747 return 0;
1748 SPFROMREG(rv.s, MIPSInst_FS(ir));
1749 break;
1750
1751 case fseleqz_op:
1752 if (!cpu_has_mips_r6)
1753 return SIGILL;
1754
1755 SPFROMREG(rv.s, MIPSInst_FT(ir));
1756 if (rv.w & 0x1)
1757 rv.w = 0;
1758 else
1759 SPFROMREG(rv.s, MIPSInst_FS(ir));
1760 break;
1761
1762 case fselnez_op:
1763 if (!cpu_has_mips_r6)
1764 return SIGILL;
1765
1766 SPFROMREG(rv.s, MIPSInst_FT(ir));
1767 if (rv.w & 0x1)
1768 SPFROMREG(rv.s, MIPSInst_FS(ir));
1769 else
1770 rv.w = 0;
1771 break;
1772
1773 case fmaddf_op: {
1774 union ieee754sp ft, fs, fd;
1775
1776 if (!cpu_has_mips_r6)
1777 return SIGILL;
1778
1779 SPFROMREG(ft, MIPSInst_FT(ir));
1780 SPFROMREG(fs, MIPSInst_FS(ir));
1781 SPFROMREG(fd, MIPSInst_FD(ir));
1782 rv.s = ieee754sp_maddf(fd, fs, ft);
1783 break;
1784 }
1785
1786 case fmsubf_op: {
1787 union ieee754sp ft, fs, fd;
1788
1789 if (!cpu_has_mips_r6)
1790 return SIGILL;
1791
1792 SPFROMREG(ft, MIPSInst_FT(ir));
1793 SPFROMREG(fs, MIPSInst_FS(ir));
1794 SPFROMREG(fd, MIPSInst_FD(ir));
1795 rv.s = ieee754sp_msubf(fd, fs, ft);
1796 break;
1797 }
1798
1799 case frint_op: {
1800 union ieee754sp fs;
1801
1802 if (!cpu_has_mips_r6)
1803 return SIGILL;
1804
1805 SPFROMREG(fs, MIPSInst_FS(ir));
1806 rv.l = ieee754sp_tlong(fs);
1807 rv.s = ieee754sp_flong(rv.l);
1808 goto copcsr;
1809 }
1810
1811 case fclass_op: {
1812 union ieee754sp fs;
1813
1814 if (!cpu_has_mips_r6)
1815 return SIGILL;
1816
1817 SPFROMREG(fs, MIPSInst_FS(ir));
1818 rv.w = ieee754sp_2008class(fs);
1819 rfmt = w_fmt;
1820 break;
1821 }
1822
1823 case fmin_op: {
1824 union ieee754sp fs, ft;
1825
1826 if (!cpu_has_mips_r6)
1827 return SIGILL;
1828
1829 SPFROMREG(ft, MIPSInst_FT(ir));
1830 SPFROMREG(fs, MIPSInst_FS(ir));
1831 rv.s = ieee754sp_fmin(fs, ft);
1832 break;
1833 }
1834
1835 case fmina_op: {
1836 union ieee754sp fs, ft;
1837
1838 if (!cpu_has_mips_r6)
1839 return SIGILL;
1840
1841 SPFROMREG(ft, MIPSInst_FT(ir));
1842 SPFROMREG(fs, MIPSInst_FS(ir));
1843 rv.s = ieee754sp_fmina(fs, ft);
1844 break;
1845 }
1846
1847 case fmax_op: {
1848 union ieee754sp fs, ft;
1849
1850 if (!cpu_has_mips_r6)
1851 return SIGILL;
1852
1853 SPFROMREG(ft, MIPSInst_FT(ir));
1854 SPFROMREG(fs, MIPSInst_FS(ir));
1855 rv.s = ieee754sp_fmax(fs, ft);
1856 break;
1857 }
1858
1859 case fmaxa_op: {
1860 union ieee754sp fs, ft;
1861
1862 if (!cpu_has_mips_r6)
1863 return SIGILL;
1864
1865 SPFROMREG(ft, MIPSInst_FT(ir));
1866 SPFROMREG(fs, MIPSInst_FS(ir));
1867 rv.s = ieee754sp_fmaxa(fs, ft);
1868 break;
1869 }
1870
1871 case fabs_op:
1872 handler.u = ieee754sp_abs;
1873 goto scopuop;
1874
1875 case fneg_op:
1876 handler.u = ieee754sp_neg;
1877 goto scopuop;
1878
1879 case fmov_op:
1880 /* an easy one */
1881 SPFROMREG(rv.s, MIPSInst_FS(ir));
1882 goto copcsr;
1883
1884 /* binary op on handler */
1885 scopbop:
1886 SPFROMREG(fs, MIPSInst_FS(ir));
1887 SPFROMREG(ft, MIPSInst_FT(ir));
1888
1889 rv.s = (*handler.b) (fs, ft);
1890 goto copcsr;
1891 scopuop:
1892 SPFROMREG(fs, MIPSInst_FS(ir));
1893 rv.s = (*handler.u) (fs);
1894 goto copcsr;
1895 copcsr:
1896 if (ieee754_cxtest(IEEE754_INEXACT)) {
1897 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1898 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1899 }
1900 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1901 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1902 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1903 }
1904 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1905 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1906 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1907 }
1908 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1909 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1910 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1911 }
1912 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1913 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1914 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1915 }
1916 break;
1917
1918 /* unary conv ops */
1919 case fcvts_op:
1920 return SIGILL; /* not defined */
1921
1922 case fcvtd_op:
1923 SPFROMREG(fs, MIPSInst_FS(ir));
1924 rv.d = ieee754dp_fsp(fs);
1925 rfmt = d_fmt;
1926 goto copcsr;
1927
1928 case fcvtw_op:
1929 SPFROMREG(fs, MIPSInst_FS(ir));
1930 rv.w = ieee754sp_tint(fs);
1931 rfmt = w_fmt;
1932 goto copcsr;
1933
1934 case fround_op:
1935 case ftrunc_op:
1936 case fceil_op:
1937 case ffloor_op:
1938 if (!cpu_has_mips_2_3_4_5_r)
1939 return SIGILL;
1940
1941 oldrm = ieee754_csr.rm;
1942 SPFROMREG(fs, MIPSInst_FS(ir));
1943 ieee754_csr.rm = MIPSInst_FUNC(ir);
1944 rv.w = ieee754sp_tint(fs);
1945 ieee754_csr.rm = oldrm;
1946 rfmt = w_fmt;
1947 goto copcsr;
1948
1949 case fcvtl_op:
1950 if (!cpu_has_mips_3_4_5_64_r2_r6)
1951 return SIGILL;
1952
1953 SPFROMREG(fs, MIPSInst_FS(ir));
1954 rv.l = ieee754sp_tlong(fs);
1955 rfmt = l_fmt;
1956 goto copcsr;
1957
1958 case froundl_op:
1959 case ftruncl_op:
1960 case fceill_op:
1961 case ffloorl_op:
1962 if (!cpu_has_mips_3_4_5_64_r2_r6)
1963 return SIGILL;
1964
1965 oldrm = ieee754_csr.rm;
1966 SPFROMREG(fs, MIPSInst_FS(ir));
1967 ieee754_csr.rm = MIPSInst_FUNC(ir);
1968 rv.l = ieee754sp_tlong(fs);
1969 ieee754_csr.rm = oldrm;
1970 rfmt = l_fmt;
1971 goto copcsr;
1972
1973 default:
1974 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
1975 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1976 union ieee754sp fs, ft;
1977
1978 SPFROMREG(fs, MIPSInst_FS(ir));
1979 SPFROMREG(ft, MIPSInst_FT(ir));
1980 rv.w = ieee754sp_cmp(fs, ft,
1981 cmptab[cmpop & 0x7], cmpop & 0x8);
1982 rfmt = -1;
1983 if ((cmpop & 0x8) && ieee754_cxtest
1984 (IEEE754_INVALID_OPERATION))
1985 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1986 else
1987 goto copcsr;
1988
1989 } else
1990 return SIGILL;
1991 break;
1992 }
1993 break;
1994 }
1995
1996 case d_fmt: {
1997 union ieee754dp fs, ft;
1998 union {
1999 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
2000 union ieee754dp(*u) (union ieee754dp);
2001 } handler;
2002
2003 switch (MIPSInst_FUNC(ir)) {
2004 /* binary ops */
2005 case fadd_op:
2006 handler.b = ieee754dp_add;
2007 goto dcopbop;
2008 case fsub_op:
2009 handler.b = ieee754dp_sub;
2010 goto dcopbop;
2011 case fmul_op:
2012 handler.b = ieee754dp_mul;
2013 goto dcopbop;
2014 case fdiv_op:
2015 handler.b = ieee754dp_div;
2016 goto dcopbop;
2017
2018 /* unary ops */
2019 case fsqrt_op:
2020 if (!cpu_has_mips_2_3_4_5_r)
2021 return SIGILL;
2022
2023 handler.u = ieee754dp_sqrt;
2024 goto dcopuop;
2025 /*
2026 * Note that on some MIPS IV implementations such as the
2027 * R5000 and R8000 the FSQRT and FRECIP instructions do not
2028 * achieve full IEEE-754 accuracy - however this emulator does.
2029 */
2030 case frsqrt_op:
2031 if (!cpu_has_mips_4_5_64_r2_r6)
2032 return SIGILL;
2033
2034 handler.u = fpemu_dp_rsqrt;
2035 goto dcopuop;
2036 case frecip_op:
2037 if (!cpu_has_mips_4_5_64_r2_r6)
2038 return SIGILL;
2039
2040 handler.u = fpemu_dp_recip;
2041 goto dcopuop;
2042 case fmovc_op:
2043 if (!cpu_has_mips_4_5_r)
2044 return SIGILL;
2045
2046 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
2047 if (((ctx->fcr31 & cond) != 0) !=
2048 ((MIPSInst_FT(ir) & 1) != 0))
2049 return 0;
2050 DPFROMREG(rv.d, MIPSInst_FS(ir));
2051 break;
2052 case fmovz_op:
2053 if (!cpu_has_mips_4_5_r)
2054 return SIGILL;
2055
2056 if (xcp->regs[MIPSInst_FT(ir)] != 0)
2057 return 0;
2058 DPFROMREG(rv.d, MIPSInst_FS(ir));
2059 break;
2060 case fmovn_op:
2061 if (!cpu_has_mips_4_5_r)
2062 return SIGILL;
2063
2064 if (xcp->regs[MIPSInst_FT(ir)] == 0)
2065 return 0;
2066 DPFROMREG(rv.d, MIPSInst_FS(ir));
2067 break;
2068
2069 case fseleqz_op:
2070 if (!cpu_has_mips_r6)
2071 return SIGILL;
2072
2073 DPFROMREG(rv.d, MIPSInst_FT(ir));
2074 if (rv.l & 0x1)
2075 rv.l = 0;
2076 else
2077 DPFROMREG(rv.d, MIPSInst_FS(ir));
2078 break;
2079
2080 case fselnez_op:
2081 if (!cpu_has_mips_r6)
2082 return SIGILL;
2083
2084 DPFROMREG(rv.d, MIPSInst_FT(ir));
2085 if (rv.l & 0x1)
2086 DPFROMREG(rv.d, MIPSInst_FS(ir));
2087 else
2088 rv.l = 0;
2089 break;
2090
2091 case fmaddf_op: {
2092 union ieee754dp ft, fs, fd;
2093
2094 if (!cpu_has_mips_r6)
2095 return SIGILL;
2096
2097 DPFROMREG(ft, MIPSInst_FT(ir));
2098 DPFROMREG(fs, MIPSInst_FS(ir));
2099 DPFROMREG(fd, MIPSInst_FD(ir));
2100 rv.d = ieee754dp_maddf(fd, fs, ft);
2101 break;
2102 }
2103
2104 case fmsubf_op: {
2105 union ieee754dp ft, fs, fd;
2106
2107 if (!cpu_has_mips_r6)
2108 return SIGILL;
2109
2110 DPFROMREG(ft, MIPSInst_FT(ir));
2111 DPFROMREG(fs, MIPSInst_FS(ir));
2112 DPFROMREG(fd, MIPSInst_FD(ir));
2113 rv.d = ieee754dp_msubf(fd, fs, ft);
2114 break;
2115 }
2116
2117 case frint_op: {
2118 union ieee754dp fs;
2119
2120 if (!cpu_has_mips_r6)
2121 return SIGILL;
2122
2123 DPFROMREG(fs, MIPSInst_FS(ir));
2124 rv.l = ieee754dp_tlong(fs);
2125 rv.d = ieee754dp_flong(rv.l);
2126 goto copcsr;
2127 }
2128
2129 case fclass_op: {
2130 union ieee754dp fs;
2131
2132 if (!cpu_has_mips_r6)
2133 return SIGILL;
2134
2135 DPFROMREG(fs, MIPSInst_FS(ir));
2136 rv.w = ieee754dp_2008class(fs);
2137 rfmt = w_fmt;
2138 break;
2139 }
2140
2141 case fmin_op: {
2142 union ieee754dp fs, ft;
2143
2144 if (!cpu_has_mips_r6)
2145 return SIGILL;
2146
2147 DPFROMREG(ft, MIPSInst_FT(ir));
2148 DPFROMREG(fs, MIPSInst_FS(ir));
2149 rv.d = ieee754dp_fmin(fs, ft);
2150 break;
2151 }
2152
2153 case fmina_op: {
2154 union ieee754dp fs, ft;
2155
2156 if (!cpu_has_mips_r6)
2157 return SIGILL;
2158
2159 DPFROMREG(ft, MIPSInst_FT(ir));
2160 DPFROMREG(fs, MIPSInst_FS(ir));
2161 rv.d = ieee754dp_fmina(fs, ft);
2162 break;
2163 }
2164
2165 case fmax_op: {
2166 union ieee754dp fs, ft;
2167
2168 if (!cpu_has_mips_r6)
2169 return SIGILL;
2170
2171 DPFROMREG(ft, MIPSInst_FT(ir));
2172 DPFROMREG(fs, MIPSInst_FS(ir));
2173 rv.d = ieee754dp_fmax(fs, ft);
2174 break;
2175 }
2176
2177 case fmaxa_op: {
2178 union ieee754dp fs, ft;
2179
2180 if (!cpu_has_mips_r6)
2181 return SIGILL;
2182
2183 DPFROMREG(ft, MIPSInst_FT(ir));
2184 DPFROMREG(fs, MIPSInst_FS(ir));
2185 rv.d = ieee754dp_fmaxa(fs, ft);
2186 break;
2187 }
2188
2189 case fabs_op:
2190 handler.u = ieee754dp_abs;
2191 goto dcopuop;
2192
2193 case fneg_op:
2194 handler.u = ieee754dp_neg;
2195 goto dcopuop;
2196
2197 case fmov_op:
2198 /* an easy one */
2199 DPFROMREG(rv.d, MIPSInst_FS(ir));
2200 goto copcsr;
2201
2202 /* binary op on handler */
2203 dcopbop:
2204 DPFROMREG(fs, MIPSInst_FS(ir));
2205 DPFROMREG(ft, MIPSInst_FT(ir));
2206
2207 rv.d = (*handler.b) (fs, ft);
2208 goto copcsr;
2209 dcopuop:
2210 DPFROMREG(fs, MIPSInst_FS(ir));
2211 rv.d = (*handler.u) (fs);
2212 goto copcsr;
2213
2214 /*
2215 * unary conv ops
2216 */
2217 case fcvts_op:
2218 DPFROMREG(fs, MIPSInst_FS(ir));
2219 rv.s = ieee754sp_fdp(fs);
2220 rfmt = s_fmt;
2221 goto copcsr;
2222
2223 case fcvtd_op:
2224 return SIGILL; /* not defined */
2225
2226 case fcvtw_op:
2227 DPFROMREG(fs, MIPSInst_FS(ir));
2228 rv.w = ieee754dp_tint(fs); /* wrong */
2229 rfmt = w_fmt;
2230 goto copcsr;
2231
2232 case fround_op:
2233 case ftrunc_op:
2234 case fceil_op:
2235 case ffloor_op:
2236 if (!cpu_has_mips_2_3_4_5_r)
2237 return SIGILL;
2238
2239 oldrm = ieee754_csr.rm;
2240 DPFROMREG(fs, MIPSInst_FS(ir));
2241 ieee754_csr.rm = MIPSInst_FUNC(ir);
2242 rv.w = ieee754dp_tint(fs);
2243 ieee754_csr.rm = oldrm;
2244 rfmt = w_fmt;
2245 goto copcsr;
2246
2247 case fcvtl_op:
2248 if (!cpu_has_mips_3_4_5_64_r2_r6)
2249 return SIGILL;
2250
2251 DPFROMREG(fs, MIPSInst_FS(ir));
2252 rv.l = ieee754dp_tlong(fs);
2253 rfmt = l_fmt;
2254 goto copcsr;
2255
2256 case froundl_op:
2257 case ftruncl_op:
2258 case fceill_op:
2259 case ffloorl_op:
2260 if (!cpu_has_mips_3_4_5_64_r2_r6)
2261 return SIGILL;
2262
2263 oldrm = ieee754_csr.rm;
2264 DPFROMREG(fs, MIPSInst_FS(ir));
2265 ieee754_csr.rm = MIPSInst_FUNC(ir);
2266 rv.l = ieee754dp_tlong(fs);
2267 ieee754_csr.rm = oldrm;
2268 rfmt = l_fmt;
2269 goto copcsr;
2270
2271 default:
2272 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
2273 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2274 union ieee754dp fs, ft;
2275
2276 DPFROMREG(fs, MIPSInst_FS(ir));
2277 DPFROMREG(ft, MIPSInst_FT(ir));
2278 rv.w = ieee754dp_cmp(fs, ft,
2279 cmptab[cmpop & 0x7], cmpop & 0x8);
2280 rfmt = -1;
2281 if ((cmpop & 0x8)
2282 &&
2283 ieee754_cxtest
2284 (IEEE754_INVALID_OPERATION))
2285 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2286 else
2287 goto copcsr;
2288
2289 }
2290 else {
2291 return SIGILL;
2292 }
2293 break;
2294 }
2295 break;
2296 }
2297
2298 case w_fmt: {
2299 union ieee754dp fs;
2300
2301 switch (MIPSInst_FUNC(ir)) {
2302 case fcvts_op:
2303 /* convert word to single precision real */
2304 SPFROMREG(fs, MIPSInst_FS(ir));
2305 rv.s = ieee754sp_fint(fs.bits);
2306 rfmt = s_fmt;
2307 goto copcsr;
2308 case fcvtd_op:
2309 /* convert word to double precision real */
2310 SPFROMREG(fs, MIPSInst_FS(ir));
2311 rv.d = ieee754dp_fint(fs.bits);
2312 rfmt = d_fmt;
2313 goto copcsr;
2314 default: {
2315 /* Emulating the new CMP.condn.fmt R6 instruction */
2316 #define CMPOP_MASK 0x7
2317 #define SIGN_BIT (0x1 << 3)
2318 #define PREDICATE_BIT (0x1 << 4)
2319
2320 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2321 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2322 union ieee754sp fs, ft;
2323
2324 /* This is an R6 only instruction */
2325 if (!cpu_has_mips_r6 ||
2326 (MIPSInst_FUNC(ir) & 0x20))
2327 return SIGILL;
2328
2329 /* fmt is w_fmt for single precision so fix it */
2330 rfmt = s_fmt;
2331 /* default to false */
2332 rv.w = 0;
2333
2334 /* CMP.condn.S */
2335 SPFROMREG(fs, MIPSInst_FS(ir));
2336 SPFROMREG(ft, MIPSInst_FT(ir));
2337
2338 /* positive predicates */
2339 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2340 if (ieee754sp_cmp(fs, ft, cmptab[cmpop],
2341 sig))
2342 rv.w = -1; /* true, all 1s */
2343 if ((sig) &&
2344 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2345 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2346 else
2347 goto copcsr;
2348 } else {
2349 /* negative predicates */
2350 switch (cmpop) {
2351 case 1:
2352 case 2:
2353 case 3:
2354 if (ieee754sp_cmp(fs, ft,
2355 negative_cmptab[cmpop],
2356 sig))
2357 rv.w = -1; /* true, all 1s */
2358 if (sig &&
2359 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2360 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2361 else
2362 goto copcsr;
2363 break;
2364 default:
2365 /* Reserved R6 ops */
2366 pr_err("Reserved MIPS R6 CMP.condn.S operation\n");
2367 return SIGILL;
2368 }
2369 }
2370 break;
2371 }
2372 }
2373 }
2374
2375 case l_fmt:
2376
2377 if (!cpu_has_mips_3_4_5_64_r2_r6)
2378 return SIGILL;
2379
2380 DIFROMREG(bits, MIPSInst_FS(ir));
2381
2382 switch (MIPSInst_FUNC(ir)) {
2383 case fcvts_op:
2384 /* convert long to single precision real */
2385 rv.s = ieee754sp_flong(bits);
2386 rfmt = s_fmt;
2387 goto copcsr;
2388 case fcvtd_op:
2389 /* convert long to double precision real */
2390 rv.d = ieee754dp_flong(bits);
2391 rfmt = d_fmt;
2392 goto copcsr;
2393 default: {
2394 /* Emulating the new CMP.condn.fmt R6 instruction */
2395 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2396 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2397 union ieee754dp fs, ft;
2398
2399 if (!cpu_has_mips_r6 ||
2400 (MIPSInst_FUNC(ir) & 0x20))
2401 return SIGILL;
2402
2403 /* fmt is l_fmt for double precision so fix it */
2404 rfmt = d_fmt;
2405 /* default to false */
2406 rv.l = 0;
2407
2408 /* CMP.condn.D */
2409 DPFROMREG(fs, MIPSInst_FS(ir));
2410 DPFROMREG(ft, MIPSInst_FT(ir));
2411
2412 /* positive predicates */
2413 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2414 if (ieee754dp_cmp(fs, ft,
2415 cmptab[cmpop], sig))
2416 rv.l = -1LL; /* true, all 1s */
2417 if (sig &&
2418 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2419 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2420 else
2421 goto copcsr;
2422 } else {
2423 /* negative predicates */
2424 switch (cmpop) {
2425 case 1:
2426 case 2:
2427 case 3:
2428 if (ieee754dp_cmp(fs, ft,
2429 negative_cmptab[cmpop],
2430 sig))
2431 rv.l = -1LL; /* true, all 1s */
2432 if (sig &&
2433 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2434 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2435 else
2436 goto copcsr;
2437 break;
2438 default:
2439 /* Reserved R6 ops */
2440 pr_err("Reserved MIPS R6 CMP.condn.D operation\n");
2441 return SIGILL;
2442 }
2443 }
2444 break;
2445 }
2446 }
2447 default:
2448 return SIGILL;
2449 }
2450
2451 /*
2452 * Update the fpu CSR register for this operation.
2453 * If an exception is required, generate a tidy SIGFPE exception,
2454 * without updating the result register.
2455 * Note: cause exception bits do not accumulate, they are rewritten
2456 * for each op; only the flag/sticky bits accumulate.
2457 */
2458 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2459 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
2460 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
2461 return SIGFPE;
2462 }
2463
2464 /*
2465 * Now we can safely write the result back to the register file.
2466 */
2467 switch (rfmt) {
2468 case -1:
2469
2470 if (cpu_has_mips_4_5_r)
2471 cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
2472 else
2473 cbit = FPU_CSR_COND;
2474 if (rv.w)
2475 ctx->fcr31 |= cbit;
2476 else
2477 ctx->fcr31 &= ~cbit;
2478 break;
2479
2480 case d_fmt:
2481 DPTOREG(rv.d, MIPSInst_FD(ir));
2482 break;
2483 case s_fmt:
2484 SPTOREG(rv.s, MIPSInst_FD(ir));
2485 break;
2486 case w_fmt:
2487 SITOREG(rv.w, MIPSInst_FD(ir));
2488 break;
2489 case l_fmt:
2490 if (!cpu_has_mips_3_4_5_64_r2_r6)
2491 return SIGILL;
2492
2493 DITOREG(rv.l, MIPSInst_FD(ir));
2494 break;
2495 default:
2496 return SIGILL;
2497 }
2498
2499 return 0;
2500 }
2501
2502 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2503 int has_fpu, void *__user *fault_addr)
2504 {
2505 unsigned long oldepc, prevepc;
2506 struct mm_decoded_insn dec_insn;
2507 u16 instr[4];
2508 u16 *instr_ptr;
2509 int sig = 0;
2510
2511 oldepc = xcp->cp0_epc;
2512 do {
2513 prevepc = xcp->cp0_epc;
2514
2515 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2516 /*
2517 * Get next 2 microMIPS instructions and convert them
2518 * into 32-bit instructions.
2519 */
2520 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2521 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2522 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2523 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2524 MIPS_FPU_EMU_INC_STATS(errors);
2525 return SIGBUS;
2526 }
2527 instr_ptr = instr;
2528
2529 /* Get first instruction. */
2530 if (mm_insn_16bit(*instr_ptr)) {
2531 /* Duplicate the half-word. */
2532 dec_insn.insn = (*instr_ptr << 16) |
2533 (*instr_ptr);
2534 /* 16-bit instruction. */
2535 dec_insn.pc_inc = 2;
2536 instr_ptr += 1;
2537 } else {
2538 dec_insn.insn = (*instr_ptr << 16) |
2539 *(instr_ptr+1);
2540 /* 32-bit instruction. */
2541 dec_insn.pc_inc = 4;
2542 instr_ptr += 2;
2543 }
2544 /* Get second instruction. */
2545 if (mm_insn_16bit(*instr_ptr)) {
2546 /* Duplicate the half-word. */
2547 dec_insn.next_insn = (*instr_ptr << 16) |
2548 (*instr_ptr);
2549 /* 16-bit instruction. */
2550 dec_insn.next_pc_inc = 2;
2551 } else {
2552 dec_insn.next_insn = (*instr_ptr << 16) |
2553 *(instr_ptr+1);
2554 /* 32-bit instruction. */
2555 dec_insn.next_pc_inc = 4;
2556 }
2557 dec_insn.micro_mips_mode = 1;
2558 } else {
2559 if ((get_user(dec_insn.insn,
2560 (mips_instruction __user *) xcp->cp0_epc)) ||
2561 (get_user(dec_insn.next_insn,
2562 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2563 MIPS_FPU_EMU_INC_STATS(errors);
2564 return SIGBUS;
2565 }
2566 dec_insn.pc_inc = 4;
2567 dec_insn.next_pc_inc = 4;
2568 dec_insn.micro_mips_mode = 0;
2569 }
2570
2571 if ((dec_insn.insn == 0) ||
2572 ((dec_insn.pc_inc == 2) &&
2573 ((dec_insn.insn & 0xffff) == MM_NOP16)))
2574 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
2575 else {
2576 /*
2577 * The 'ieee754_csr' is an alias of ctx->fcr31.
2578 * No need to copy ctx->fcr31 to ieee754_csr.
2579 */
2580 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2581 }
2582
2583 if (has_fpu)
2584 break;
2585 if (sig)
2586 break;
2587
2588 cond_resched();
2589 } while (xcp->cp0_epc > prevepc);
2590
2591 /* SIGILL indicates a non-fpu instruction */
2592 if (sig == SIGILL && xcp->cp0_epc != oldepc)
2593 /* but if EPC has advanced, then ignore it */
2594 sig = 0;
2595
2596 return sig;
2597 }
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