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MIPS: Emulate the BC1{EQ,NE}Z FPU instructions
[mirror_ubuntu-hirsute-kernel.git] / arch / mips / math-emu / cp1emu.c
1 /*
2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
22 *
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
26 *
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware FPU at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
32 *
33 * Note if you know that you won't have an FPU, then you'll get much
34 * better performance by compiling with -msoft-float!
35 */
36 #include <linux/sched.h>
37 #include <linux/debugfs.h>
38 #include <linux/kconfig.h>
39 #include <linux/percpu-defs.h>
40 #include <linux/perf_event.h>
41
42 #include <asm/branch.h>
43 #include <asm/inst.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/uaccess.h>
47
48 #include <asm/processor.h>
49 #include <asm/fpu_emulator.h>
50 #include <asm/fpu.h>
51
52 #include "ieee754.h"
53
54 /* Function which emulates a floating point instruction. */
55
56 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
57 mips_instruction);
58
59 static int fpux_emu(struct pt_regs *,
60 struct mips_fpu_struct *, mips_instruction, void *__user *);
61
62 /* Control registers */
63
64 #define FPCREG_RID 0 /* $0 = revision id */
65 #define FPCREG_CSR 31 /* $31 = csr */
66
67 /* Determine rounding mode from the RM bits of the FCSR */
68 #define modeindex(v) ((v) & FPU_CSR_RM)
69
70 /* convert condition code register number to csr bit */
71 static const unsigned int fpucondbit[8] = {
72 FPU_CSR_COND0,
73 FPU_CSR_COND1,
74 FPU_CSR_COND2,
75 FPU_CSR_COND3,
76 FPU_CSR_COND4,
77 FPU_CSR_COND5,
78 FPU_CSR_COND6,
79 FPU_CSR_COND7
80 };
81
82 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
83 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
84 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
85 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
86 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
87
88 /*
89 * This functions translates a 32-bit microMIPS instruction
90 * into a 32-bit MIPS32 instruction. Returns 0 on success
91 * and SIGILL otherwise.
92 */
93 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
94 {
95 union mips_instruction insn = *insn_ptr;
96 union mips_instruction mips32_insn = insn;
97 int func, fmt, op;
98
99 switch (insn.mm_i_format.opcode) {
100 case mm_ldc132_op:
101 mips32_insn.mm_i_format.opcode = ldc1_op;
102 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
103 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
104 break;
105 case mm_lwc132_op:
106 mips32_insn.mm_i_format.opcode = lwc1_op;
107 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
108 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
109 break;
110 case mm_sdc132_op:
111 mips32_insn.mm_i_format.opcode = sdc1_op;
112 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
113 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
114 break;
115 case mm_swc132_op:
116 mips32_insn.mm_i_format.opcode = swc1_op;
117 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
118 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
119 break;
120 case mm_pool32i_op:
121 /* NOTE: offset is << by 1 if in microMIPS mode. */
122 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
123 (insn.mm_i_format.rt == mm_bc1t_op)) {
124 mips32_insn.fb_format.opcode = cop1_op;
125 mips32_insn.fb_format.bc = bc_op;
126 mips32_insn.fb_format.flag =
127 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
128 } else
129 return SIGILL;
130 break;
131 case mm_pool32f_op:
132 switch (insn.mm_fp0_format.func) {
133 case mm_32f_01_op:
134 case mm_32f_11_op:
135 case mm_32f_02_op:
136 case mm_32f_12_op:
137 case mm_32f_41_op:
138 case mm_32f_51_op:
139 case mm_32f_42_op:
140 case mm_32f_52_op:
141 op = insn.mm_fp0_format.func;
142 if (op == mm_32f_01_op)
143 func = madd_s_op;
144 else if (op == mm_32f_11_op)
145 func = madd_d_op;
146 else if (op == mm_32f_02_op)
147 func = nmadd_s_op;
148 else if (op == mm_32f_12_op)
149 func = nmadd_d_op;
150 else if (op == mm_32f_41_op)
151 func = msub_s_op;
152 else if (op == mm_32f_51_op)
153 func = msub_d_op;
154 else if (op == mm_32f_42_op)
155 func = nmsub_s_op;
156 else
157 func = nmsub_d_op;
158 mips32_insn.fp6_format.opcode = cop1x_op;
159 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
160 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
161 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
162 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
163 mips32_insn.fp6_format.func = func;
164 break;
165 case mm_32f_10_op:
166 func = -1; /* Invalid */
167 op = insn.mm_fp5_format.op & 0x7;
168 if (op == mm_ldxc1_op)
169 func = ldxc1_op;
170 else if (op == mm_sdxc1_op)
171 func = sdxc1_op;
172 else if (op == mm_lwxc1_op)
173 func = lwxc1_op;
174 else if (op == mm_swxc1_op)
175 func = swxc1_op;
176
177 if (func != -1) {
178 mips32_insn.r_format.opcode = cop1x_op;
179 mips32_insn.r_format.rs =
180 insn.mm_fp5_format.base;
181 mips32_insn.r_format.rt =
182 insn.mm_fp5_format.index;
183 mips32_insn.r_format.rd = 0;
184 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
185 mips32_insn.r_format.func = func;
186 } else
187 return SIGILL;
188 break;
189 case mm_32f_40_op:
190 op = -1; /* Invalid */
191 if (insn.mm_fp2_format.op == mm_fmovt_op)
192 op = 1;
193 else if (insn.mm_fp2_format.op == mm_fmovf_op)
194 op = 0;
195 if (op != -1) {
196 mips32_insn.fp0_format.opcode = cop1_op;
197 mips32_insn.fp0_format.fmt =
198 sdps_format[insn.mm_fp2_format.fmt];
199 mips32_insn.fp0_format.ft =
200 (insn.mm_fp2_format.cc<<2) + op;
201 mips32_insn.fp0_format.fs =
202 insn.mm_fp2_format.fs;
203 mips32_insn.fp0_format.fd =
204 insn.mm_fp2_format.fd;
205 mips32_insn.fp0_format.func = fmovc_op;
206 } else
207 return SIGILL;
208 break;
209 case mm_32f_60_op:
210 func = -1; /* Invalid */
211 if (insn.mm_fp0_format.op == mm_fadd_op)
212 func = fadd_op;
213 else if (insn.mm_fp0_format.op == mm_fsub_op)
214 func = fsub_op;
215 else if (insn.mm_fp0_format.op == mm_fmul_op)
216 func = fmul_op;
217 else if (insn.mm_fp0_format.op == mm_fdiv_op)
218 func = fdiv_op;
219 if (func != -1) {
220 mips32_insn.fp0_format.opcode = cop1_op;
221 mips32_insn.fp0_format.fmt =
222 sdps_format[insn.mm_fp0_format.fmt];
223 mips32_insn.fp0_format.ft =
224 insn.mm_fp0_format.ft;
225 mips32_insn.fp0_format.fs =
226 insn.mm_fp0_format.fs;
227 mips32_insn.fp0_format.fd =
228 insn.mm_fp0_format.fd;
229 mips32_insn.fp0_format.func = func;
230 } else
231 return SIGILL;
232 break;
233 case mm_32f_70_op:
234 func = -1; /* Invalid */
235 if (insn.mm_fp0_format.op == mm_fmovn_op)
236 func = fmovn_op;
237 else if (insn.mm_fp0_format.op == mm_fmovz_op)
238 func = fmovz_op;
239 if (func != -1) {
240 mips32_insn.fp0_format.opcode = cop1_op;
241 mips32_insn.fp0_format.fmt =
242 sdps_format[insn.mm_fp0_format.fmt];
243 mips32_insn.fp0_format.ft =
244 insn.mm_fp0_format.ft;
245 mips32_insn.fp0_format.fs =
246 insn.mm_fp0_format.fs;
247 mips32_insn.fp0_format.fd =
248 insn.mm_fp0_format.fd;
249 mips32_insn.fp0_format.func = func;
250 } else
251 return SIGILL;
252 break;
253 case mm_32f_73_op: /* POOL32FXF */
254 switch (insn.mm_fp1_format.op) {
255 case mm_movf0_op:
256 case mm_movf1_op:
257 case mm_movt0_op:
258 case mm_movt1_op:
259 if ((insn.mm_fp1_format.op & 0x7f) ==
260 mm_movf0_op)
261 op = 0;
262 else
263 op = 1;
264 mips32_insn.r_format.opcode = spec_op;
265 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
266 mips32_insn.r_format.rt =
267 (insn.mm_fp4_format.cc << 2) + op;
268 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
269 mips32_insn.r_format.re = 0;
270 mips32_insn.r_format.func = movc_op;
271 break;
272 case mm_fcvtd0_op:
273 case mm_fcvtd1_op:
274 case mm_fcvts0_op:
275 case mm_fcvts1_op:
276 if ((insn.mm_fp1_format.op & 0x7f) ==
277 mm_fcvtd0_op) {
278 func = fcvtd_op;
279 fmt = swl_format[insn.mm_fp3_format.fmt];
280 } else {
281 func = fcvts_op;
282 fmt = dwl_format[insn.mm_fp3_format.fmt];
283 }
284 mips32_insn.fp0_format.opcode = cop1_op;
285 mips32_insn.fp0_format.fmt = fmt;
286 mips32_insn.fp0_format.ft = 0;
287 mips32_insn.fp0_format.fs =
288 insn.mm_fp3_format.fs;
289 mips32_insn.fp0_format.fd =
290 insn.mm_fp3_format.rt;
291 mips32_insn.fp0_format.func = func;
292 break;
293 case mm_fmov0_op:
294 case mm_fmov1_op:
295 case mm_fabs0_op:
296 case mm_fabs1_op:
297 case mm_fneg0_op:
298 case mm_fneg1_op:
299 if ((insn.mm_fp1_format.op & 0x7f) ==
300 mm_fmov0_op)
301 func = fmov_op;
302 else if ((insn.mm_fp1_format.op & 0x7f) ==
303 mm_fabs0_op)
304 func = fabs_op;
305 else
306 func = fneg_op;
307 mips32_insn.fp0_format.opcode = cop1_op;
308 mips32_insn.fp0_format.fmt =
309 sdps_format[insn.mm_fp3_format.fmt];
310 mips32_insn.fp0_format.ft = 0;
311 mips32_insn.fp0_format.fs =
312 insn.mm_fp3_format.fs;
313 mips32_insn.fp0_format.fd =
314 insn.mm_fp3_format.rt;
315 mips32_insn.fp0_format.func = func;
316 break;
317 case mm_ffloorl_op:
318 case mm_ffloorw_op:
319 case mm_fceill_op:
320 case mm_fceilw_op:
321 case mm_ftruncl_op:
322 case mm_ftruncw_op:
323 case mm_froundl_op:
324 case mm_froundw_op:
325 case mm_fcvtl_op:
326 case mm_fcvtw_op:
327 if (insn.mm_fp1_format.op == mm_ffloorl_op)
328 func = ffloorl_op;
329 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
330 func = ffloor_op;
331 else if (insn.mm_fp1_format.op == mm_fceill_op)
332 func = fceill_op;
333 else if (insn.mm_fp1_format.op == mm_fceilw_op)
334 func = fceil_op;
335 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
336 func = ftruncl_op;
337 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
338 func = ftrunc_op;
339 else if (insn.mm_fp1_format.op == mm_froundl_op)
340 func = froundl_op;
341 else if (insn.mm_fp1_format.op == mm_froundw_op)
342 func = fround_op;
343 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
344 func = fcvtl_op;
345 else
346 func = fcvtw_op;
347 mips32_insn.fp0_format.opcode = cop1_op;
348 mips32_insn.fp0_format.fmt =
349 sd_format[insn.mm_fp1_format.fmt];
350 mips32_insn.fp0_format.ft = 0;
351 mips32_insn.fp0_format.fs =
352 insn.mm_fp1_format.fs;
353 mips32_insn.fp0_format.fd =
354 insn.mm_fp1_format.rt;
355 mips32_insn.fp0_format.func = func;
356 break;
357 case mm_frsqrt_op:
358 case mm_fsqrt_op:
359 case mm_frecip_op:
360 if (insn.mm_fp1_format.op == mm_frsqrt_op)
361 func = frsqrt_op;
362 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
363 func = fsqrt_op;
364 else
365 func = frecip_op;
366 mips32_insn.fp0_format.opcode = cop1_op;
367 mips32_insn.fp0_format.fmt =
368 sdps_format[insn.mm_fp1_format.fmt];
369 mips32_insn.fp0_format.ft = 0;
370 mips32_insn.fp0_format.fs =
371 insn.mm_fp1_format.fs;
372 mips32_insn.fp0_format.fd =
373 insn.mm_fp1_format.rt;
374 mips32_insn.fp0_format.func = func;
375 break;
376 case mm_mfc1_op:
377 case mm_mtc1_op:
378 case mm_cfc1_op:
379 case mm_ctc1_op:
380 case mm_mfhc1_op:
381 case mm_mthc1_op:
382 if (insn.mm_fp1_format.op == mm_mfc1_op)
383 op = mfc_op;
384 else if (insn.mm_fp1_format.op == mm_mtc1_op)
385 op = mtc_op;
386 else if (insn.mm_fp1_format.op == mm_cfc1_op)
387 op = cfc_op;
388 else if (insn.mm_fp1_format.op == mm_ctc1_op)
389 op = ctc_op;
390 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
391 op = mfhc_op;
392 else
393 op = mthc_op;
394 mips32_insn.fp1_format.opcode = cop1_op;
395 mips32_insn.fp1_format.op = op;
396 mips32_insn.fp1_format.rt =
397 insn.mm_fp1_format.rt;
398 mips32_insn.fp1_format.fs =
399 insn.mm_fp1_format.fs;
400 mips32_insn.fp1_format.fd = 0;
401 mips32_insn.fp1_format.func = 0;
402 break;
403 default:
404 return SIGILL;
405 }
406 break;
407 case mm_32f_74_op: /* c.cond.fmt */
408 mips32_insn.fp0_format.opcode = cop1_op;
409 mips32_insn.fp0_format.fmt =
410 sdps_format[insn.mm_fp4_format.fmt];
411 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
412 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
413 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
414 mips32_insn.fp0_format.func =
415 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
416 break;
417 default:
418 return SIGILL;
419 }
420 break;
421 default:
422 return SIGILL;
423 }
424
425 *insn_ptr = mips32_insn;
426 return 0;
427 }
428
429 /*
430 * Redundant with logic already in kernel/branch.c,
431 * embedded in compute_return_epc. At some point,
432 * a single subroutine should be used across both
433 * modules.
434 */
435 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
436 unsigned long *contpc)
437 {
438 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
439 unsigned int fcr31;
440 unsigned int bit = 0;
441
442 switch (insn.i_format.opcode) {
443 case spec_op:
444 switch (insn.r_format.func) {
445 case jalr_op:
446 regs->regs[insn.r_format.rd] =
447 regs->cp0_epc + dec_insn.pc_inc +
448 dec_insn.next_pc_inc;
449 /* Fall through */
450 case jr_op:
451 /* For R6, JR already emulated in jalr_op */
452 if (NO_R6EMU && insn.r_format.opcode == jr_op)
453 break;
454 *contpc = regs->regs[insn.r_format.rs];
455 return 1;
456 }
457 break;
458 case bcond_op:
459 switch (insn.i_format.rt) {
460 case bltzal_op:
461 case bltzall_op:
462 if (NO_R6EMU && (insn.i_format.rs ||
463 insn.i_format.rt == bltzall_op))
464 break;
465
466 regs->regs[31] = regs->cp0_epc +
467 dec_insn.pc_inc +
468 dec_insn.next_pc_inc;
469 /* Fall through */
470 case bltzl_op:
471 if (NO_R6EMU)
472 break;
473 case bltz_op:
474 if ((long)regs->regs[insn.i_format.rs] < 0)
475 *contpc = regs->cp0_epc +
476 dec_insn.pc_inc +
477 (insn.i_format.simmediate << 2);
478 else
479 *contpc = regs->cp0_epc +
480 dec_insn.pc_inc +
481 dec_insn.next_pc_inc;
482 return 1;
483 case bgezal_op:
484 case bgezall_op:
485 if (NO_R6EMU && (insn.i_format.rs ||
486 insn.i_format.rt == bgezall_op))
487 break;
488
489 regs->regs[31] = regs->cp0_epc +
490 dec_insn.pc_inc +
491 dec_insn.next_pc_inc;
492 /* Fall through */
493 case bgezl_op:
494 if (NO_R6EMU)
495 break;
496 case bgez_op:
497 if ((long)regs->regs[insn.i_format.rs] >= 0)
498 *contpc = regs->cp0_epc +
499 dec_insn.pc_inc +
500 (insn.i_format.simmediate << 2);
501 else
502 *contpc = regs->cp0_epc +
503 dec_insn.pc_inc +
504 dec_insn.next_pc_inc;
505 return 1;
506 }
507 break;
508 case jalx_op:
509 set_isa16_mode(bit);
510 case jal_op:
511 regs->regs[31] = regs->cp0_epc +
512 dec_insn.pc_inc +
513 dec_insn.next_pc_inc;
514 /* Fall through */
515 case j_op:
516 *contpc = regs->cp0_epc + dec_insn.pc_inc;
517 *contpc >>= 28;
518 *contpc <<= 28;
519 *contpc |= (insn.j_format.target << 2);
520 /* Set microMIPS mode bit: XOR for jalx. */
521 *contpc ^= bit;
522 return 1;
523 case beql_op:
524 if (NO_R6EMU)
525 break;
526 case beq_op:
527 if (regs->regs[insn.i_format.rs] ==
528 regs->regs[insn.i_format.rt])
529 *contpc = regs->cp0_epc +
530 dec_insn.pc_inc +
531 (insn.i_format.simmediate << 2);
532 else
533 *contpc = regs->cp0_epc +
534 dec_insn.pc_inc +
535 dec_insn.next_pc_inc;
536 return 1;
537 case bnel_op:
538 if (NO_R6EMU)
539 break;
540 case bne_op:
541 if (regs->regs[insn.i_format.rs] !=
542 regs->regs[insn.i_format.rt])
543 *contpc = regs->cp0_epc +
544 dec_insn.pc_inc +
545 (insn.i_format.simmediate << 2);
546 else
547 *contpc = regs->cp0_epc +
548 dec_insn.pc_inc +
549 dec_insn.next_pc_inc;
550 return 1;
551 case blezl_op:
552 if (NO_R6EMU)
553 break;
554 case blez_op:
555 if ((long)regs->regs[insn.i_format.rs] <= 0)
556 *contpc = regs->cp0_epc +
557 dec_insn.pc_inc +
558 (insn.i_format.simmediate << 2);
559 else
560 *contpc = regs->cp0_epc +
561 dec_insn.pc_inc +
562 dec_insn.next_pc_inc;
563 return 1;
564 case bgtzl_op:
565 if (NO_R6EMU)
566 break;
567 case bgtz_op:
568 if ((long)regs->regs[insn.i_format.rs] > 0)
569 *contpc = regs->cp0_epc +
570 dec_insn.pc_inc +
571 (insn.i_format.simmediate << 2);
572 else
573 *contpc = regs->cp0_epc +
574 dec_insn.pc_inc +
575 dec_insn.next_pc_inc;
576 return 1;
577 #ifdef CONFIG_CPU_CAVIUM_OCTEON
578 case lwc2_op: /* This is bbit0 on Octeon */
579 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
580 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
581 else
582 *contpc = regs->cp0_epc + 8;
583 return 1;
584 case ldc2_op: /* This is bbit032 on Octeon */
585 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
586 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
587 else
588 *contpc = regs->cp0_epc + 8;
589 return 1;
590 case swc2_op: /* This is bbit1 on Octeon */
591 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
592 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
593 else
594 *contpc = regs->cp0_epc + 8;
595 return 1;
596 case sdc2_op: /* This is bbit132 on Octeon */
597 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
598 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
599 else
600 *contpc = regs->cp0_epc + 8;
601 return 1;
602 #endif
603 case cop0_op:
604 case cop1_op:
605 /* Need to check for R6 bc1nez and bc1eqz branches */
606 if (cpu_has_mips_r6 &&
607 ((insn.i_format.rs == bc1eqz_op) ||
608 (insn.i_format.rs == bc1nez_op))) {
609 bit = 0;
610 switch (insn.i_format.rs) {
611 case bc1eqz_op:
612 if (get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)
613 bit = 1;
614 break;
615 case bc1nez_op:
616 if (!(get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1))
617 bit = 1;
618 break;
619 }
620 if (bit)
621 *contpc = regs->cp0_epc +
622 dec_insn.pc_inc +
623 (insn.i_format.simmediate << 2);
624 else
625 *contpc = regs->cp0_epc +
626 dec_insn.pc_inc +
627 dec_insn.next_pc_inc;
628
629 return 1;
630 }
631 /* R2/R6 compatible cop1 instruction. Fall through */
632 case cop2_op:
633 case cop1x_op:
634 if (insn.i_format.rs == bc_op) {
635 preempt_disable();
636 if (is_fpu_owner())
637 fcr31 = read_32bit_cp1_register(CP1_STATUS);
638 else
639 fcr31 = current->thread.fpu.fcr31;
640 preempt_enable();
641
642 bit = (insn.i_format.rt >> 2);
643 bit += (bit != 0);
644 bit += 23;
645 switch (insn.i_format.rt & 3) {
646 case 0: /* bc1f */
647 case 2: /* bc1fl */
648 if (~fcr31 & (1 << bit))
649 *contpc = regs->cp0_epc +
650 dec_insn.pc_inc +
651 (insn.i_format.simmediate << 2);
652 else
653 *contpc = regs->cp0_epc +
654 dec_insn.pc_inc +
655 dec_insn.next_pc_inc;
656 return 1;
657 case 1: /* bc1t */
658 case 3: /* bc1tl */
659 if (fcr31 & (1 << bit))
660 *contpc = regs->cp0_epc +
661 dec_insn.pc_inc +
662 (insn.i_format.simmediate << 2);
663 else
664 *contpc = regs->cp0_epc +
665 dec_insn.pc_inc +
666 dec_insn.next_pc_inc;
667 return 1;
668 }
669 }
670 break;
671 }
672 return 0;
673 }
674
675 /*
676 * In the Linux kernel, we support selection of FPR format on the
677 * basis of the Status.FR bit. If an FPU is not present, the FR bit
678 * is hardwired to zero, which would imply a 32-bit FPU even for
679 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
680 * FPU emu is slow and bulky and optimizing this function offers fairly
681 * sizeable benefits so we try to be clever and make this function return
682 * a constant whenever possible, that is on 64-bit kernels without O32
683 * compatibility enabled and on 32-bit without 64-bit FPU support.
684 */
685 static inline int cop1_64bit(struct pt_regs *xcp)
686 {
687 if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
688 return 1;
689 else if (config_enabled(CONFIG_32BIT) &&
690 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
691 return 0;
692
693 return !test_thread_flag(TIF_32BIT_FPREGS);
694 }
695
696 static inline bool hybrid_fprs(void)
697 {
698 return test_thread_flag(TIF_HYBRID_FPREGS);
699 }
700
701 #define SIFROMREG(si, x) \
702 do { \
703 if (cop1_64bit(xcp) && !hybrid_fprs()) \
704 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \
705 else \
706 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
707 } while (0)
708
709 #define SITOREG(si, x) \
710 do { \
711 if (cop1_64bit(xcp) && !hybrid_fprs()) { \
712 unsigned i; \
713 set_fpr32(&ctx->fpr[x], 0, si); \
714 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
715 set_fpr32(&ctx->fpr[x], i, 0); \
716 } else { \
717 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
718 } \
719 } while (0)
720
721 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
722
723 #define SITOHREG(si, x) \
724 do { \
725 unsigned i; \
726 set_fpr32(&ctx->fpr[x], 1, si); \
727 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
728 set_fpr32(&ctx->fpr[x], i, 0); \
729 } while (0)
730
731 #define DIFROMREG(di, x) \
732 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
733
734 #define DITOREG(di, x) \
735 do { \
736 unsigned fpr, i; \
737 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
738 set_fpr64(&ctx->fpr[fpr], 0, di); \
739 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
740 set_fpr64(&ctx->fpr[fpr], i, 0); \
741 } while (0)
742
743 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
744 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
745 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
746 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
747
748 /*
749 * Emulate the single floating point instruction pointed at by EPC.
750 * Two instructions if the instruction is in a branch delay slot.
751 */
752
753 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
754 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
755 {
756 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
757 unsigned int cond, cbit;
758 mips_instruction ir;
759 int likely, pc_inc;
760 u32 __user *wva;
761 u64 __user *dva;
762 u32 value;
763 u32 wval;
764 u64 dval;
765 int sig;
766
767 /*
768 * These are giving gcc a gentle hint about what to expect in
769 * dec_inst in order to do better optimization.
770 */
771 if (!cpu_has_mmips && dec_insn.micro_mips_mode)
772 unreachable();
773
774 /* XXX NEC Vr54xx bug workaround */
775 if (delay_slot(xcp)) {
776 if (dec_insn.micro_mips_mode) {
777 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
778 clear_delay_slot(xcp);
779 } else {
780 if (!isBranchInstr(xcp, dec_insn, &contpc))
781 clear_delay_slot(xcp);
782 }
783 }
784
785 if (delay_slot(xcp)) {
786 /*
787 * The instruction to be emulated is in a branch delay slot
788 * which means that we have to emulate the branch instruction
789 * BEFORE we do the cop1 instruction.
790 *
791 * This branch could be a COP1 branch, but in that case we
792 * would have had a trap for that instruction, and would not
793 * come through this route.
794 *
795 * Linux MIPS branch emulator operates on context, updating the
796 * cp0_epc.
797 */
798 ir = dec_insn.next_insn; /* process delay slot instr */
799 pc_inc = dec_insn.next_pc_inc;
800 } else {
801 ir = dec_insn.insn; /* process current instr */
802 pc_inc = dec_insn.pc_inc;
803 }
804
805 /*
806 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
807 * instructions, we want to convert microMIPS FPU instructions
808 * into MIPS32 instructions so that we could reuse all of the
809 * FPU emulation code.
810 *
811 * NOTE: We cannot do this for branch instructions since they
812 * are not a subset. Example: Cannot emulate a 16-bit
813 * aligned target address with a MIPS32 instruction.
814 */
815 if (dec_insn.micro_mips_mode) {
816 /*
817 * If next instruction is a 16-bit instruction, then it
818 * it cannot be a FPU instruction. This could happen
819 * since we can be called for non-FPU instructions.
820 */
821 if ((pc_inc == 2) ||
822 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
823 == SIGILL))
824 return SIGILL;
825 }
826
827 emul:
828 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
829 MIPS_FPU_EMU_INC_STATS(emulated);
830 switch (MIPSInst_OPCODE(ir)) {
831 case ldc1_op:
832 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
833 MIPSInst_SIMM(ir));
834 MIPS_FPU_EMU_INC_STATS(loads);
835
836 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
837 MIPS_FPU_EMU_INC_STATS(errors);
838 *fault_addr = dva;
839 return SIGBUS;
840 }
841 if (__get_user(dval, dva)) {
842 MIPS_FPU_EMU_INC_STATS(errors);
843 *fault_addr = dva;
844 return SIGSEGV;
845 }
846 DITOREG(dval, MIPSInst_RT(ir));
847 break;
848
849 case sdc1_op:
850 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
851 MIPSInst_SIMM(ir));
852 MIPS_FPU_EMU_INC_STATS(stores);
853 DIFROMREG(dval, MIPSInst_RT(ir));
854 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
855 MIPS_FPU_EMU_INC_STATS(errors);
856 *fault_addr = dva;
857 return SIGBUS;
858 }
859 if (__put_user(dval, dva)) {
860 MIPS_FPU_EMU_INC_STATS(errors);
861 *fault_addr = dva;
862 return SIGSEGV;
863 }
864 break;
865
866 case lwc1_op:
867 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
868 MIPSInst_SIMM(ir));
869 MIPS_FPU_EMU_INC_STATS(loads);
870 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
871 MIPS_FPU_EMU_INC_STATS(errors);
872 *fault_addr = wva;
873 return SIGBUS;
874 }
875 if (__get_user(wval, wva)) {
876 MIPS_FPU_EMU_INC_STATS(errors);
877 *fault_addr = wva;
878 return SIGSEGV;
879 }
880 SITOREG(wval, MIPSInst_RT(ir));
881 break;
882
883 case swc1_op:
884 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
885 MIPSInst_SIMM(ir));
886 MIPS_FPU_EMU_INC_STATS(stores);
887 SIFROMREG(wval, MIPSInst_RT(ir));
888 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
889 MIPS_FPU_EMU_INC_STATS(errors);
890 *fault_addr = wva;
891 return SIGBUS;
892 }
893 if (__put_user(wval, wva)) {
894 MIPS_FPU_EMU_INC_STATS(errors);
895 *fault_addr = wva;
896 return SIGSEGV;
897 }
898 break;
899
900 case cop1_op:
901 switch (MIPSInst_RS(ir)) {
902 case dmfc_op:
903 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
904 return SIGILL;
905
906 /* copregister fs -> gpr[rt] */
907 if (MIPSInst_RT(ir) != 0) {
908 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
909 MIPSInst_RD(ir));
910 }
911 break;
912
913 case dmtc_op:
914 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
915 return SIGILL;
916
917 /* copregister fs <- rt */
918 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
919 break;
920
921 case mfhc_op:
922 if (!cpu_has_mips_r2)
923 goto sigill;
924
925 /* copregister rd -> gpr[rt] */
926 if (MIPSInst_RT(ir) != 0) {
927 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
928 MIPSInst_RD(ir));
929 }
930 break;
931
932 case mthc_op:
933 if (!cpu_has_mips_r2)
934 goto sigill;
935
936 /* copregister rd <- gpr[rt] */
937 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
938 break;
939
940 case mfc_op:
941 /* copregister rd -> gpr[rt] */
942 if (MIPSInst_RT(ir) != 0) {
943 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
944 MIPSInst_RD(ir));
945 }
946 break;
947
948 case mtc_op:
949 /* copregister rd <- rt */
950 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
951 break;
952
953 case cfc_op:
954 /* cop control register rd -> gpr[rt] */
955 if (MIPSInst_RD(ir) == FPCREG_CSR) {
956 value = ctx->fcr31;
957 value = (value & ~FPU_CSR_RM) | modeindex(value);
958 pr_debug("%p gpr[%d]<-csr=%08x\n",
959 (void *) (xcp->cp0_epc),
960 MIPSInst_RT(ir), value);
961 }
962 else if (MIPSInst_RD(ir) == FPCREG_RID)
963 value = 0;
964 else
965 value = 0;
966 if (MIPSInst_RT(ir))
967 xcp->regs[MIPSInst_RT(ir)] = value;
968 break;
969
970 case ctc_op:
971 /* copregister rd <- rt */
972 if (MIPSInst_RT(ir) == 0)
973 value = 0;
974 else
975 value = xcp->regs[MIPSInst_RT(ir)];
976
977 /* we only have one writable control reg
978 */
979 if (MIPSInst_RD(ir) == FPCREG_CSR) {
980 pr_debug("%p gpr[%d]->csr=%08x\n",
981 (void *) (xcp->cp0_epc),
982 MIPSInst_RT(ir), value);
983
984 /*
985 * Don't write reserved bits,
986 * and convert to ieee library modes
987 */
988 ctx->fcr31 = (value & ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
989 modeindex(value);
990 }
991 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
992 return SIGFPE;
993 }
994 break;
995
996 case bc_op:
997 if (delay_slot(xcp))
998 return SIGILL;
999
1000 if (cpu_has_mips_4_5_r)
1001 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1002 else
1003 cbit = FPU_CSR_COND;
1004 cond = ctx->fcr31 & cbit;
1005
1006 likely = 0;
1007 switch (MIPSInst_RT(ir) & 3) {
1008 case bcfl_op:
1009 likely = 1;
1010 case bcf_op:
1011 cond = !cond;
1012 break;
1013 case bctl_op:
1014 likely = 1;
1015 case bct_op:
1016 break;
1017 default:
1018 /* thats an illegal instruction */
1019 return SIGILL;
1020 }
1021
1022 set_delay_slot(xcp);
1023 if (cond) {
1024 /*
1025 * Branch taken: emulate dslot instruction
1026 */
1027 xcp->cp0_epc += dec_insn.pc_inc;
1028
1029 contpc = MIPSInst_SIMM(ir);
1030 ir = dec_insn.next_insn;
1031 if (dec_insn.micro_mips_mode) {
1032 contpc = (xcp->cp0_epc + (contpc << 1));
1033
1034 /* If 16-bit instruction, not FPU. */
1035 if ((dec_insn.next_pc_inc == 2) ||
1036 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1037
1038 /*
1039 * Since this instruction will
1040 * be put on the stack with
1041 * 32-bit words, get around
1042 * this problem by putting a
1043 * NOP16 as the second one.
1044 */
1045 if (dec_insn.next_pc_inc == 2)
1046 ir = (ir & (~0xffff)) | MM_NOP16;
1047
1048 /*
1049 * Single step the non-CP1
1050 * instruction in the dslot.
1051 */
1052 return mips_dsemul(xcp, ir, contpc);
1053 }
1054 } else
1055 contpc = (xcp->cp0_epc + (contpc << 2));
1056
1057 switch (MIPSInst_OPCODE(ir)) {
1058 case lwc1_op:
1059 goto emul;
1060
1061 case swc1_op:
1062 goto emul;
1063
1064 case ldc1_op:
1065 case sdc1_op:
1066 if (cpu_has_mips_2_3_4_5 ||
1067 cpu_has_mips64)
1068 goto emul;
1069
1070 return SIGILL;
1071 goto emul;
1072
1073 case cop1_op:
1074 goto emul;
1075
1076 case cop1x_op:
1077 if (cpu_has_mips_4_5 || cpu_has_mips64 || cpu_has_mips32r2)
1078 /* its one of ours */
1079 goto emul;
1080
1081 return SIGILL;
1082
1083 case spec_op:
1084 if (!cpu_has_mips_4_5_r)
1085 return SIGILL;
1086
1087 if (MIPSInst_FUNC(ir) == movc_op)
1088 goto emul;
1089 break;
1090 }
1091
1092 /*
1093 * Single step the non-cp1
1094 * instruction in the dslot
1095 */
1096 return mips_dsemul(xcp, ir, contpc);
1097 } else if (likely) { /* branch not taken */
1098 /*
1099 * branch likely nullifies
1100 * dslot if not taken
1101 */
1102 xcp->cp0_epc += dec_insn.pc_inc;
1103 contpc += dec_insn.pc_inc;
1104 /*
1105 * else continue & execute
1106 * dslot as normal insn
1107 */
1108 }
1109 break;
1110
1111 default:
1112 if (!(MIPSInst_RS(ir) & 0x10))
1113 return SIGILL;
1114
1115 /* a real fpu computation instruction */
1116 if ((sig = fpu_emu(xcp, ctx, ir)))
1117 return sig;
1118 }
1119 break;
1120
1121 case cop1x_op:
1122 if (!cpu_has_mips_4_5 && !cpu_has_mips64 && !cpu_has_mips32r2)
1123 return SIGILL;
1124
1125 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1126 if (sig)
1127 return sig;
1128 break;
1129
1130 case spec_op:
1131 if (!cpu_has_mips_4_5_r)
1132 return SIGILL;
1133
1134 if (MIPSInst_FUNC(ir) != movc_op)
1135 return SIGILL;
1136 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1137 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1138 xcp->regs[MIPSInst_RD(ir)] =
1139 xcp->regs[MIPSInst_RS(ir)];
1140 break;
1141 default:
1142 sigill:
1143 return SIGILL;
1144 }
1145
1146 /* we did it !! */
1147 xcp->cp0_epc = contpc;
1148 clear_delay_slot(xcp);
1149
1150 return 0;
1151 }
1152
1153 /*
1154 * Conversion table from MIPS compare ops 48-63
1155 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1156 */
1157 static const unsigned char cmptab[8] = {
1158 0, /* cmp_0 (sig) cmp_sf */
1159 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1160 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1161 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1162 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1163 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1164 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1165 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1166 };
1167
1168
1169 /*
1170 * Additional MIPS4 instructions
1171 */
1172
1173 #define DEF3OP(name, p, f1, f2, f3) \
1174 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1175 union ieee754##p s, union ieee754##p t) \
1176 { \
1177 struct _ieee754_csr ieee754_csr_save; \
1178 s = f1(s, t); \
1179 ieee754_csr_save = ieee754_csr; \
1180 s = f2(s, r); \
1181 ieee754_csr_save.cx |= ieee754_csr.cx; \
1182 ieee754_csr_save.sx |= ieee754_csr.sx; \
1183 s = f3(s); \
1184 ieee754_csr.cx |= ieee754_csr_save.cx; \
1185 ieee754_csr.sx |= ieee754_csr_save.sx; \
1186 return s; \
1187 }
1188
1189 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1190 {
1191 return ieee754dp_div(ieee754dp_one(0), d);
1192 }
1193
1194 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1195 {
1196 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1197 }
1198
1199 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1200 {
1201 return ieee754sp_div(ieee754sp_one(0), s);
1202 }
1203
1204 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1205 {
1206 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1207 }
1208
1209 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1210 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1211 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1212 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1213 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1214 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1215 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1216 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1217
1218 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1219 mips_instruction ir, void *__user *fault_addr)
1220 {
1221 unsigned rcsr = 0; /* resulting csr */
1222
1223 MIPS_FPU_EMU_INC_STATS(cp1xops);
1224
1225 switch (MIPSInst_FMA_FFMT(ir)) {
1226 case s_fmt:{ /* 0 */
1227
1228 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1229 union ieee754sp fd, fr, fs, ft;
1230 u32 __user *va;
1231 u32 val;
1232
1233 switch (MIPSInst_FUNC(ir)) {
1234 case lwxc1_op:
1235 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1236 xcp->regs[MIPSInst_FT(ir)]);
1237
1238 MIPS_FPU_EMU_INC_STATS(loads);
1239 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1240 MIPS_FPU_EMU_INC_STATS(errors);
1241 *fault_addr = va;
1242 return SIGBUS;
1243 }
1244 if (__get_user(val, va)) {
1245 MIPS_FPU_EMU_INC_STATS(errors);
1246 *fault_addr = va;
1247 return SIGSEGV;
1248 }
1249 SITOREG(val, MIPSInst_FD(ir));
1250 break;
1251
1252 case swxc1_op:
1253 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1254 xcp->regs[MIPSInst_FT(ir)]);
1255
1256 MIPS_FPU_EMU_INC_STATS(stores);
1257
1258 SIFROMREG(val, MIPSInst_FS(ir));
1259 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1260 MIPS_FPU_EMU_INC_STATS(errors);
1261 *fault_addr = va;
1262 return SIGBUS;
1263 }
1264 if (put_user(val, va)) {
1265 MIPS_FPU_EMU_INC_STATS(errors);
1266 *fault_addr = va;
1267 return SIGSEGV;
1268 }
1269 break;
1270
1271 case madd_s_op:
1272 handler = fpemu_sp_madd;
1273 goto scoptop;
1274 case msub_s_op:
1275 handler = fpemu_sp_msub;
1276 goto scoptop;
1277 case nmadd_s_op:
1278 handler = fpemu_sp_nmadd;
1279 goto scoptop;
1280 case nmsub_s_op:
1281 handler = fpemu_sp_nmsub;
1282 goto scoptop;
1283
1284 scoptop:
1285 SPFROMREG(fr, MIPSInst_FR(ir));
1286 SPFROMREG(fs, MIPSInst_FS(ir));
1287 SPFROMREG(ft, MIPSInst_FT(ir));
1288 fd = (*handler) (fr, fs, ft);
1289 SPTOREG(fd, MIPSInst_FD(ir));
1290
1291 copcsr:
1292 if (ieee754_cxtest(IEEE754_INEXACT)) {
1293 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1294 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1295 }
1296 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1297 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1298 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1299 }
1300 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1301 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1302 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1303 }
1304 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1305 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1306 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1307 }
1308
1309 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1310 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1311 /*printk ("SIGFPE: FPU csr = %08x\n",
1312 ctx->fcr31); */
1313 return SIGFPE;
1314 }
1315
1316 break;
1317
1318 default:
1319 return SIGILL;
1320 }
1321 break;
1322 }
1323
1324 case d_fmt:{ /* 1 */
1325 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1326 union ieee754dp fd, fr, fs, ft;
1327 u64 __user *va;
1328 u64 val;
1329
1330 switch (MIPSInst_FUNC(ir)) {
1331 case ldxc1_op:
1332 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1333 xcp->regs[MIPSInst_FT(ir)]);
1334
1335 MIPS_FPU_EMU_INC_STATS(loads);
1336 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1337 MIPS_FPU_EMU_INC_STATS(errors);
1338 *fault_addr = va;
1339 return SIGBUS;
1340 }
1341 if (__get_user(val, va)) {
1342 MIPS_FPU_EMU_INC_STATS(errors);
1343 *fault_addr = va;
1344 return SIGSEGV;
1345 }
1346 DITOREG(val, MIPSInst_FD(ir));
1347 break;
1348
1349 case sdxc1_op:
1350 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1351 xcp->regs[MIPSInst_FT(ir)]);
1352
1353 MIPS_FPU_EMU_INC_STATS(stores);
1354 DIFROMREG(val, MIPSInst_FS(ir));
1355 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1356 MIPS_FPU_EMU_INC_STATS(errors);
1357 *fault_addr = va;
1358 return SIGBUS;
1359 }
1360 if (__put_user(val, va)) {
1361 MIPS_FPU_EMU_INC_STATS(errors);
1362 *fault_addr = va;
1363 return SIGSEGV;
1364 }
1365 break;
1366
1367 case madd_d_op:
1368 handler = fpemu_dp_madd;
1369 goto dcoptop;
1370 case msub_d_op:
1371 handler = fpemu_dp_msub;
1372 goto dcoptop;
1373 case nmadd_d_op:
1374 handler = fpemu_dp_nmadd;
1375 goto dcoptop;
1376 case nmsub_d_op:
1377 handler = fpemu_dp_nmsub;
1378 goto dcoptop;
1379
1380 dcoptop:
1381 DPFROMREG(fr, MIPSInst_FR(ir));
1382 DPFROMREG(fs, MIPSInst_FS(ir));
1383 DPFROMREG(ft, MIPSInst_FT(ir));
1384 fd = (*handler) (fr, fs, ft);
1385 DPTOREG(fd, MIPSInst_FD(ir));
1386 goto copcsr;
1387
1388 default:
1389 return SIGILL;
1390 }
1391 break;
1392 }
1393
1394 case 0x3:
1395 if (MIPSInst_FUNC(ir) != pfetch_op)
1396 return SIGILL;
1397
1398 /* ignore prefx operation */
1399 break;
1400
1401 default:
1402 return SIGILL;
1403 }
1404
1405 return 0;
1406 }
1407
1408
1409
1410 /*
1411 * Emulate a single COP1 arithmetic instruction.
1412 */
1413 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1414 mips_instruction ir)
1415 {
1416 int rfmt; /* resulting format */
1417 unsigned rcsr = 0; /* resulting csr */
1418 unsigned int oldrm;
1419 unsigned int cbit;
1420 unsigned cond;
1421 union {
1422 union ieee754dp d;
1423 union ieee754sp s;
1424 int w;
1425 s64 l;
1426 } rv; /* resulting value */
1427 u64 bits;
1428
1429 MIPS_FPU_EMU_INC_STATS(cp1ops);
1430 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1431 case s_fmt: { /* 0 */
1432 union {
1433 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1434 union ieee754sp(*u) (union ieee754sp);
1435 } handler;
1436 union ieee754sp fs, ft;
1437
1438 switch (MIPSInst_FUNC(ir)) {
1439 /* binary ops */
1440 case fadd_op:
1441 handler.b = ieee754sp_add;
1442 goto scopbop;
1443 case fsub_op:
1444 handler.b = ieee754sp_sub;
1445 goto scopbop;
1446 case fmul_op:
1447 handler.b = ieee754sp_mul;
1448 goto scopbop;
1449 case fdiv_op:
1450 handler.b = ieee754sp_div;
1451 goto scopbop;
1452
1453 /* unary ops */
1454 case fsqrt_op:
1455 if (!cpu_has_mips_4_5_r)
1456 return SIGILL;
1457
1458 handler.u = ieee754sp_sqrt;
1459 goto scopuop;
1460
1461 /*
1462 * Note that on some MIPS IV implementations such as the
1463 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1464 * achieve full IEEE-754 accuracy - however this emulator does.
1465 */
1466 case frsqrt_op:
1467 if (!cpu_has_mips_4_5_r2)
1468 return SIGILL;
1469
1470 handler.u = fpemu_sp_rsqrt;
1471 goto scopuop;
1472
1473 case frecip_op:
1474 if (!cpu_has_mips_4_5_r2)
1475 return SIGILL;
1476
1477 handler.u = fpemu_sp_recip;
1478 goto scopuop;
1479
1480 case fmovc_op:
1481 if (!cpu_has_mips_4_5_r)
1482 return SIGILL;
1483
1484 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1485 if (((ctx->fcr31 & cond) != 0) !=
1486 ((MIPSInst_FT(ir) & 1) != 0))
1487 return 0;
1488 SPFROMREG(rv.s, MIPSInst_FS(ir));
1489 break;
1490
1491 case fmovz_op:
1492 if (!cpu_has_mips_4_5_r)
1493 return SIGILL;
1494
1495 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1496 return 0;
1497 SPFROMREG(rv.s, MIPSInst_FS(ir));
1498 break;
1499
1500 case fmovn_op:
1501 if (!cpu_has_mips_4_5_r)
1502 return SIGILL;
1503
1504 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1505 return 0;
1506 SPFROMREG(rv.s, MIPSInst_FS(ir));
1507 break;
1508
1509 case fabs_op:
1510 handler.u = ieee754sp_abs;
1511 goto scopuop;
1512
1513 case fneg_op:
1514 handler.u = ieee754sp_neg;
1515 goto scopuop;
1516
1517 case fmov_op:
1518 /* an easy one */
1519 SPFROMREG(rv.s, MIPSInst_FS(ir));
1520 goto copcsr;
1521
1522 /* binary op on handler */
1523 scopbop:
1524 SPFROMREG(fs, MIPSInst_FS(ir));
1525 SPFROMREG(ft, MIPSInst_FT(ir));
1526
1527 rv.s = (*handler.b) (fs, ft);
1528 goto copcsr;
1529 scopuop:
1530 SPFROMREG(fs, MIPSInst_FS(ir));
1531 rv.s = (*handler.u) (fs);
1532 goto copcsr;
1533 copcsr:
1534 if (ieee754_cxtest(IEEE754_INEXACT)) {
1535 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1536 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1537 }
1538 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1539 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1540 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1541 }
1542 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1543 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1544 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1545 }
1546 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1547 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1548 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1549 }
1550 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1551 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1552 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1553 }
1554 break;
1555
1556 /* unary conv ops */
1557 case fcvts_op:
1558 return SIGILL; /* not defined */
1559
1560 case fcvtd_op:
1561 SPFROMREG(fs, MIPSInst_FS(ir));
1562 rv.d = ieee754dp_fsp(fs);
1563 rfmt = d_fmt;
1564 goto copcsr;
1565
1566 case fcvtw_op:
1567 SPFROMREG(fs, MIPSInst_FS(ir));
1568 rv.w = ieee754sp_tint(fs);
1569 rfmt = w_fmt;
1570 goto copcsr;
1571
1572 case fround_op:
1573 case ftrunc_op:
1574 case fceil_op:
1575 case ffloor_op:
1576 if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64)
1577 return SIGILL;
1578
1579 oldrm = ieee754_csr.rm;
1580 SPFROMREG(fs, MIPSInst_FS(ir));
1581 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1582 rv.w = ieee754sp_tint(fs);
1583 ieee754_csr.rm = oldrm;
1584 rfmt = w_fmt;
1585 goto copcsr;
1586
1587 case fcvtl_op:
1588 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1589 return SIGILL;
1590
1591 SPFROMREG(fs, MIPSInst_FS(ir));
1592 rv.l = ieee754sp_tlong(fs);
1593 rfmt = l_fmt;
1594 goto copcsr;
1595
1596 case froundl_op:
1597 case ftruncl_op:
1598 case fceill_op:
1599 case ffloorl_op:
1600 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1601 return SIGILL;
1602
1603 oldrm = ieee754_csr.rm;
1604 SPFROMREG(fs, MIPSInst_FS(ir));
1605 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1606 rv.l = ieee754sp_tlong(fs);
1607 ieee754_csr.rm = oldrm;
1608 rfmt = l_fmt;
1609 goto copcsr;
1610
1611 default:
1612 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1613 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1614 union ieee754sp fs, ft;
1615
1616 SPFROMREG(fs, MIPSInst_FS(ir));
1617 SPFROMREG(ft, MIPSInst_FT(ir));
1618 rv.w = ieee754sp_cmp(fs, ft,
1619 cmptab[cmpop & 0x7], cmpop & 0x8);
1620 rfmt = -1;
1621 if ((cmpop & 0x8) && ieee754_cxtest
1622 (IEEE754_INVALID_OPERATION))
1623 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1624 else
1625 goto copcsr;
1626
1627 } else
1628 return SIGILL;
1629 break;
1630 }
1631 break;
1632 }
1633
1634 case d_fmt: {
1635 union ieee754dp fs, ft;
1636 union {
1637 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1638 union ieee754dp(*u) (union ieee754dp);
1639 } handler;
1640
1641 switch (MIPSInst_FUNC(ir)) {
1642 /* binary ops */
1643 case fadd_op:
1644 handler.b = ieee754dp_add;
1645 goto dcopbop;
1646 case fsub_op:
1647 handler.b = ieee754dp_sub;
1648 goto dcopbop;
1649 case fmul_op:
1650 handler.b = ieee754dp_mul;
1651 goto dcopbop;
1652 case fdiv_op:
1653 handler.b = ieee754dp_div;
1654 goto dcopbop;
1655
1656 /* unary ops */
1657 case fsqrt_op:
1658 if (!cpu_has_mips_2_3_4_5_r)
1659 return SIGILL;
1660
1661 handler.u = ieee754dp_sqrt;
1662 goto dcopuop;
1663 /*
1664 * Note that on some MIPS IV implementations such as the
1665 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1666 * achieve full IEEE-754 accuracy - however this emulator does.
1667 */
1668 case frsqrt_op:
1669 if (!cpu_has_mips_4_5_r2)
1670 return SIGILL;
1671
1672 handler.u = fpemu_dp_rsqrt;
1673 goto dcopuop;
1674 case frecip_op:
1675 if (!cpu_has_mips_4_5_r2)
1676 return SIGILL;
1677
1678 handler.u = fpemu_dp_recip;
1679 goto dcopuop;
1680 case fmovc_op:
1681 if (!cpu_has_mips_4_5_r)
1682 return SIGILL;
1683
1684 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1685 if (((ctx->fcr31 & cond) != 0) !=
1686 ((MIPSInst_FT(ir) & 1) != 0))
1687 return 0;
1688 DPFROMREG(rv.d, MIPSInst_FS(ir));
1689 break;
1690 case fmovz_op:
1691 if (!cpu_has_mips_4_5_r)
1692 return SIGILL;
1693
1694 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1695 return 0;
1696 DPFROMREG(rv.d, MIPSInst_FS(ir));
1697 break;
1698 case fmovn_op:
1699 if (!cpu_has_mips_4_5_r)
1700 return SIGILL;
1701
1702 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1703 return 0;
1704 DPFROMREG(rv.d, MIPSInst_FS(ir));
1705 break;
1706 case fabs_op:
1707 handler.u = ieee754dp_abs;
1708 goto dcopuop;
1709
1710 case fneg_op:
1711 handler.u = ieee754dp_neg;
1712 goto dcopuop;
1713
1714 case fmov_op:
1715 /* an easy one */
1716 DPFROMREG(rv.d, MIPSInst_FS(ir));
1717 goto copcsr;
1718
1719 /* binary op on handler */
1720 dcopbop:
1721 DPFROMREG(fs, MIPSInst_FS(ir));
1722 DPFROMREG(ft, MIPSInst_FT(ir));
1723
1724 rv.d = (*handler.b) (fs, ft);
1725 goto copcsr;
1726 dcopuop:
1727 DPFROMREG(fs, MIPSInst_FS(ir));
1728 rv.d = (*handler.u) (fs);
1729 goto copcsr;
1730
1731 /*
1732 * unary conv ops
1733 */
1734 case fcvts_op:
1735 DPFROMREG(fs, MIPSInst_FS(ir));
1736 rv.s = ieee754sp_fdp(fs);
1737 rfmt = s_fmt;
1738 goto copcsr;
1739
1740 case fcvtd_op:
1741 return SIGILL; /* not defined */
1742
1743 case fcvtw_op:
1744 DPFROMREG(fs, MIPSInst_FS(ir));
1745 rv.w = ieee754dp_tint(fs); /* wrong */
1746 rfmt = w_fmt;
1747 goto copcsr;
1748
1749 case fround_op:
1750 case ftrunc_op:
1751 case fceil_op:
1752 case ffloor_op:
1753 if (!cpu_has_mips_2_3_4_5_r)
1754 return SIGILL;
1755
1756 oldrm = ieee754_csr.rm;
1757 DPFROMREG(fs, MIPSInst_FS(ir));
1758 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1759 rv.w = ieee754dp_tint(fs);
1760 ieee754_csr.rm = oldrm;
1761 rfmt = w_fmt;
1762 goto copcsr;
1763
1764 case fcvtl_op:
1765 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1766 return SIGILL;
1767
1768 DPFROMREG(fs, MIPSInst_FS(ir));
1769 rv.l = ieee754dp_tlong(fs);
1770 rfmt = l_fmt;
1771 goto copcsr;
1772
1773 case froundl_op:
1774 case ftruncl_op:
1775 case fceill_op:
1776 case ffloorl_op:
1777 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1778 return SIGILL;
1779
1780 oldrm = ieee754_csr.rm;
1781 DPFROMREG(fs, MIPSInst_FS(ir));
1782 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1783 rv.l = ieee754dp_tlong(fs);
1784 ieee754_csr.rm = oldrm;
1785 rfmt = l_fmt;
1786 goto copcsr;
1787
1788 default:
1789 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1790 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1791 union ieee754dp fs, ft;
1792
1793 DPFROMREG(fs, MIPSInst_FS(ir));
1794 DPFROMREG(ft, MIPSInst_FT(ir));
1795 rv.w = ieee754dp_cmp(fs, ft,
1796 cmptab[cmpop & 0x7], cmpop & 0x8);
1797 rfmt = -1;
1798 if ((cmpop & 0x8)
1799 &&
1800 ieee754_cxtest
1801 (IEEE754_INVALID_OPERATION))
1802 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1803 else
1804 goto copcsr;
1805
1806 }
1807 else {
1808 return SIGILL;
1809 }
1810 break;
1811 }
1812 break;
1813
1814 case w_fmt:
1815 switch (MIPSInst_FUNC(ir)) {
1816 case fcvts_op:
1817 /* convert word to single precision real */
1818 SPFROMREG(fs, MIPSInst_FS(ir));
1819 rv.s = ieee754sp_fint(fs.bits);
1820 rfmt = s_fmt;
1821 goto copcsr;
1822 case fcvtd_op:
1823 /* convert word to double precision real */
1824 SPFROMREG(fs, MIPSInst_FS(ir));
1825 rv.d = ieee754dp_fint(fs.bits);
1826 rfmt = d_fmt;
1827 goto copcsr;
1828 default:
1829 return SIGILL;
1830 }
1831 break;
1832 }
1833
1834 case l_fmt:
1835
1836 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1837 return SIGILL;
1838
1839 DIFROMREG(bits, MIPSInst_FS(ir));
1840
1841 switch (MIPSInst_FUNC(ir)) {
1842 case fcvts_op:
1843 /* convert long to single precision real */
1844 rv.s = ieee754sp_flong(bits);
1845 rfmt = s_fmt;
1846 goto copcsr;
1847 case fcvtd_op:
1848 /* convert long to double precision real */
1849 rv.d = ieee754dp_flong(bits);
1850 rfmt = d_fmt;
1851 goto copcsr;
1852 default:
1853 return SIGILL;
1854 }
1855 break;
1856
1857 default:
1858 return SIGILL;
1859 }
1860
1861 /*
1862 * Update the fpu CSR register for this operation.
1863 * If an exception is required, generate a tidy SIGFPE exception,
1864 * without updating the result register.
1865 * Note: cause exception bits do not accumulate, they are rewritten
1866 * for each op; only the flag/sticky bits accumulate.
1867 */
1868 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1869 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1870 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
1871 return SIGFPE;
1872 }
1873
1874 /*
1875 * Now we can safely write the result back to the register file.
1876 */
1877 switch (rfmt) {
1878 case -1:
1879
1880 if (cpu_has_mips_4_5_r)
1881 cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
1882 else
1883 cbit = FPU_CSR_COND;
1884 if (rv.w)
1885 ctx->fcr31 |= cbit;
1886 else
1887 ctx->fcr31 &= ~cbit;
1888 break;
1889
1890 case d_fmt:
1891 DPTOREG(rv.d, MIPSInst_FD(ir));
1892 break;
1893 case s_fmt:
1894 SPTOREG(rv.s, MIPSInst_FD(ir));
1895 break;
1896 case w_fmt:
1897 SITOREG(rv.w, MIPSInst_FD(ir));
1898 break;
1899 case l_fmt:
1900 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1901 return SIGILL;
1902
1903 DITOREG(rv.l, MIPSInst_FD(ir));
1904 break;
1905 default:
1906 return SIGILL;
1907 }
1908
1909 return 0;
1910 }
1911
1912 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1913 int has_fpu, void *__user *fault_addr)
1914 {
1915 unsigned long oldepc, prevepc;
1916 struct mm_decoded_insn dec_insn;
1917 u16 instr[4];
1918 u16 *instr_ptr;
1919 int sig = 0;
1920
1921 oldepc = xcp->cp0_epc;
1922 do {
1923 prevepc = xcp->cp0_epc;
1924
1925 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
1926 /*
1927 * Get next 2 microMIPS instructions and convert them
1928 * into 32-bit instructions.
1929 */
1930 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
1931 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
1932 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
1933 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
1934 MIPS_FPU_EMU_INC_STATS(errors);
1935 return SIGBUS;
1936 }
1937 instr_ptr = instr;
1938
1939 /* Get first instruction. */
1940 if (mm_insn_16bit(*instr_ptr)) {
1941 /* Duplicate the half-word. */
1942 dec_insn.insn = (*instr_ptr << 16) |
1943 (*instr_ptr);
1944 /* 16-bit instruction. */
1945 dec_insn.pc_inc = 2;
1946 instr_ptr += 1;
1947 } else {
1948 dec_insn.insn = (*instr_ptr << 16) |
1949 *(instr_ptr+1);
1950 /* 32-bit instruction. */
1951 dec_insn.pc_inc = 4;
1952 instr_ptr += 2;
1953 }
1954 /* Get second instruction. */
1955 if (mm_insn_16bit(*instr_ptr)) {
1956 /* Duplicate the half-word. */
1957 dec_insn.next_insn = (*instr_ptr << 16) |
1958 (*instr_ptr);
1959 /* 16-bit instruction. */
1960 dec_insn.next_pc_inc = 2;
1961 } else {
1962 dec_insn.next_insn = (*instr_ptr << 16) |
1963 *(instr_ptr+1);
1964 /* 32-bit instruction. */
1965 dec_insn.next_pc_inc = 4;
1966 }
1967 dec_insn.micro_mips_mode = 1;
1968 } else {
1969 if ((get_user(dec_insn.insn,
1970 (mips_instruction __user *) xcp->cp0_epc)) ||
1971 (get_user(dec_insn.next_insn,
1972 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
1973 MIPS_FPU_EMU_INC_STATS(errors);
1974 return SIGBUS;
1975 }
1976 dec_insn.pc_inc = 4;
1977 dec_insn.next_pc_inc = 4;
1978 dec_insn.micro_mips_mode = 0;
1979 }
1980
1981 if ((dec_insn.insn == 0) ||
1982 ((dec_insn.pc_inc == 2) &&
1983 ((dec_insn.insn & 0xffff) == MM_NOP16)))
1984 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
1985 else {
1986 /*
1987 * The 'ieee754_csr' is an alias of
1988 * ctx->fcr31. No need to copy ctx->fcr31 to
1989 * ieee754_csr. But ieee754_csr.rm is ieee
1990 * library modes. (not mips rounding mode)
1991 */
1992 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
1993 }
1994
1995 if (has_fpu)
1996 break;
1997 if (sig)
1998 break;
1999
2000 cond_resched();
2001 } while (xcp->cp0_epc > prevepc);
2002
2003 /* SIGILL indicates a non-fpu instruction */
2004 if (sig == SIGILL && xcp->cp0_epc != oldepc)
2005 /* but if EPC has advanced, then ignore it */
2006 sig = 0;
2007
2008 return sig;
2009 }
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