arch/mips/mips-boards/generic/mipsIRQ.S

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 1999, 2000 MIPS Technologies, Inc.  All rights reserved.
   4  *
   5  * ########################################################################
   6  *
   7  *  This program is free software; you can distribute it and/or modify it
   8  *  under the terms of the GNU General Public License (Version 2) as
   9  *  published by the Free Software Foundation.
  10  *
  11  *  This program is distributed in the hope it will be useful, but WITHOUT
  12  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  *  for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License along
  17  *  with this program; if not, write to the Free Software Foundation, Inc.,
  18  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  19  *
  20  * ########################################################################
  21  *
  22  * Interrupt exception dispatch code.
  23  *
  24  */
  25 #include <linux/config.h>
  26
  27 #include <asm/asm.h>
  28 #include <asm/mipsregs.h>
  29 #include <asm/regdef.h>
  30 #include <asm/stackframe.h>
  31
  32 /* A lot of complication here is taken away because:
  33  *
  34  * 1) We handle one interrupt and return, sitting in a loop and moving across
  35  *    all the pending IRQ bits in the cause register is _NOT_ the answer, the
  36  *    common case is one pending IRQ so optimize in that direction.
  37  *
  38  * 2) We need not check against bits in the status register IRQ mask, that
  39  *    would make this routine slow as hell.
  40  *
  41  * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
  42  *    between like BSD spl() brain-damage.
  43  *
  44  * Furthermore, the IRQs on the MIPS board look basically (barring software
  45  * IRQs which we don't use at all and all external interrupt sources are
  46  * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
  47  *
  48  *      MIPS IRQ        Source
  49  *      --------        ------
  50  *             0        Software (ignored)
  51  *             1        Software (ignored)
  52  *             2        Combined hardware interrupt (hw0)
  53  *             3        Hardware (ignored)
  54  *             4        Hardware (ignored)
  55  *             5        Hardware (ignored)
  56  *             6        Hardware (ignored)
  57  *             7        R4k timer (what we use)
  58  *
  59  * Note: On the SEAD board thing are a little bit different.
  60  *       Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
  61  *       wired to UART1.
  62  *
  63  * We handle the IRQ according to _our_ priority which is:
  64  *
  65  * Highest ----     R4k Timer
  66  * Lowest  ----     Combined hardware interrupt
  67  *
  68  * then we just return, if multiple IRQs are pending then we will just take
  69  * another exception, big deal.
  70  */
  71
  72         .text
  73         .set    noreorder
  74         .set    noat
  75         .align  5
  76         NESTED(mipsIRQ, PT_SIZE, sp)
  77         SAVE_ALL
  78         CLI
  79         .set    at
  80
  81         mfc0    s0, CP0_CAUSE           # get irq bits
  82         mfc0    s1, CP0_STATUS          # get irq mask
  83         and     s0, s1
  84
  85         /* First we check for r4k counter/timer IRQ. */
  86         andi    a0, s0, CAUSEF_IP7
  87         beq     a0, zero, 1f
  88          andi   a0, s0, CAUSEF_IP2      # delay slot, check hw0 interrupt
  89
  90         /* Wheee, a timer interrupt. */
  91         move    a0, sp
  92         jal     mips_timer_interrupt
  93          nop
  94
  95         j       ret_from_irq
  96          nop
  97
  98 1:
  99 #if defined(CONFIG_MIPS_SEAD)
 100         beq     a0, zero, 1f
 101          andi   a0, s0, CAUSEF_IP3      # delay slot, check hw1 interrupt
 102 #else
 103         beq     a0, zero, 1f            # delay slot, check hw3 interrupt
 104          andi   a0, s0, CAUSEF_IP5
 105 #endif
 106
 107         /* Wheee, combined hardware level zero interrupt. */
 108 #if defined(CONFIG_MIPS_ATLAS)
 109         jal     atlas_hw0_irqdispatch
 110 #elif defined(CONFIG_MIPS_MALTA)
 111         jal     malta_hw0_irqdispatch
 112 #elif defined(CONFIG_MIPS_SEAD)
 113         jal     sead_hw0_irqdispatch
 114 #else
 115 #error "MIPS board not supported\n"
 116 #endif
 117          move   a0, sp                  # delay slot
 118
 119         j       ret_from_irq
 120          nop                            # delay slot
 121
 122 1:
 123 #if defined(CONFIG_MIPS_SEAD)
 124         beq     a0, zero, 1f
 125          andi   a0, s0, CAUSEF_IP5      # delay slot, check hw3 interrupt
 126         jal     sead_hw1_irqdispatch
 127          move   a0, sp                  # delay slot
 128         j       ret_from_irq
 129          nop                            # delay slot
 130 1:
 131 #endif
 132 #if defined(CONFIG_MIPS_MALTA)
 133         beq     a0, zero, 1f            # check hw3 (coreHI) interrupt
 134          nop
 135         jal     corehi_irqdispatch
 136          move   a0, sp
 137         j       ret_from_irq
 138          nop
 139 1:
 140 #endif
 141         /*
 142          * Here by mistake?  This is possible, what can happen is that by the
 143          * time we take the exception the IRQ pin goes low, so just leave if
 144          * this is the case.
 145          */
 146         move    a1,s0
 147         PRINT("Got interrupt: c0_cause = %08x\n")
 148         mfc0    a1, CP0_EPC
 149         PRINT("c0_epc = %08x\n")
 150
 151         j       ret_from_irq
 152          nop
 153         END(mipsIRQ)