arch/mips/mips-boards/generic/time.c

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
   4  *
   5  *  This program is free software; you can distribute it and/or modify it
   6  *  under the terms of the GNU General Public License (Version 2) as
   7  *  published by the Free Software Foundation.
   8  *
   9  *  This program is distributed in the hope it will be useful, but WITHOUT
  10  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  *  for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License along
  15  *  with this program; if not, write to the Free Software Foundation, Inc.,
  16  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17  *
  18  * Setting up the clock on the MIPS boards.
  19  */
  20
  21 #include <linux/types.h>
  22 #include <linux/init.h>
  23 #include <linux/kernel_stat.h>
  24 #include <linux/sched.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/time.h>
  28 #include <linux/timex.h>
  29 #include <linux/mc146818rtc.h>
  30
  31 #include <asm/mipsregs.h>
  32 #include <asm/mipsmtregs.h>
  33 #include <asm/hardirq.h>
  34 #include <asm/irq.h>
  35 #include <asm/div64.h>
  36 #include <asm/cpu.h>
  37 #include <asm/time.h>
  38 #include <asm/mc146818-time.h>
  39 #include <asm/msc01_ic.h>
  40
  41 #include <asm/mips-boards/generic.h>
  42 #include <asm/mips-boards/prom.h>
  43
  44 #ifdef CONFIG_MIPS_ATLAS
  45 #include <asm/mips-boards/atlasint.h>
  46 #endif
  47 #ifdef CONFIG_MIPS_MALTA
  48 #include <asm/mips-boards/maltaint.h>
  49 #endif
  50 #ifdef CONFIG_MIPS_SEAD
  51 #include <asm/mips-boards/seadint.h>
  52 #endif
  53
  54 unsigned long cpu_khz;
  55
  56 static int mips_cpu_timer_irq;
  57 extern int cp0_perfcount_irq;
  58 extern void smtc_timer_broadcast(int);
  59
  60 static void mips_timer_dispatch(void)
  61 {
  62         do_IRQ(mips_cpu_timer_irq);
  63 }
  64
  65 static void mips_perf_dispatch(void)
  66 {
  67         do_IRQ(cp0_perfcount_irq);
  68 }
  69
  70 /*
  71  * Redeclare until I get around mopping the timer code insanity on MIPS.
  72  */
  73 extern int null_perf_irq(void);
  74
  75 extern int (*perf_irq)(void);
  76
  77 /*
  78  * Possibly handle a performance counter interrupt.
  79  * Return true if the timer interrupt should not be checked
  80  */
  81 static inline int handle_perf_irq (int r2)
  82 {
  83         /*
  84          * The performance counter overflow interrupt may be shared with the
  85          * timer interrupt (cp0_perfcount_irq < 0). If it is and a
  86          * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
  87          * and we can't reliably determine if a counter interrupt has also
  88          * happened (!r2) then don't check for a timer interrupt.
  89          */
  90         return (cp0_perfcount_irq < 0) &&
  91                 perf_irq() == IRQ_HANDLED &&
  92                 !r2;
  93 }
  94
  95 irqreturn_t mips_timer_interrupt(int irq, void *dev_id)
  96 {
  97         int cpu = smp_processor_id();
  98
  99 #ifdef CONFIG_MIPS_MT_SMTC
 100         /*
 101          *  In an SMTC system, one Count/Compare set exists per VPE.
 102          *  Which TC within a VPE gets the interrupt is essentially
 103          *  random - we only know that it shouldn't be one with
 104          *  IXMT set. Whichever TC gets the interrupt needs to
 105          *  send special interprocessor interrupts to the other
 106          *  TCs to make sure that they schedule, etc.
 107          *
 108          *  That code is specific to the SMTC kernel, not to
 109          *  the a particular platform, so it's invoked from
 110          *  the general MIPS timer_interrupt routine.
 111          */
 112
 113         /*
 114          * We could be here due to timer interrupt,
 115          * perf counter overflow, or both.
 116          */
 117         (void) handle_perf_irq(1);
 118
 119         if (read_c0_cause() & (1 << 30)) {
 120                 /*
 121                  * There are things we only want to do once per tick
 122                  * in an "MP" system.   One TC of each VPE will take
 123                  * the actual timer interrupt.  The others will get
 124                  * timer broadcast IPIs. We use whoever it is that takes
 125                  * the tick on VPE 0 to run the full timer_interrupt().
 126                  */
 127                 if (cpu_data[cpu].vpe_id == 0) {
 128                         timer_interrupt(irq, NULL);
 129                 } else {
 130                         write_c0_compare(read_c0_count() +
 131                                          (mips_hpt_frequency/HZ));
 132                         local_timer_interrupt(irq, dev_id);
 133                 }
 134                 smtc_timer_broadcast(cpu_data[cpu].vpe_id);
 135         }
 136 #else /* CONFIG_MIPS_MT_SMTC */
 137         int r2 = cpu_has_mips_r2;
 138
 139         if (handle_perf_irq(r2))
 140                 goto out;
 141
 142         if (r2 && ((read_c0_cause() & (1 << 30)) == 0))
 143                 goto out;
 144
 145         if (cpu == 0) {
 146                 /*
 147                  * CPU 0 handles the global timer interrupt job and process
 148                  * accounting resets count/compare registers to trigger next
 149                  * timer int.
 150                  */
 151                 timer_interrupt(irq, NULL);
 152         } else {
 153                 /* Everyone else needs to reset the timer int here as
 154                    ll_local_timer_interrupt doesn't */
 155                 /*
 156                  * FIXME: need to cope with counter underflow.
 157                  * More support needs to be added to kernel/time for
 158                  * counter/timer interrupts on multiple CPU's
 159                  */
 160                 write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ));
 161
 162                 /*
 163                  * Other CPUs should do profiling and process accounting
 164                  */
 165                 local_timer_interrupt(irq, dev_id);
 166         }
 167 out:
 168 #endif /* CONFIG_MIPS_MT_SMTC */
 169         return IRQ_HANDLED;
 170 }
 171
 172 /*
 173  * Estimate CPU frequency.  Sets mips_hpt_frequency as a side-effect
 174  */
 175 static unsigned int __init estimate_cpu_frequency(void)
 176 {
 177         unsigned int prid = read_c0_prid() & 0xffff00;
 178         unsigned int count;
 179
 180 #if defined(CONFIG_MIPS_SEAD) || defined(CONFIG_MIPS_SIM)
 181         /*
 182          * The SEAD board doesn't have a real time clock, so we can't
 183          * really calculate the timer frequency
 184          * For now we hardwire the SEAD board frequency to 12MHz.
 185          */
 186
 187         if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
 188             (prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
 189                 count = 12000000;
 190         else
 191                 count = 6000000;
 192 #endif
 193 #if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
 194         unsigned long flags;
 195         unsigned int start;
 196
 197         local_irq_save(flags);
 198
 199         /* Start counter exactly on falling edge of update flag */
 200         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 201         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 202
 203         /* Start r4k counter. */
 204         start = read_c0_count();
 205
 206         /* Read counter exactly on falling edge of update flag */
 207         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 208         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 209
 210         count = read_c0_count() - start;
 211
 212         /* restore interrupts */
 213         local_irq_restore(flags);
 214 #endif
 215
 216         mips_hpt_frequency = count;
 217         if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
 218             (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
 219                 count *= 2;
 220
 221         count += 5000;    /* round */
 222         count -= count%10000;
 223
 224         return count;
 225 }
 226
 227 unsigned long __init mips_rtc_get_time(void)
 228 {
 229         return mc146818_get_cmos_time();
 230 }
 231
 232 void __init mips_time_init(void)
 233 {
 234         unsigned int est_freq;
 235
 236         /* Set Data mode - binary. */
 237         CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
 238
 239         est_freq = estimate_cpu_frequency ();
 240
 241         printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
 242                (est_freq%1000000)*100/1000000);
 243
 244         cpu_khz = est_freq / 1000;
 245
 246         mips_scroll_message();
 247 }
 248
 249 irqreturn_t mips_perf_interrupt(int irq, void *dev_id)
 250 {
 251         return perf_irq();
 252 }
 253
 254 static struct irqaction perf_irqaction = {
 255         .handler = mips_perf_interrupt,
 256         .flags = IRQF_DISABLED | IRQF_PERCPU,
 257         .name = "performance",
 258 };
 259
 260 void __init plat_perf_setup(struct irqaction *irq)
 261 {
 262         cp0_perfcount_irq = -1;
 263
 264 #ifdef MSC01E_INT_BASE
 265         if (cpu_has_veic) {
 266                 set_vi_handler (MSC01E_INT_PERFCTR, mips_perf_dispatch);
 267                 cp0_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
 268         } else
 269 #endif
 270         if (cp0_perfcount_irq >= 0) {
 271                 if (cpu_has_vint)
 272                         set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
 273 #ifdef CONFIG_MIPS_MT_SMTC
 274                 setup_irq_smtc(cp0_perfcount_irq, irq,
 275                                0x100 << cp0_perfcount_irq);
 276 #else
 277                 setup_irq(cp0_perfcount_irq, irq);
 278 #endif /* CONFIG_MIPS_MT_SMTC */
 279 #ifdef CONFIG_SMP
 280                 set_irq_handler(cp0_perfcount_irq, handle_percpu_irq);
 281 #endif
 282         }
 283 }
 284
 285 void __init plat_timer_setup(struct irqaction *irq)
 286 {
 287 #ifdef MSC01E_INT_BASE
 288         if (cpu_has_veic) {
 289                 set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch);
 290                 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
 291         }
 292         else
 293 #endif
 294         {
 295                 if (cpu_has_vint)
 296                         set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
 297                 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
 298         }
 299
 300         /* we are using the cpu counter for timer interrupts */
 301         irq->handler = mips_timer_interrupt;    /* we use our own handler */
 302 #ifdef CONFIG_MIPS_MT_SMTC
 303         setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << cp0_compare_irq);
 304 #else
 305         setup_irq(mips_cpu_timer_irq, irq);
 306 #endif /* CONFIG_MIPS_MT_SMTC */
 307 #ifdef CONFIG_SMP
 308         set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
 309 #endif
 310
 311         plat_perf_setup(&perf_irqaction);
 312 }