2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 #include <linux/init.h>
19 #include <linux/sched.h>
20 #include <linux/ioport.h>
21 #include <linux/pci.h>
22 #include <linux/tty.h>
25 #include <linux/mtd/partitions.h>
26 #include <linux/mtd/physmap.h>
27 #include <linux/mtd/mtd.h>
28 #include <linux/mtd/map.h>
32 #include <asm/bootinfo.h>
34 #include <asm/mips-boards/generic.h>
35 #include <asm/mips-boards/prom.h>
36 #include <asm/mips-boards/malta.h>
37 #include <asm/mips-boards/maltaint.h>
40 #include <asm/traps.h>
42 #include <linux/console.h>
45 extern void mips_reboot_setup(void);
46 extern void mips_time_init(void);
47 extern void mips_timer_setup(struct irqaction
*irq
);
48 extern unsigned long mips_rtc_get_time(void);
51 extern void kgdb_config(void);
54 struct resource standard_io_resources
[] = {
55 { .name
= "dma1", .start
= 0x00, .end
= 0x1f, .flags
= IORESOURCE_BUSY
},
56 { .name
= "timer", .start
= 0x40, .end
= 0x5f, .flags
= IORESOURCE_BUSY
},
57 { .name
= "keyboard", .start
= 0x60, .end
= 0x6f, .flags
= IORESOURCE_BUSY
},
58 { .name
= "dma page reg", .start
= 0x80, .end
= 0x8f, .flags
= IORESOURCE_BUSY
},
59 { .name
= "dma2", .start
= 0xc0, .end
= 0xdf, .flags
= IORESOURCE_BUSY
},
63 static struct mtd_partition malta_mtd_partitions
[] = {
68 .mask_flags
= MTD_WRITEABLE
76 .name
= "Board Config",
79 .mask_flags
= MTD_WRITEABLE
83 #define number_partitions (sizeof(malta_mtd_partitions)/sizeof(struct mtd_partition))
86 const char *get_system_type(void)
91 #ifdef CONFIG_BLK_DEV_FD
92 void __init
fd_activate(void)
95 * Activate Floppy Controller in the SMSC FDC37M817 Super I/O
97 * Done by YAMON 2.00 onwards
99 /* Entering config state. */
100 SMSC_WRITE(SMSC_CONFIG_ENTER
, SMSC_CONFIG_REG
);
102 /* Activate floppy controller. */
103 SMSC_WRITE(SMSC_CONFIG_DEVNUM
, SMSC_CONFIG_REG
);
104 SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY
, SMSC_DATA_REG
);
105 SMSC_WRITE(SMSC_CONFIG_ACTIVATE
, SMSC_CONFIG_REG
);
106 SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE
, SMSC_DATA_REG
);
108 /* Exit config state. */
109 SMSC_WRITE(SMSC_CONFIG_EXIT
, SMSC_CONFIG_REG
);
113 void __init
plat_mem_setup(void)
119 /* Request I/O space for devices used on the Malta board. */
120 for (i
= 0; i
< ARRAY_SIZE(standard_io_resources
); i
++)
121 request_resource(&ioport_resource
, standard_io_resources
+i
);
124 * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
132 if ((mips_revision_corid
== MIPS_REVISION_CORID_BONITO64
) ||
133 (mips_revision_corid
== MIPS_REVISION_CORID_CORE_20K
) ||
134 (mips_revision_corid
== MIPS_REVISION_CORID_CORE_EMUL_BON
)) {
137 argptr
= prom_getcmdline();
138 if (strstr(argptr
, "debug")) {
139 BONITO_BONGENCFG
|= BONITO_BONGENCFG_DEBUGMODE
;
140 printk ("Enabled Bonito debug mode\n");
143 BONITO_BONGENCFG
&= ~BONITO_BONGENCFG_DEBUGMODE
;
145 #ifdef CONFIG_DMA_COHERENT
146 if (BONITO_PCICACHECTRL
& BONITO_PCICACHECTRL_CPUCOH_PRES
) {
147 BONITO_PCICACHECTRL
|= BONITO_PCICACHECTRL_CPUCOH_EN
;
148 printk("Enabled Bonito CPU coherency\n");
150 argptr
= prom_getcmdline();
151 if (strstr(argptr
, "iobcuncached")) {
152 BONITO_PCICACHECTRL
&= ~BONITO_PCICACHECTRL_IOBCCOH_EN
;
153 BONITO_PCIMEMBASECFG
= BONITO_PCIMEMBASECFG
&
154 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED
|
155 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED
);
156 printk("Disabled Bonito IOBC coherency\n");
159 BONITO_PCICACHECTRL
|= BONITO_PCICACHECTRL_IOBCCOH_EN
;
160 BONITO_PCIMEMBASECFG
|=
161 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED
|
162 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED
);
163 printk("Disabled Bonito IOBC coherency\n");
167 panic("Hardware DMA cache coherency not supported");
171 #ifdef CONFIG_DMA_COHERENT
173 panic("Hardware DMA cache coherency not supported");
177 #ifdef CONFIG_BLK_DEV_IDE
178 /* Check PCI clock */
180 int jmpr
= (*((volatile unsigned int *)ioremap(MALTA_JMPRS_REG
, sizeof(unsigned int))) >> 2) & 0x07;
181 static const int pciclocks
[] __initdata
= {
182 33, 20, 25, 30, 12, 16, 37, 10
184 int pciclock
= pciclocks
[jmpr
];
185 char *argptr
= prom_getcmdline();
187 if (pciclock
!= 33 && !strstr (argptr
, "idebus=")) {
188 printk("WARNING: PCI clock is %dMHz, setting idebus\n", pciclock
);
189 argptr
+= strlen(argptr
);
190 sprintf (argptr
, " idebus=%d", pciclock
);
191 if (pciclock
< 20 || pciclock
> 66)
192 printk ("WARNING: IDE timing calculations will be incorrect\n");
196 #ifdef CONFIG_BLK_DEV_FD
200 #if defined(CONFIG_VGA_CONSOLE)
201 screen_info
= (struct screen_info
) {
202 0, 25, /* orig-x, orig-y */
204 0, /* orig-video-page */
205 0, /* orig-video-mode */
206 80, /* orig-video-cols */
207 0,0,0, /* ega_ax, ega_bx, ega_cx */
208 25, /* orig-video-lines */
209 VIDEO_TYPE_VGAC
, /* orig-video-isVGA */
210 16 /* orig-video-points */
217 * Support for MTD on Malta. Use the generic physmap driver
219 physmap_configure(0x1e000000, 0x400000, 4, NULL
);
220 physmap_set_partitions(malta_mtd_partitions
, number_partitions
);
225 board_time_init
= mips_time_init
;
226 board_timer_setup
= mips_timer_setup
;
227 rtc_mips_get_time
= mips_rtc_get_time
;