arch/mips/mips-boards/malta/malta_smtc.c

   1 /*
   2  * Malta Platform-specific hooks for SMP operation
   3  */
   4 #include <linux/irq.h>
   5 #include <linux/init.h>
   6
   7 #include <asm/mipsregs.h>
   8 #include <asm/mipsmtregs.h>
   9 #include <asm/smtc.h>
  10 #include <asm/smtc_ipi.h>
  11
  12 /* VPE/SMP Prototype implements platform interfaces directly */
  13
  14 /*
  15  * Cause the specified action to be performed on a targeted "CPU"
  16  */
  17
  18 void core_send_ipi(int cpu, unsigned int action)
  19 {
  20         /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */
  21         smtc_send_ipi(cpu, LINUX_SMP_IPI, action);
  22 }
  23
  24 /*
  25  * Platform "CPU" startup hook
  26  */
  27
  28 void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle)
  29 {
  30         smtc_boot_secondary(cpu, idle);
  31 }
  32
  33 /*
  34  * Post-config but pre-boot cleanup entry point
  35  */
  36
  37 void __cpuinit prom_init_secondary(void)
  38 {
  39         void smtc_init_secondary(void);
  40         int myvpe;
  41
  42         /* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */
  43         myvpe = read_c0_tcbind() & TCBIND_CURVPE;
  44         if (myvpe != 0) {
  45                 /* Ideally, this should be done only once per VPE, but... */
  46                 clear_c0_status(ST0_IM);
  47                 set_c0_status((0x100 << cp0_compare_irq)
  48                                 | (0x100 << MIPS_CPU_IPI_IRQ));
  49                 if (cp0_perfcount_irq >= 0)
  50                         set_c0_status(0x100 << cp0_perfcount_irq);
  51         }
  52
  53         smtc_init_secondary();
  54 }
  55
  56 /*
  57  * Platform SMP pre-initialization
  58  *
  59  * As noted above, we can assume a single CPU for now
  60  * but it may be multithreaded.
  61  */
  62
  63 void __cpuinit plat_smp_setup(void)
  64 {
  65         if (read_c0_config3() & (1<<2))
  66                 mipsmt_build_cpu_map(0);
  67 }
  68
  69 void __init plat_prepare_cpus(unsigned int max_cpus)
  70 {
  71         if (read_c0_config3() & (1<<2))
  72                 mipsmt_prepare_cpus();
  73 }
  74
  75 /*
  76  * SMP initialization finalization entry point
  77  */
  78
  79 void __cpuinit prom_smp_finish(void)
  80 {
  81         smtc_smp_finish();
  82 }
  83
  84 /*
  85  * Hook for after all CPUs are online
  86  */
  87
  88 void prom_cpus_done(void)
  89 {
  90 }
  91
  92 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
  93 /*
  94  * IRQ affinity hook
  95  */
  96
  97
  98 void plat_set_irq_affinity(unsigned int irq, cpumask_t affinity)
  99 {
 100         cpumask_t tmask = affinity;
 101         int cpu = 0;
 102         void smtc_set_irq_affinity(unsigned int irq, cpumask_t aff);
 103
 104         /*
 105          * On the legacy Malta development board, all I/O interrupts
 106          * are routed through the 8259 and combined in a single signal
 107          * to the CPU daughterboard, and on the CoreFPGA2/3 34K models,
 108          * that signal is brought to IP2 of both VPEs. To avoid racing
 109          * concurrent interrupt service events, IP2 is enabled only on
 110          * one VPE, by convention VPE0.  So long as no bits are ever
 111          * cleared in the affinity mask, there will never be any
 112          * interrupt forwarding.  But as soon as a program or operator
 113          * sets affinity for one of the related IRQs, we need to make
 114          * sure that we don't ever try to forward across the VPE boundry,
 115          * at least not until we engineer a system where the interrupt
 116          * _ack() or _end() function can somehow know that it corresponds
 117          * to an interrupt taken on another VPE, and perform the appropriate
 118          * restoration of Status.IM state using MFTR/MTTR instead of the
 119          * normal local behavior. We also ensure that no attempt will
 120          * be made to forward to an offline "CPU".
 121          */
 122
 123         for_each_cpu_mask(cpu, affinity) {
 124                 if ((cpu_data[cpu].vpe_id != 0) || !cpu_online(cpu))
 125                         cpu_clear(cpu, tmask);
 126         }
 127         irq_desc[irq].affinity = tmask;
 128
 129         if (cpus_empty(tmask))
 130                 /*
 131                  * We could restore a default mask here, but the
 132                  * runtime code can anyway deal with the null set
 133                  */
 134                 printk(KERN_WARNING
 135                         "IRQ affinity leaves no legal CPU for IRQ %d\n", irq);
 136
 137         /* Do any generic SMTC IRQ affinity setup */
 138         smtc_set_irq_affinity(irq, tmask);
 139 }
 140 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */