arch/mips/mm/cex-sb1.S

   1 /*
   2  * Copyright (C) 2001,2002,2003 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  */
  18 #include <linux/init.h>
  19
  20 #include <asm/asm.h>
  21 #include <asm/regdef.h>
  22 #include <asm/mipsregs.h>
  23 #include <asm/stackframe.h>
  24 #include <asm/cacheops.h>
  25 #include <asm/sibyte/board.h>
  26
  27 #define C0_ERRCTL     $26             /* CP0: Error info */
  28 #define C0_CERR_I     $27             /* CP0: Icache error */
  29 #define C0_CERR_D     $27,1           /* CP0: Dcache error */
  30
  31         /*
  32          * Based on SiByte sample software cache-err/cerr.S
  33          * CVS revision 1.8.  Only the 'unrecoverable' case
  34          * is changed.
  35          */
  36
  37         __INIT
  38
  39         .set    mips64
  40         .set    noreorder
  41         .set    noat
  42
  43         /*
  44          * sb1_cerr_vec: code to be copied to the Cache Error
  45          * Exception vector.  The code must be pushed out to memory
  46          * (either by copying to Kseg0 and Kseg1 both, or by flushing
  47          * the L1 and L2) since it is fetched as 0xa0000100.
  48          *
  49          * NOTE: Be sure this handler is at most 28 instructions long
  50          * since the final 16 bytes of the exception vector memory
  51          * (0x170-0x17f) are used to preserve k0, k1, and ra.
  52          */
  53
  54 LEAF(except_vec2_sb1)
  55         /*
  56          * If this error is recoverable, we need to exit the handler
  57          * without having dirtied any registers.  To do this,
  58          * save/restore k0 and k1 from low memory (Useg is direct
  59          * mapped while ERL=1). Note that we can't save to a
  60          * CPU-specific location without ruining a register in the
  61          * process.  This means we are vulnerable to data corruption
  62          * whenever the handler is reentered by a second CPU.
  63          */
  64         sd      k0,0x170($0)
  65         sd      k1,0x178($0)
  66
  67         /*
  68          * M_ERRCTL_RECOVERABLE is bit 31, which makes it easy to tell
  69          * if we can fast-path out of here for a h/w-recovered error.
  70          */
  71         mfc0    k1,C0_ERRCTL
  72         bgtz    k1,attempt_recovery
  73          sll    k0,k1,1
  74
  75 recovered_dcache:
  76         /*
  77          * Unlock CacheErr-D (which in turn unlocks CacheErr-DPA).
  78          * Ought to log the occurence of this recovered dcache error.
  79          */
  80         b       recovered
  81          mtc0   $0,C0_CERR_D
  82
  83 attempt_recovery:
  84         /*
  85          * k0 has C0_ERRCTL << 1, which puts 'DC' at bit 31.  Any
  86          * Dcache errors we can recover from will take more extensive
  87          * processing.  For now, they are considered "unrecoverable".
  88          * Note that 'DC' becoming set (outside of ERL mode) will
  89          * cause 'IC' to clear; so if there's an Icache error, we'll
  90          * only find out about it if we recover from this error and
  91          * continue executing.
  92          */
  93         bltz    k0,unrecoverable
  94          sll    k0,1
  95
  96         /*
  97          * k0 has C0_ERRCTL << 2, which puts 'IC' at bit 31.  If an
  98          * Icache error isn't indicated, I'm not sure why we got here.
  99          * Consider that case "unrecoverable" for now.
 100          */
 101         bgez    k0,unrecoverable
 102
 103 attempt_icache_recovery:
 104         /*
 105          * External icache errors are due to uncorrectable ECC errors
 106          * in the L2 cache or Memory Controller and cannot be
 107          * recovered here.
 108          */
 109          mfc0   k0,C0_CERR_I            /* delay slot */
 110         li      k1,1 << 26              /* ICACHE_EXTERNAL */
 111         and     k1,k0
 112         bnez    k1,unrecoverable
 113          andi   k0,0x1fe0
 114
 115         /*
 116          * Since the error is internal, the 'IDX' field from
 117          * CacheErr-I is valid and we can just invalidate all blocks
 118          * in that set.
 119          */
 120         cache   Index_Invalidate_I,(0<<13)(k0)
 121         cache   Index_Invalidate_I,(1<<13)(k0)
 122         cache   Index_Invalidate_I,(2<<13)(k0)
 123         cache   Index_Invalidate_I,(3<<13)(k0)
 124
 125         /* Ought to log this recovered icache error */
 126
 127 recovered:
 128         /* Restore the saved registers */
 129         ld      k0,0x170($0)
 130         ld      k1,0x178($0)
 131         eret
 132
 133 unrecoverable:
 134         /* Unrecoverable Icache or Dcache error; log it and/or fail */
 135         j       handle_vec2_sb1
 136          nop
 137
 138 END(except_vec2_sb1)
 139
 140         __FINIT
 141
 142         LEAF(handle_vec2_sb1)
 143         mfc0    k0,CP0_CONFIG
 144         li      k1,~CONF_CM_CMASK
 145         and     k0,k0,k1
 146         ori     k0,k0,CONF_CM_UNCACHED
 147         mtc0    k0,CP0_CONFIG
 148
 149         SSNOP
 150         SSNOP
 151         SSNOP
 152         SSNOP
 153         bnezl   $0, 1f
 154 1:
 155         mfc0    k0, CP0_STATUS
 156         sll     k0, k0, 3                       # check CU0 (kernel?)
 157         bltz    k0, 2f
 158          nop
 159
 160         /* Get a valid Kseg0 stack pointer.  Any task's stack pointer
 161          * will do, although if we ever want to resume execution we
 162          * better not have corrupted any state. */
 163         get_saved_sp
 164         move    sp, k1
 165
 166 2:
 167         j       sb1_cache_error
 168          nop
 169
 170         END(handle_vec2_sb1)