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git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - arch/mips/mm/tlb-r3k.c
2 * r2300.c: R2000 and R3000 specific mmu/cache code.
4 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
6 * with a lot of changes to make this thing work for R3000s
7 * Tx39XX R4k style caches added. HK
8 * Copyright (C) 1998, 1999, 2000 Harald Koerfgen
9 * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
10 * Copyright (C) 2002 Ralf Baechle
11 * Copyright (C) 2002 Maciej W. Rozycki
13 #include <linux/init.h>
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
19 #include <asm/pgtable.h>
20 #include <asm/mmu_context.h>
21 #include <asm/system.h>
22 #include <asm/isadep.h>
24 #include <asm/bootinfo.h>
29 extern void build_tlb_refill_handler(void);
31 /* CP0 hazard avoidance. */
33 __asm__ __volatile__( \
35 ".set noreorder\n\t" \
39 int r3k_have_wired_reg
; /* should be in cpu_data? */
42 void local_flush_tlb_all(void)
45 unsigned long old_ctx
;
52 local_irq_save(flags
);
53 old_ctx
= read_c0_entryhi() & ASID_MASK
;
55 entry
= r3k_have_wired_reg
? read_c0_wired() : 8;
56 for (; entry
< current_cpu_data
.tlbsize
; entry
++) {
57 write_c0_index(entry
<< 8);
58 write_c0_entryhi((entry
| 0x80000) << 12);
62 write_c0_entryhi(old_ctx
);
63 local_irq_restore(flags
);
66 void local_flush_tlb_mm(struct mm_struct
*mm
)
68 int cpu
= smp_processor_id();
70 if (cpu_context(cpu
, mm
) != 0) {
72 printk("[tlbmm<%lu>]", (unsigned long)cpu_context(cpu
, mm
));
74 drop_mmu_context(mm
, cpu
);
78 void local_flush_tlb_range(struct vm_area_struct
*vma
, unsigned long start
,
81 struct mm_struct
*mm
= vma
->vm_mm
;
82 int cpu
= smp_processor_id();
84 if (cpu_context(cpu
, mm
) != 0) {
89 printk("[tlbrange<%lu,0x%08lx,0x%08lx>]",
90 cpu_context(cpu
, mm
) & ASID_MASK
, start
, end
);
92 local_irq_save(flags
);
93 size
= (end
- start
+ (PAGE_SIZE
- 1)) >> PAGE_SHIFT
;
94 if (size
<= current_cpu_data
.tlbsize
) {
95 int oldpid
= read_c0_entryhi() & ASID_MASK
;
96 int newpid
= cpu_context(cpu
, mm
) & ASID_MASK
;
101 while (start
< end
) {
104 write_c0_entryhi(start
| newpid
);
105 start
+= PAGE_SIZE
; /* BARRIER */
107 idx
= read_c0_index();
108 write_c0_entrylo0(0);
109 write_c0_entryhi(KSEG0
);
110 if (idx
< 0) /* BARRIER */
114 write_c0_entryhi(oldpid
);
116 drop_mmu_context(mm
, cpu
);
118 local_irq_restore(flags
);
122 void local_flush_tlb_kernel_range(unsigned long start
, unsigned long end
)
128 printk("[tlbrange<%lu,0x%08lx,0x%08lx>]", start
, end
);
130 local_irq_save(flags
);
131 size
= (end
- start
+ (PAGE_SIZE
- 1)) >> PAGE_SHIFT
;
132 if (size
<= current_cpu_data
.tlbsize
) {
133 int pid
= read_c0_entryhi();
136 end
+= PAGE_SIZE
- 1;
139 while (start
< end
) {
142 write_c0_entryhi(start
);
143 start
+= PAGE_SIZE
; /* BARRIER */
145 idx
= read_c0_index();
146 write_c0_entrylo0(0);
147 write_c0_entryhi(KSEG0
);
148 if (idx
< 0) /* BARRIER */
152 write_c0_entryhi(pid
);
154 local_flush_tlb_all();
156 local_irq_restore(flags
);
159 void local_flush_tlb_page(struct vm_area_struct
*vma
, unsigned long page
)
161 int cpu
= smp_processor_id();
163 if (!vma
|| cpu_context(cpu
, vma
->vm_mm
) != 0) {
165 int oldpid
, newpid
, idx
;
168 printk("[tlbpage<%lu,0x%08lx>]", cpu_context(cpu
, vma
->vm_mm
), page
);
170 newpid
= cpu_context(cpu
, vma
->vm_mm
) & ASID_MASK
;
172 local_irq_save(flags
);
173 oldpid
= read_c0_entryhi() & ASID_MASK
;
174 write_c0_entryhi(page
| newpid
);
177 idx
= read_c0_index();
178 write_c0_entrylo0(0);
179 write_c0_entryhi(KSEG0
);
180 if (idx
< 0) /* BARRIER */
185 write_c0_entryhi(oldpid
);
186 local_irq_restore(flags
);
190 void __update_tlb(struct vm_area_struct
*vma
, unsigned long address
, pte_t pte
)
196 * Handle debugger faulting in for debugee.
198 if (current
->active_mm
!= vma
->vm_mm
)
201 pid
= read_c0_entryhi() & ASID_MASK
;
204 if ((pid
!= (cpu_context(cpu
, vma
->vm_mm
) & ASID_MASK
)) || (cpu_context(cpu
, vma
->vm_mm
) == 0)) {
205 printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%lu tlbpid=%d\n",
206 (cpu_context(cpu
, vma
->vm_mm
)), pid
);
210 local_irq_save(flags
);
211 address
&= PAGE_MASK
;
212 write_c0_entryhi(address
| pid
);
215 idx
= read_c0_index();
216 write_c0_entrylo0(pte_val(pte
));
217 write_c0_entryhi(address
| pid
);
218 if (idx
< 0) { /* BARRIER */
223 write_c0_entryhi(pid
);
224 local_irq_restore(flags
);
227 void __init
add_wired_entry(unsigned long entrylo0
, unsigned long entrylo1
,
228 unsigned long entryhi
, unsigned long pagemask
)
231 unsigned long old_ctx
;
232 static unsigned long wired
= 0;
234 if (r3k_have_wired_reg
) { /* TX39XX */
235 unsigned long old_pagemask
;
239 printk("[tlbwired<entry lo0 %8x, hi %8x\n, pagemask %8x>]\n",
240 entrylo0
, entryhi
, pagemask
);
243 local_irq_save(flags
);
244 /* Save old context and create impossible VPN2 value */
245 old_ctx
= read_c0_entryhi() & ASID_MASK
;
246 old_pagemask
= read_c0_pagemask();
248 write_c0_wired(w
+ 1);
249 if (read_c0_wired() != w
+ 1) {
250 printk("[tlbwired] No WIRED reg?\n");
253 write_c0_index(w
<< 8);
254 write_c0_pagemask(pagemask
);
255 write_c0_entryhi(entryhi
);
256 write_c0_entrylo0(entrylo0
);
260 write_c0_entryhi(old_ctx
);
261 write_c0_pagemask(old_pagemask
);
262 local_flush_tlb_all();
263 local_irq_restore(flags
);
265 } else if (wired
< 8) {
267 printk("[tlbwired<entry lo0 %8x, hi %8x\n>]\n",
271 local_irq_save(flags
);
272 old_ctx
= read_c0_entryhi() & ASID_MASK
;
273 write_c0_entrylo0(entrylo0
);
274 write_c0_entryhi(entryhi
);
275 write_c0_index(wired
);
276 wired
++; /* BARRIER */
278 write_c0_entryhi(old_ctx
);
279 local_flush_tlb_all();
280 local_irq_restore(flags
);
284 void __init
tlb_init(void)
286 local_flush_tlb_all();
288 build_tlb_refill_handler();