]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - arch/mips/mm/tlbex.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge remote-tracking branches 'asoc/topic/adsp', 'asoc/topic/ak4613', 'asoc/topic...
[mirror_ubuntu-bionic-kernel.git] / arch / mips / mm / tlbex.c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Synthesize TLB refill handlers at runtime.
7 *
8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
11 * Copyright (C) 2008, 2009 Cavium Networks, Inc.
12 * Copyright (C) 2011 MIPS Technologies, Inc.
13 *
14 * ... and the days got worse and worse and now you see
15 * I've gone completely out of my mind.
16 *
17 * They're coming to take me a away haha
18 * they're coming to take me a away hoho hihi haha
19 * to the funny farm where code is beautiful all the time ...
20 *
21 * (Condolences to Napoleon XIV)
22 */
23
24 #include <linux/bug.h>
25 #include <linux/export.h>
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/smp.h>
29 #include <linux/string.h>
30 #include <linux/cache.h>
31
32 #include <asm/cacheflush.h>
33 #include <asm/cpu-type.h>
34 #include <asm/pgtable.h>
35 #include <asm/war.h>
36 #include <asm/uasm.h>
37 #include <asm/setup.h>
38 #include <asm/tlbex.h>
39
40 static int mips_xpa_disabled;
41
42 static int __init xpa_disable(char *s)
43 {
44 mips_xpa_disabled = 1;
45
46 return 1;
47 }
48
49 __setup("noxpa", xpa_disable);
50
51 /*
52 * TLB load/store/modify handlers.
53 *
54 * Only the fastpath gets synthesized at runtime, the slowpath for
55 * do_page_fault remains normal asm.
56 */
57 extern void tlb_do_page_fault_0(void);
58 extern void tlb_do_page_fault_1(void);
59
60 struct work_registers {
61 int r1;
62 int r2;
63 int r3;
64 };
65
66 struct tlb_reg_save {
67 unsigned long a;
68 unsigned long b;
69 } ____cacheline_aligned_in_smp;
70
71 static struct tlb_reg_save handler_reg_save[NR_CPUS];
72
73 static inline int r45k_bvahwbug(void)
74 {
75 /* XXX: We should probe for the presence of this bug, but we don't. */
76 return 0;
77 }
78
79 static inline int r4k_250MHZhwbug(void)
80 {
81 /* XXX: We should probe for the presence of this bug, but we don't. */
82 return 0;
83 }
84
85 static inline int __maybe_unused bcm1250_m3_war(void)
86 {
87 return BCM1250_M3_WAR;
88 }
89
90 static inline int __maybe_unused r10000_llsc_war(void)
91 {
92 return R10000_LLSC_WAR;
93 }
94
95 static int use_bbit_insns(void)
96 {
97 switch (current_cpu_type()) {
98 case CPU_CAVIUM_OCTEON:
99 case CPU_CAVIUM_OCTEON_PLUS:
100 case CPU_CAVIUM_OCTEON2:
101 case CPU_CAVIUM_OCTEON3:
102 return 1;
103 default:
104 return 0;
105 }
106 }
107
108 static int use_lwx_insns(void)
109 {
110 switch (current_cpu_type()) {
111 case CPU_CAVIUM_OCTEON2:
112 case CPU_CAVIUM_OCTEON3:
113 return 1;
114 default:
115 return 0;
116 }
117 }
118 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
119 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
120 static bool scratchpad_available(void)
121 {
122 return true;
123 }
124 static int scratchpad_offset(int i)
125 {
126 /*
127 * CVMSEG starts at address -32768 and extends for
128 * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines.
129 */
130 i += 1; /* Kernel use starts at the top and works down. */
131 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768;
132 }
133 #else
134 static bool scratchpad_available(void)
135 {
136 return false;
137 }
138 static int scratchpad_offset(int i)
139 {
140 BUG();
141 /* Really unreachable, but evidently some GCC want this. */
142 return 0;
143 }
144 #endif
145 /*
146 * Found by experiment: At least some revisions of the 4kc throw under
147 * some circumstances a machine check exception, triggered by invalid
148 * values in the index register. Delaying the tlbp instruction until
149 * after the next branch, plus adding an additional nop in front of
150 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
151 * why; it's not an issue caused by the core RTL.
152 *
153 */
154 static int m4kc_tlbp_war(void)
155 {
156 return (current_cpu_data.processor_id & 0xffff00) ==
157 (PRID_COMP_MIPS | PRID_IMP_4KC);
158 }
159
160 /* Handle labels (which must be positive integers). */
161 enum label_id {
162 label_second_part = 1,
163 label_leave,
164 label_vmalloc,
165 label_vmalloc_done,
166 label_tlbw_hazard_0,
167 label_split = label_tlbw_hazard_0 + 8,
168 label_tlbl_goaround1,
169 label_tlbl_goaround2,
170 label_nopage_tlbl,
171 label_nopage_tlbs,
172 label_nopage_tlbm,
173 label_smp_pgtable_change,
174 label_r3000_write_probe_fail,
175 label_large_segbits_fault,
176 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
177 label_tlb_huge_update,
178 #endif
179 };
180
181 UASM_L_LA(_second_part)
182 UASM_L_LA(_leave)
183 UASM_L_LA(_vmalloc)
184 UASM_L_LA(_vmalloc_done)
185 /* _tlbw_hazard_x is handled differently. */
186 UASM_L_LA(_split)
187 UASM_L_LA(_tlbl_goaround1)
188 UASM_L_LA(_tlbl_goaround2)
189 UASM_L_LA(_nopage_tlbl)
190 UASM_L_LA(_nopage_tlbs)
191 UASM_L_LA(_nopage_tlbm)
192 UASM_L_LA(_smp_pgtable_change)
193 UASM_L_LA(_r3000_write_probe_fail)
194 UASM_L_LA(_large_segbits_fault)
195 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
196 UASM_L_LA(_tlb_huge_update)
197 #endif
198
199 static int hazard_instance;
200
201 static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance)
202 {
203 switch (instance) {
204 case 0 ... 7:
205 uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance);
206 return;
207 default:
208 BUG();
209 }
210 }
211
212 static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance)
213 {
214 switch (instance) {
215 case 0 ... 7:
216 uasm_build_label(l, *p, label_tlbw_hazard_0 + instance);
217 break;
218 default:
219 BUG();
220 }
221 }
222
223 /*
224 * pgtable bits are assigned dynamically depending on processor feature
225 * and statically based on kernel configuration. This spits out the actual
226 * values the kernel is using. Required to make sense from disassembled
227 * TLB exception handlers.
228 */
229 static void output_pgtable_bits_defines(void)
230 {
231 #define pr_define(fmt, ...) \
232 pr_debug("#define " fmt, ##__VA_ARGS__)
233
234 pr_debug("#include <asm/asm.h>\n");
235 pr_debug("#include <asm/regdef.h>\n");
236 pr_debug("\n");
237
238 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT);
239 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT);
240 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT);
241 pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT);
242 pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT);
243 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
244 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT);
245 #endif
246 #ifdef _PAGE_NO_EXEC_SHIFT
247 if (cpu_has_rixi)
248 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT);
249 #endif
250 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT);
251 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT);
252 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT);
253 pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT);
254 pr_debug("\n");
255 }
256
257 static inline void dump_handler(const char *symbol, const u32 *handler, int count)
258 {
259 int i;
260
261 pr_debug("LEAF(%s)\n", symbol);
262
263 pr_debug("\t.set push\n");
264 pr_debug("\t.set noreorder\n");
265
266 for (i = 0; i < count; i++)
267 pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]);
268
269 pr_debug("\t.set\tpop\n");
270
271 pr_debug("\tEND(%s)\n", symbol);
272 }
273
274 /* The only general purpose registers allowed in TLB handlers. */
275 #define K0 26
276 #define K1 27
277
278 /* Some CP0 registers */
279 #define C0_INDEX 0, 0
280 #define C0_ENTRYLO0 2, 0
281 #define C0_TCBIND 2, 2
282 #define C0_ENTRYLO1 3, 0
283 #define C0_CONTEXT 4, 0
284 #define C0_PAGEMASK 5, 0
285 #define C0_PWBASE 5, 5
286 #define C0_PWFIELD 5, 6
287 #define C0_PWSIZE 5, 7
288 #define C0_PWCTL 6, 6
289 #define C0_BADVADDR 8, 0
290 #define C0_PGD 9, 7
291 #define C0_ENTRYHI 10, 0
292 #define C0_EPC 14, 0
293 #define C0_XCONTEXT 20, 0
294
295 #ifdef CONFIG_64BIT
296 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
297 #else
298 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT)
299 #endif
300
301 /* The worst case length of the handler is around 18 instructions for
302 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
303 * Maximum space available is 32 instructions for R3000 and 64
304 * instructions for R4000.
305 *
306 * We deliberately chose a buffer size of 128, so we won't scribble
307 * over anything important on overflow before we panic.
308 */
309 static u32 tlb_handler[128];
310
311 /* simply assume worst case size for labels and relocs */
312 static struct uasm_label labels[128];
313 static struct uasm_reloc relocs[128];
314
315 static int check_for_high_segbits;
316 static bool fill_includes_sw_bits;
317
318 static unsigned int kscratch_used_mask;
319
320 static inline int __maybe_unused c0_kscratch(void)
321 {
322 switch (current_cpu_type()) {
323 case CPU_XLP:
324 case CPU_XLR:
325 return 22;
326 default:
327 return 31;
328 }
329 }
330
331 static int allocate_kscratch(void)
332 {
333 int r;
334 unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask;
335
336 r = ffs(a);
337
338 if (r == 0)
339 return -1;
340
341 r--; /* make it zero based */
342
343 kscratch_used_mask |= (1 << r);
344
345 return r;
346 }
347
348 static int scratch_reg;
349 int pgd_reg;
350 EXPORT_SYMBOL_GPL(pgd_reg);
351 enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch};
352
353 static struct work_registers build_get_work_registers(u32 **p)
354 {
355 struct work_registers r;
356
357 if (scratch_reg >= 0) {
358 /* Save in CPU local C0_KScratch? */
359 UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg);
360 r.r1 = K0;
361 r.r2 = K1;
362 r.r3 = 1;
363 return r;
364 }
365
366 if (num_possible_cpus() > 1) {
367 /* Get smp_processor_id */
368 UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG);
369 UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT);
370
371 /* handler_reg_save index in K0 */
372 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save)));
373
374 UASM_i_LA(p, K1, (long)&handler_reg_save);
375 UASM_i_ADDU(p, K0, K0, K1);
376 } else {
377 UASM_i_LA(p, K0, (long)&handler_reg_save);
378 }
379 /* K0 now points to save area, save $1 and $2 */
380 UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0);
381 UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0);
382
383 r.r1 = K1;
384 r.r2 = 1;
385 r.r3 = 2;
386 return r;
387 }
388
389 static void build_restore_work_registers(u32 **p)
390 {
391 if (scratch_reg >= 0) {
392 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
393 return;
394 }
395 /* K0 already points to save area, restore $1 and $2 */
396 UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0);
397 UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0);
398 }
399
400 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
401
402 /*
403 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
404 * we cannot do r3000 under these circumstances.
405 *
406 * Declare pgd_current here instead of including mmu_context.h to avoid type
407 * conflicts for tlbmiss_handler_setup_pgd
408 */
409 extern unsigned long pgd_current[];
410
411 /*
412 * The R3000 TLB handler is simple.
413 */
414 static void build_r3000_tlb_refill_handler(void)
415 {
416 long pgdc = (long)pgd_current;
417 u32 *p;
418
419 memset(tlb_handler, 0, sizeof(tlb_handler));
420 p = tlb_handler;
421
422 uasm_i_mfc0(&p, K0, C0_BADVADDR);
423 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */
424 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1);
425 uasm_i_srl(&p, K0, K0, 22); /* load delay */
426 uasm_i_sll(&p, K0, K0, 2);
427 uasm_i_addu(&p, K1, K1, K0);
428 uasm_i_mfc0(&p, K0, C0_CONTEXT);
429 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */
430 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */
431 uasm_i_addu(&p, K1, K1, K0);
432 uasm_i_lw(&p, K0, 0, K1);
433 uasm_i_nop(&p); /* load delay */
434 uasm_i_mtc0(&p, K0, C0_ENTRYLO0);
435 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
436 uasm_i_tlbwr(&p); /* cp0 delay */
437 uasm_i_jr(&p, K1);
438 uasm_i_rfe(&p); /* branch delay */
439
440 if (p > tlb_handler + 32)
441 panic("TLB refill handler space exceeded");
442
443 pr_debug("Wrote TLB refill handler (%u instructions).\n",
444 (unsigned int)(p - tlb_handler));
445
446 memcpy((void *)ebase, tlb_handler, 0x80);
447 local_flush_icache_range(ebase, ebase + 0x80);
448
449 dump_handler("r3000_tlb_refill", (u32 *)ebase, 32);
450 }
451 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
452
453 /*
454 * The R4000 TLB handler is much more complicated. We have two
455 * consecutive handler areas with 32 instructions space each.
456 * Since they aren't used at the same time, we can overflow in the
457 * other one.To keep things simple, we first assume linear space,
458 * then we relocate it to the final handler layout as needed.
459 */
460 static u32 final_handler[64];
461
462 /*
463 * Hazards
464 *
465 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
466 * 2. A timing hazard exists for the TLBP instruction.
467 *
468 * stalling_instruction
469 * TLBP
470 *
471 * The JTLB is being read for the TLBP throughout the stall generated by the
472 * previous instruction. This is not really correct as the stalling instruction
473 * can modify the address used to access the JTLB. The failure symptom is that
474 * the TLBP instruction will use an address created for the stalling instruction
475 * and not the address held in C0_ENHI and thus report the wrong results.
476 *
477 * The software work-around is to not allow the instruction preceding the TLBP
478 * to stall - make it an NOP or some other instruction guaranteed not to stall.
479 *
480 * Errata 2 will not be fixed. This errata is also on the R5000.
481 *
482 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
483 */
484 static void __maybe_unused build_tlb_probe_entry(u32 **p)
485 {
486 switch (current_cpu_type()) {
487 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */
488 case CPU_R4600:
489 case CPU_R4700:
490 case CPU_R5000:
491 case CPU_NEVADA:
492 uasm_i_nop(p);
493 uasm_i_tlbp(p);
494 break;
495
496 default:
497 uasm_i_tlbp(p);
498 break;
499 }
500 }
501
502 void build_tlb_write_entry(u32 **p, struct uasm_label **l,
503 struct uasm_reloc **r,
504 enum tlb_write_entry wmode)
505 {
506 void(*tlbw)(u32 **) = NULL;
507
508 switch (wmode) {
509 case tlb_random: tlbw = uasm_i_tlbwr; break;
510 case tlb_indexed: tlbw = uasm_i_tlbwi; break;
511 }
512
513 if (cpu_has_mips_r2_r6) {
514 if (cpu_has_mips_r2_exec_hazard)
515 uasm_i_ehb(p);
516 tlbw(p);
517 return;
518 }
519
520 switch (current_cpu_type()) {
521 case CPU_R4000PC:
522 case CPU_R4000SC:
523 case CPU_R4000MC:
524 case CPU_R4400PC:
525 case CPU_R4400SC:
526 case CPU_R4400MC:
527 /*
528 * This branch uses up a mtc0 hazard nop slot and saves
529 * two nops after the tlbw instruction.
530 */
531 uasm_bgezl_hazard(p, r, hazard_instance);
532 tlbw(p);
533 uasm_bgezl_label(l, p, hazard_instance);
534 hazard_instance++;
535 uasm_i_nop(p);
536 break;
537
538 case CPU_R4600:
539 case CPU_R4700:
540 uasm_i_nop(p);
541 tlbw(p);
542 uasm_i_nop(p);
543 break;
544
545 case CPU_R5000:
546 case CPU_NEVADA:
547 uasm_i_nop(p); /* QED specifies 2 nops hazard */
548 uasm_i_nop(p); /* QED specifies 2 nops hazard */
549 tlbw(p);
550 break;
551
552 case CPU_R4300:
553 case CPU_5KC:
554 case CPU_TX49XX:
555 case CPU_PR4450:
556 case CPU_XLR:
557 uasm_i_nop(p);
558 tlbw(p);
559 break;
560
561 case CPU_R10000:
562 case CPU_R12000:
563 case CPU_R14000:
564 case CPU_R16000:
565 case CPU_4KC:
566 case CPU_4KEC:
567 case CPU_M14KC:
568 case CPU_M14KEC:
569 case CPU_SB1:
570 case CPU_SB1A:
571 case CPU_4KSC:
572 case CPU_20KC:
573 case CPU_25KF:
574 case CPU_BMIPS32:
575 case CPU_BMIPS3300:
576 case CPU_BMIPS4350:
577 case CPU_BMIPS4380:
578 case CPU_BMIPS5000:
579 case CPU_LOONGSON2:
580 case CPU_LOONGSON3:
581 case CPU_R5500:
582 if (m4kc_tlbp_war())
583 uasm_i_nop(p);
584 case CPU_ALCHEMY:
585 tlbw(p);
586 break;
587
588 case CPU_RM7000:
589 uasm_i_nop(p);
590 uasm_i_nop(p);
591 uasm_i_nop(p);
592 uasm_i_nop(p);
593 tlbw(p);
594 break;
595
596 case CPU_VR4111:
597 case CPU_VR4121:
598 case CPU_VR4122:
599 case CPU_VR4181:
600 case CPU_VR4181A:
601 uasm_i_nop(p);
602 uasm_i_nop(p);
603 tlbw(p);
604 uasm_i_nop(p);
605 uasm_i_nop(p);
606 break;
607
608 case CPU_VR4131:
609 case CPU_VR4133:
610 case CPU_R5432:
611 uasm_i_nop(p);
612 uasm_i_nop(p);
613 tlbw(p);
614 break;
615
616 case CPU_JZRISC:
617 tlbw(p);
618 uasm_i_nop(p);
619 break;
620
621 default:
622 panic("No TLB refill handler yet (CPU type: %d)",
623 current_cpu_type());
624 break;
625 }
626 }
627 EXPORT_SYMBOL_GPL(build_tlb_write_entry);
628
629 static __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
630 unsigned int reg)
631 {
632 if (_PAGE_GLOBAL_SHIFT == 0) {
633 /* pte_t is already in EntryLo format */
634 return;
635 }
636
637 if (cpu_has_rixi && _PAGE_NO_EXEC) {
638 if (fill_includes_sw_bits) {
639 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL));
640 } else {
641 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC));
642 UASM_i_ROTR(p, reg, reg,
643 ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
644 }
645 } else {
646 #ifdef CONFIG_PHYS_ADDR_T_64BIT
647 uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL));
648 #else
649 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL));
650 #endif
651 }
652 }
653
654 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
655
656 static void build_restore_pagemask(u32 **p, struct uasm_reloc **r,
657 unsigned int tmp, enum label_id lid,
658 int restore_scratch)
659 {
660 if (restore_scratch) {
661 /* Reset default page size */
662 if (PM_DEFAULT_MASK >> 16) {
663 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
664 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
665 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
666 uasm_il_b(p, r, lid);
667 } else if (PM_DEFAULT_MASK) {
668 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
669 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
670 uasm_il_b(p, r, lid);
671 } else {
672 uasm_i_mtc0(p, 0, C0_PAGEMASK);
673 uasm_il_b(p, r, lid);
674 }
675 if (scratch_reg >= 0)
676 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
677 else
678 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
679 } else {
680 /* Reset default page size */
681 if (PM_DEFAULT_MASK >> 16) {
682 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
683 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
684 uasm_il_b(p, r, lid);
685 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
686 } else if (PM_DEFAULT_MASK) {
687 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
688 uasm_il_b(p, r, lid);
689 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
690 } else {
691 uasm_il_b(p, r, lid);
692 uasm_i_mtc0(p, 0, C0_PAGEMASK);
693 }
694 }
695 }
696
697 static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l,
698 struct uasm_reloc **r,
699 unsigned int tmp,
700 enum tlb_write_entry wmode,
701 int restore_scratch)
702 {
703 /* Set huge page tlb entry size */
704 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16);
705 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff);
706 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
707
708 build_tlb_write_entry(p, l, r, wmode);
709
710 build_restore_pagemask(p, r, tmp, label_leave, restore_scratch);
711 }
712
713 /*
714 * Check if Huge PTE is present, if so then jump to LABEL.
715 */
716 static void
717 build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp,
718 unsigned int pmd, int lid)
719 {
720 UASM_i_LW(p, tmp, 0, pmd);
721 if (use_bbit_insns()) {
722 uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid);
723 } else {
724 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE);
725 uasm_il_bnez(p, r, tmp, lid);
726 }
727 }
728
729 static void build_huge_update_entries(u32 **p, unsigned int pte,
730 unsigned int tmp)
731 {
732 int small_sequence;
733
734 /*
735 * A huge PTE describes an area the size of the
736 * configured huge page size. This is twice the
737 * of the large TLB entry size we intend to use.
738 * A TLB entry half the size of the configured
739 * huge page size is configured into entrylo0
740 * and entrylo1 to cover the contiguous huge PTE
741 * address space.
742 */
743 small_sequence = (HPAGE_SIZE >> 7) < 0x10000;
744
745 /* We can clobber tmp. It isn't used after this.*/
746 if (!small_sequence)
747 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16));
748
749 build_convert_pte_to_entrylo(p, pte);
750 UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */
751 /* convert to entrylo1 */
752 if (small_sequence)
753 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7);
754 else
755 UASM_i_ADDU(p, pte, pte, tmp);
756
757 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */
758 }
759
760 static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r,
761 struct uasm_label **l,
762 unsigned int pte,
763 unsigned int ptr,
764 unsigned int flush)
765 {
766 #ifdef CONFIG_SMP
767 UASM_i_SC(p, pte, 0, ptr);
768 uasm_il_beqz(p, r, pte, label_tlb_huge_update);
769 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */
770 #else
771 UASM_i_SW(p, pte, 0, ptr);
772 #endif
773 if (cpu_has_ftlb && flush) {
774 BUG_ON(!cpu_has_tlbinv);
775
776 UASM_i_MFC0(p, ptr, C0_ENTRYHI);
777 uasm_i_ori(p, ptr, ptr, MIPS_ENTRYHI_EHINV);
778 UASM_i_MTC0(p, ptr, C0_ENTRYHI);
779 build_tlb_write_entry(p, l, r, tlb_indexed);
780
781 uasm_i_xori(p, ptr, ptr, MIPS_ENTRYHI_EHINV);
782 UASM_i_MTC0(p, ptr, C0_ENTRYHI);
783 build_huge_update_entries(p, pte, ptr);
784 build_huge_tlb_write_entry(p, l, r, pte, tlb_random, 0);
785
786 return;
787 }
788
789 build_huge_update_entries(p, pte, ptr);
790 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0);
791 }
792 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
793
794 #ifdef CONFIG_64BIT
795 /*
796 * TMP and PTR are scratch.
797 * TMP will be clobbered, PTR will hold the pmd entry.
798 */
799 void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
800 unsigned int tmp, unsigned int ptr)
801 {
802 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
803 long pgdc = (long)pgd_current;
804 #endif
805 /*
806 * The vmalloc handling is not in the hotpath.
807 */
808 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
809
810 if (check_for_high_segbits) {
811 /*
812 * The kernel currently implicitely assumes that the
813 * MIPS SEGBITS parameter for the processor is
814 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never
815 * allocate virtual addresses outside the maximum
816 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But
817 * that doesn't prevent user code from accessing the
818 * higher xuseg addresses. Here, we make sure that
819 * everything but the lower xuseg addresses goes down
820 * the module_alloc/vmalloc path.
821 */
822 uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
823 uasm_il_bnez(p, r, ptr, label_vmalloc);
824 } else {
825 uasm_il_bltz(p, r, tmp, label_vmalloc);
826 }
827 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
828
829 if (pgd_reg != -1) {
830 /* pgd is in pgd_reg */
831 if (cpu_has_ldpte)
832 UASM_i_MFC0(p, ptr, C0_PWBASE);
833 else
834 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
835 } else {
836 #if defined(CONFIG_MIPS_PGD_C0_CONTEXT)
837 /*
838 * &pgd << 11 stored in CONTEXT [23..63].
839 */
840 UASM_i_MFC0(p, ptr, C0_CONTEXT);
841
842 /* Clear lower 23 bits of context. */
843 uasm_i_dins(p, ptr, 0, 0, 23);
844
845 /* 1 0 1 0 1 << 6 xkphys cached */
846 uasm_i_ori(p, ptr, ptr, 0x540);
847 uasm_i_drotr(p, ptr, ptr, 11);
848 #elif defined(CONFIG_SMP)
849 UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG);
850 uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
851 UASM_i_LA_mostly(p, tmp, pgdc);
852 uasm_i_daddu(p, ptr, ptr, tmp);
853 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
854 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
855 #else
856 UASM_i_LA_mostly(p, ptr, pgdc);
857 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
858 #endif
859 }
860
861 uasm_l_vmalloc_done(l, *p);
862
863 /* get pgd offset in bytes */
864 uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3);
865
866 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
867 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
868 #ifndef __PAGETABLE_PMD_FOLDED
869 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
870 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */
871 uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
872 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
873 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
874 #endif
875 }
876 EXPORT_SYMBOL_GPL(build_get_pmde64);
877
878 /*
879 * BVADDR is the faulting address, PTR is scratch.
880 * PTR will hold the pgd for vmalloc.
881 */
882 static void
883 build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
884 unsigned int bvaddr, unsigned int ptr,
885 enum vmalloc64_mode mode)
886 {
887 long swpd = (long)swapper_pg_dir;
888 int single_insn_swpd;
889 int did_vmalloc_branch = 0;
890
891 single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd);
892
893 uasm_l_vmalloc(l, *p);
894
895 if (mode != not_refill && check_for_high_segbits) {
896 if (single_insn_swpd) {
897 uasm_il_bltz(p, r, bvaddr, label_vmalloc_done);
898 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
899 did_vmalloc_branch = 1;
900 /* fall through */
901 } else {
902 uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault);
903 }
904 }
905 if (!did_vmalloc_branch) {
906 if (single_insn_swpd) {
907 uasm_il_b(p, r, label_vmalloc_done);
908 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
909 } else {
910 UASM_i_LA_mostly(p, ptr, swpd);
911 uasm_il_b(p, r, label_vmalloc_done);
912 if (uasm_in_compat_space_p(swpd))
913 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd));
914 else
915 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd));
916 }
917 }
918 if (mode != not_refill && check_for_high_segbits) {
919 uasm_l_large_segbits_fault(l, *p);
920 /*
921 * We get here if we are an xsseg address, or if we are
922 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary.
923 *
924 * Ignoring xsseg (assume disabled so would generate
925 * (address errors?), the only remaining possibility
926 * is the upper xuseg addresses. On processors with
927 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these
928 * addresses would have taken an address error. We try
929 * to mimic that here by taking a load/istream page
930 * fault.
931 */
932 UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0);
933 uasm_i_jr(p, ptr);
934
935 if (mode == refill_scratch) {
936 if (scratch_reg >= 0)
937 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
938 else
939 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
940 } else {
941 uasm_i_nop(p);
942 }
943 }
944 }
945
946 #else /* !CONFIG_64BIT */
947
948 /*
949 * TMP and PTR are scratch.
950 * TMP will be clobbered, PTR will hold the pgd entry.
951 */
952 void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
953 {
954 if (pgd_reg != -1) {
955 /* pgd is in pgd_reg */
956 uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg);
957 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
958 } else {
959 long pgdc = (long)pgd_current;
960
961 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
962 #ifdef CONFIG_SMP
963 uasm_i_mfc0(p, ptr, SMP_CPUID_REG);
964 UASM_i_LA_mostly(p, tmp, pgdc);
965 uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
966 uasm_i_addu(p, ptr, tmp, ptr);
967 #else
968 UASM_i_LA_mostly(p, ptr, pgdc);
969 #endif
970 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
971 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
972 }
973 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
974 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
975 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
976 }
977 EXPORT_SYMBOL_GPL(build_get_pgde32);
978
979 #endif /* !CONFIG_64BIT */
980
981 static void build_adjust_context(u32 **p, unsigned int ctx)
982 {
983 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
984 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
985
986 switch (current_cpu_type()) {
987 case CPU_VR41XX:
988 case CPU_VR4111:
989 case CPU_VR4121:
990 case CPU_VR4122:
991 case CPU_VR4131:
992 case CPU_VR4181:
993 case CPU_VR4181A:
994 case CPU_VR4133:
995 shift += 2;
996 break;
997
998 default:
999 break;
1000 }
1001
1002 if (shift)
1003 UASM_i_SRL(p, ctx, ctx, shift);
1004 uasm_i_andi(p, ctx, ctx, mask);
1005 }
1006
1007 void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
1008 {
1009 /*
1010 * Bug workaround for the Nevada. It seems as if under certain
1011 * circumstances the move from cp0_context might produce a
1012 * bogus result when the mfc0 instruction and its consumer are
1013 * in a different cacheline or a load instruction, probably any
1014 * memory reference, is between them.
1015 */
1016 switch (current_cpu_type()) {
1017 case CPU_NEVADA:
1018 UASM_i_LW(p, ptr, 0, ptr);
1019 GET_CONTEXT(p, tmp); /* get context reg */
1020 break;
1021
1022 default:
1023 GET_CONTEXT(p, tmp); /* get context reg */
1024 UASM_i_LW(p, ptr, 0, ptr);
1025 break;
1026 }
1027
1028 build_adjust_context(p, tmp);
1029 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */
1030 }
1031 EXPORT_SYMBOL_GPL(build_get_ptep);
1032
1033 void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
1034 {
1035 int pte_off_even = 0;
1036 int pte_off_odd = sizeof(pte_t);
1037
1038 #if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_PHYS_ADDR_T_64BIT)
1039 /* The low 32 bits of EntryLo is stored in pte_high */
1040 pte_off_even += offsetof(pte_t, pte_high);
1041 pte_off_odd += offsetof(pte_t, pte_high);
1042 #endif
1043
1044 if (IS_ENABLED(CONFIG_XPA)) {
1045 uasm_i_lw(p, tmp, pte_off_even, ptep); /* even pte */
1046 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
1047 UASM_i_MTC0(p, tmp, C0_ENTRYLO0);
1048
1049 if (cpu_has_xpa && !mips_xpa_disabled) {
1050 uasm_i_lw(p, tmp, 0, ptep);
1051 uasm_i_ext(p, tmp, tmp, 0, 24);
1052 uasm_i_mthc0(p, tmp, C0_ENTRYLO0);
1053 }
1054
1055 uasm_i_lw(p, tmp, pte_off_odd, ptep); /* odd pte */
1056 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
1057 UASM_i_MTC0(p, tmp, C0_ENTRYLO1);
1058
1059 if (cpu_has_xpa && !mips_xpa_disabled) {
1060 uasm_i_lw(p, tmp, sizeof(pte_t), ptep);
1061 uasm_i_ext(p, tmp, tmp, 0, 24);
1062 uasm_i_mthc0(p, tmp, C0_ENTRYLO1);
1063 }
1064 return;
1065 }
1066
1067 UASM_i_LW(p, tmp, pte_off_even, ptep); /* get even pte */
1068 UASM_i_LW(p, ptep, pte_off_odd, ptep); /* get odd pte */
1069 if (r45k_bvahwbug())
1070 build_tlb_probe_entry(p);
1071 build_convert_pte_to_entrylo(p, tmp);
1072 if (r4k_250MHZhwbug())
1073 UASM_i_MTC0(p, 0, C0_ENTRYLO0);
1074 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1075 build_convert_pte_to_entrylo(p, ptep);
1076 if (r45k_bvahwbug())
1077 uasm_i_mfc0(p, tmp, C0_INDEX);
1078 if (r4k_250MHZhwbug())
1079 UASM_i_MTC0(p, 0, C0_ENTRYLO1);
1080 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1081 }
1082 EXPORT_SYMBOL_GPL(build_update_entries);
1083
1084 struct mips_huge_tlb_info {
1085 int huge_pte;
1086 int restore_scratch;
1087 bool need_reload_pte;
1088 };
1089
1090 static struct mips_huge_tlb_info
1091 build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
1092 struct uasm_reloc **r, unsigned int tmp,
1093 unsigned int ptr, int c0_scratch_reg)
1094 {
1095 struct mips_huge_tlb_info rv;
1096 unsigned int even, odd;
1097 int vmalloc_branch_delay_filled = 0;
1098 const int scratch = 1; /* Our extra working register */
1099
1100 rv.huge_pte = scratch;
1101 rv.restore_scratch = 0;
1102 rv.need_reload_pte = false;
1103
1104 if (check_for_high_segbits) {
1105 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1106
1107 if (pgd_reg != -1)
1108 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
1109 else
1110 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1111
1112 if (c0_scratch_reg >= 0)
1113 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1114 else
1115 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1116
1117 uasm_i_dsrl_safe(p, scratch, tmp,
1118 PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
1119 uasm_il_bnez(p, r, scratch, label_vmalloc);
1120
1121 if (pgd_reg == -1) {
1122 vmalloc_branch_delay_filled = 1;
1123 /* Clear lower 23 bits of context. */
1124 uasm_i_dins(p, ptr, 0, 0, 23);
1125 }
1126 } else {
1127 if (pgd_reg != -1)
1128 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
1129 else
1130 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1131
1132 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1133
1134 if (c0_scratch_reg >= 0)
1135 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1136 else
1137 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1138
1139 if (pgd_reg == -1)
1140 /* Clear lower 23 bits of context. */
1141 uasm_i_dins(p, ptr, 0, 0, 23);
1142
1143 uasm_il_bltz(p, r, tmp, label_vmalloc);
1144 }
1145
1146 if (pgd_reg == -1) {
1147 vmalloc_branch_delay_filled = 1;
1148 /* 1 0 1 0 1 << 6 xkphys cached */
1149 uasm_i_ori(p, ptr, ptr, 0x540);
1150 uasm_i_drotr(p, ptr, ptr, 11);
1151 }
1152
1153 #ifdef __PAGETABLE_PMD_FOLDED
1154 #define LOC_PTEP scratch
1155 #else
1156 #define LOC_PTEP ptr
1157 #endif
1158
1159 if (!vmalloc_branch_delay_filled)
1160 /* get pgd offset in bytes */
1161 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1162
1163 uasm_l_vmalloc_done(l, *p);
1164
1165 /*
1166 * tmp ptr
1167 * fall-through case = badvaddr *pgd_current
1168 * vmalloc case = badvaddr swapper_pg_dir
1169 */
1170
1171 if (vmalloc_branch_delay_filled)
1172 /* get pgd offset in bytes */
1173 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1174
1175 #ifdef __PAGETABLE_PMD_FOLDED
1176 GET_CONTEXT(p, tmp); /* get context reg */
1177 #endif
1178 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3);
1179
1180 if (use_lwx_insns()) {
1181 UASM_i_LWX(p, LOC_PTEP, scratch, ptr);
1182 } else {
1183 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */
1184 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */
1185 }
1186
1187 #ifndef __PAGETABLE_PMD_FOLDED
1188 /* get pmd offset in bytes */
1189 uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3);
1190 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3);
1191 GET_CONTEXT(p, tmp); /* get context reg */
1192
1193 if (use_lwx_insns()) {
1194 UASM_i_LWX(p, scratch, scratch, ptr);
1195 } else {
1196 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */
1197 UASM_i_LW(p, scratch, 0, ptr);
1198 }
1199 #endif
1200 /* Adjust the context during the load latency. */
1201 build_adjust_context(p, tmp);
1202
1203 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1204 uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update);
1205 /*
1206 * The in the LWX case we don't want to do the load in the
1207 * delay slot. It cannot issue in the same cycle and may be
1208 * speculative and unneeded.
1209 */
1210 if (use_lwx_insns())
1211 uasm_i_nop(p);
1212 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
1213
1214
1215 /* build_update_entries */
1216 if (use_lwx_insns()) {
1217 even = ptr;
1218 odd = tmp;
1219 UASM_i_LWX(p, even, scratch, tmp);
1220 UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t));
1221 UASM_i_LWX(p, odd, scratch, tmp);
1222 } else {
1223 UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */
1224 even = tmp;
1225 odd = ptr;
1226 UASM_i_LW(p, even, 0, ptr); /* get even pte */
1227 UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */
1228 }
1229 if (cpu_has_rixi) {
1230 uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL));
1231 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1232 uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL));
1233 } else {
1234 uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL));
1235 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1236 uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL));
1237 }
1238 UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */
1239
1240 if (c0_scratch_reg >= 0) {
1241 UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1242 build_tlb_write_entry(p, l, r, tlb_random);
1243 uasm_l_leave(l, *p);
1244 rv.restore_scratch = 1;
1245 } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) {
1246 build_tlb_write_entry(p, l, r, tlb_random);
1247 uasm_l_leave(l, *p);
1248 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1249 } else {
1250 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1251 build_tlb_write_entry(p, l, r, tlb_random);
1252 uasm_l_leave(l, *p);
1253 rv.restore_scratch = 1;
1254 }
1255
1256 uasm_i_eret(p); /* return from trap */
1257
1258 return rv;
1259 }
1260
1261 /*
1262 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
1263 * because EXL == 0. If we wrap, we can also use the 32 instruction
1264 * slots before the XTLB refill exception handler which belong to the
1265 * unused TLB refill exception.
1266 */
1267 #define MIPS64_REFILL_INSNS 32
1268
1269 static void build_r4000_tlb_refill_handler(void)
1270 {
1271 u32 *p = tlb_handler;
1272 struct uasm_label *l = labels;
1273 struct uasm_reloc *r = relocs;
1274 u32 *f;
1275 unsigned int final_len;
1276 struct mips_huge_tlb_info htlb_info __maybe_unused;
1277 enum vmalloc64_mode vmalloc_mode __maybe_unused;
1278
1279 memset(tlb_handler, 0, sizeof(tlb_handler));
1280 memset(labels, 0, sizeof(labels));
1281 memset(relocs, 0, sizeof(relocs));
1282 memset(final_handler, 0, sizeof(final_handler));
1283
1284 if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) {
1285 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,
1286 scratch_reg);
1287 vmalloc_mode = refill_scratch;
1288 } else {
1289 htlb_info.huge_pte = K0;
1290 htlb_info.restore_scratch = 0;
1291 htlb_info.need_reload_pte = true;
1292 vmalloc_mode = refill_noscratch;
1293 /*
1294 * create the plain linear handler
1295 */
1296 if (bcm1250_m3_war()) {
1297 unsigned int segbits = 44;
1298
1299 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1300 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
1301 uasm_i_xor(&p, K0, K0, K1);
1302 uasm_i_dsrl_safe(&p, K1, K0, 62);
1303 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
1304 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
1305 uasm_i_or(&p, K0, K0, K1);
1306 uasm_il_bnez(&p, &r, K0, label_leave);
1307 /* No need for uasm_i_nop */
1308 }
1309
1310 #ifdef CONFIG_64BIT
1311 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
1312 #else
1313 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
1314 #endif
1315
1316 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1317 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update);
1318 #endif
1319
1320 build_get_ptep(&p, K0, K1);
1321 build_update_entries(&p, K0, K1);
1322 build_tlb_write_entry(&p, &l, &r, tlb_random);
1323 uasm_l_leave(&l, p);
1324 uasm_i_eret(&p); /* return from trap */
1325 }
1326 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1327 uasm_l_tlb_huge_update(&l, p);
1328 if (htlb_info.need_reload_pte)
1329 UASM_i_LW(&p, htlb_info.huge_pte, 0, K1);
1330 build_huge_update_entries(&p, htlb_info.huge_pte, K1);
1331 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random,
1332 htlb_info.restore_scratch);
1333 #endif
1334
1335 #ifdef CONFIG_64BIT
1336 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode);
1337 #endif
1338
1339 /*
1340 * Overflow check: For the 64bit handler, we need at least one
1341 * free instruction slot for the wrap-around branch. In worst
1342 * case, if the intended insertion point is a delay slot, we
1343 * need three, with the second nop'ed and the third being
1344 * unused.
1345 */
1346 switch (boot_cpu_type()) {
1347 default:
1348 if (sizeof(long) == 4) {
1349 case CPU_LOONGSON2:
1350 /* Loongson2 ebase is different than r4k, we have more space */
1351 if ((p - tlb_handler) > 64)
1352 panic("TLB refill handler space exceeded");
1353 /*
1354 * Now fold the handler in the TLB refill handler space.
1355 */
1356 f = final_handler;
1357 /* Simplest case, just copy the handler. */
1358 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1359 final_len = p - tlb_handler;
1360 break;
1361 } else {
1362 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1)
1363 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3)
1364 && uasm_insn_has_bdelay(relocs,
1365 tlb_handler + MIPS64_REFILL_INSNS - 3)))
1366 panic("TLB refill handler space exceeded");
1367 /*
1368 * Now fold the handler in the TLB refill handler space.
1369 */
1370 f = final_handler + MIPS64_REFILL_INSNS;
1371 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) {
1372 /* Just copy the handler. */
1373 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1374 final_len = p - tlb_handler;
1375 } else {
1376 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1377 const enum label_id ls = label_tlb_huge_update;
1378 #else
1379 const enum label_id ls = label_vmalloc;
1380 #endif
1381 u32 *split;
1382 int ov = 0;
1383 int i;
1384
1385 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++)
1386 ;
1387 BUG_ON(i == ARRAY_SIZE(labels));
1388 split = labels[i].addr;
1389
1390 /*
1391 * See if we have overflown one way or the other.
1392 */
1393 if (split > tlb_handler + MIPS64_REFILL_INSNS ||
1394 split < p - MIPS64_REFILL_INSNS)
1395 ov = 1;
1396
1397 if (ov) {
1398 /*
1399 * Split two instructions before the end. One
1400 * for the branch and one for the instruction
1401 * in the delay slot.
1402 */
1403 split = tlb_handler + MIPS64_REFILL_INSNS - 2;
1404
1405 /*
1406 * If the branch would fall in a delay slot,
1407 * we must back up an additional instruction
1408 * so that it is no longer in a delay slot.
1409 */
1410 if (uasm_insn_has_bdelay(relocs, split - 1))
1411 split--;
1412 }
1413 /* Copy first part of the handler. */
1414 uasm_copy_handler(relocs, labels, tlb_handler, split, f);
1415 f += split - tlb_handler;
1416
1417 if (ov) {
1418 /* Insert branch. */
1419 uasm_l_split(&l, final_handler);
1420 uasm_il_b(&f, &r, label_split);
1421 if (uasm_insn_has_bdelay(relocs, split))
1422 uasm_i_nop(&f);
1423 else {
1424 uasm_copy_handler(relocs, labels,
1425 split, split + 1, f);
1426 uasm_move_labels(labels, f, f + 1, -1);
1427 f++;
1428 split++;
1429 }
1430 }
1431
1432 /* Copy the rest of the handler. */
1433 uasm_copy_handler(relocs, labels, split, p, final_handler);
1434 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) +
1435 (p - split);
1436 }
1437 }
1438 break;
1439 }
1440
1441 uasm_resolve_relocs(relocs, labels);
1442 pr_debug("Wrote TLB refill handler (%u instructions).\n",
1443 final_len);
1444
1445 memcpy((void *)ebase, final_handler, 0x100);
1446 local_flush_icache_range(ebase, ebase + 0x100);
1447
1448 dump_handler("r4000_tlb_refill", (u32 *)ebase, 64);
1449 }
1450
1451 static void setup_pw(void)
1452 {
1453 unsigned long pgd_i, pgd_w;
1454 #ifndef __PAGETABLE_PMD_FOLDED
1455 unsigned long pmd_i, pmd_w;
1456 #endif
1457 unsigned long pt_i, pt_w;
1458 unsigned long pte_i, pte_w;
1459 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1460 unsigned long psn;
1461
1462 psn = ilog2(_PAGE_HUGE); /* bit used to indicate huge page */
1463 #endif
1464 pgd_i = PGDIR_SHIFT; /* 1st level PGD */
1465 #ifndef __PAGETABLE_PMD_FOLDED
1466 pgd_w = PGDIR_SHIFT - PMD_SHIFT + PGD_ORDER;
1467
1468 pmd_i = PMD_SHIFT; /* 2nd level PMD */
1469 pmd_w = PMD_SHIFT - PAGE_SHIFT;
1470 #else
1471 pgd_w = PGDIR_SHIFT - PAGE_SHIFT + PGD_ORDER;
1472 #endif
1473
1474 pt_i = PAGE_SHIFT; /* 3rd level PTE */
1475 pt_w = PAGE_SHIFT - 3;
1476
1477 pte_i = ilog2(_PAGE_GLOBAL);
1478 pte_w = 0;
1479
1480 #ifndef __PAGETABLE_PMD_FOLDED
1481 write_c0_pwfield(pgd_i << 24 | pmd_i << 12 | pt_i << 6 | pte_i);
1482 write_c0_pwsize(1 << 30 | pgd_w << 24 | pmd_w << 12 | pt_w << 6 | pte_w);
1483 #else
1484 write_c0_pwfield(pgd_i << 24 | pt_i << 6 | pte_i);
1485 write_c0_pwsize(1 << 30 | pgd_w << 24 | pt_w << 6 | pte_w);
1486 #endif
1487
1488 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1489 write_c0_pwctl(1 << 6 | psn);
1490 #endif
1491 write_c0_kpgd(swapper_pg_dir);
1492 kscratch_used_mask |= (1 << 7); /* KScratch6 is used for KPGD */
1493 }
1494
1495 static void build_loongson3_tlb_refill_handler(void)
1496 {
1497 u32 *p = tlb_handler;
1498 struct uasm_label *l = labels;
1499 struct uasm_reloc *r = relocs;
1500
1501 memset(labels, 0, sizeof(labels));
1502 memset(relocs, 0, sizeof(relocs));
1503 memset(tlb_handler, 0, sizeof(tlb_handler));
1504
1505 if (check_for_high_segbits) {
1506 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1507 uasm_i_dsrl_safe(&p, K1, K0, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
1508 uasm_il_beqz(&p, &r, K1, label_vmalloc);
1509 uasm_i_nop(&p);
1510
1511 uasm_il_bgez(&p, &r, K0, label_large_segbits_fault);
1512 uasm_i_nop(&p);
1513 uasm_l_vmalloc(&l, p);
1514 }
1515
1516 uasm_i_dmfc0(&p, K1, C0_PGD);
1517
1518 uasm_i_lddir(&p, K0, K1, 3); /* global page dir */
1519 #ifndef __PAGETABLE_PMD_FOLDED
1520 uasm_i_lddir(&p, K1, K0, 1); /* middle page dir */
1521 #endif
1522 uasm_i_ldpte(&p, K1, 0); /* even */
1523 uasm_i_ldpte(&p, K1, 1); /* odd */
1524 uasm_i_tlbwr(&p);
1525
1526 /* restore page mask */
1527 if (PM_DEFAULT_MASK >> 16) {
1528 uasm_i_lui(&p, K0, PM_DEFAULT_MASK >> 16);
1529 uasm_i_ori(&p, K0, K0, PM_DEFAULT_MASK & 0xffff);
1530 uasm_i_mtc0(&p, K0, C0_PAGEMASK);
1531 } else if (PM_DEFAULT_MASK) {
1532 uasm_i_ori(&p, K0, 0, PM_DEFAULT_MASK);
1533 uasm_i_mtc0(&p, K0, C0_PAGEMASK);
1534 } else {
1535 uasm_i_mtc0(&p, 0, C0_PAGEMASK);
1536 }
1537
1538 uasm_i_eret(&p);
1539
1540 if (check_for_high_segbits) {
1541 uasm_l_large_segbits_fault(&l, p);
1542 UASM_i_LA(&p, K1, (unsigned long)tlb_do_page_fault_0);
1543 uasm_i_jr(&p, K1);
1544 uasm_i_nop(&p);
1545 }
1546
1547 uasm_resolve_relocs(relocs, labels);
1548 memcpy((void *)(ebase + 0x80), tlb_handler, 0x80);
1549 local_flush_icache_range(ebase + 0x80, ebase + 0x100);
1550 dump_handler("loongson3_tlb_refill", (u32 *)(ebase + 0x80), 32);
1551 }
1552
1553 extern u32 handle_tlbl[], handle_tlbl_end[];
1554 extern u32 handle_tlbs[], handle_tlbs_end[];
1555 extern u32 handle_tlbm[], handle_tlbm_end[];
1556 extern u32 tlbmiss_handler_setup_pgd_start[];
1557 extern u32 tlbmiss_handler_setup_pgd[];
1558 EXPORT_SYMBOL_GPL(tlbmiss_handler_setup_pgd);
1559 extern u32 tlbmiss_handler_setup_pgd_end[];
1560
1561 static void build_setup_pgd(void)
1562 {
1563 const int a0 = 4;
1564 const int __maybe_unused a1 = 5;
1565 const int __maybe_unused a2 = 6;
1566 u32 *p = tlbmiss_handler_setup_pgd_start;
1567 const int tlbmiss_handler_setup_pgd_size =
1568 tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd_start;
1569 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1570 long pgdc = (long)pgd_current;
1571 #endif
1572
1573 memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size *
1574 sizeof(tlbmiss_handler_setup_pgd[0]));
1575 memset(labels, 0, sizeof(labels));
1576 memset(relocs, 0, sizeof(relocs));
1577 pgd_reg = allocate_kscratch();
1578 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
1579 if (pgd_reg == -1) {
1580 struct uasm_label *l = labels;
1581 struct uasm_reloc *r = relocs;
1582
1583 /* PGD << 11 in c0_Context */
1584 /*
1585 * If it is a ckseg0 address, convert to a physical
1586 * address. Shifting right by 29 and adding 4 will
1587 * result in zero for these addresses.
1588 *
1589 */
1590 UASM_i_SRA(&p, a1, a0, 29);
1591 UASM_i_ADDIU(&p, a1, a1, 4);
1592 uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1);
1593 uasm_i_nop(&p);
1594 uasm_i_dinsm(&p, a0, 0, 29, 64 - 29);
1595 uasm_l_tlbl_goaround1(&l, p);
1596 UASM_i_SLL(&p, a0, a0, 11);
1597 uasm_i_jr(&p, 31);
1598 UASM_i_MTC0(&p, a0, C0_CONTEXT);
1599 } else {
1600 /* PGD in c0_KScratch */
1601 uasm_i_jr(&p, 31);
1602 if (cpu_has_ldpte)
1603 UASM_i_MTC0(&p, a0, C0_PWBASE);
1604 else
1605 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
1606 }
1607 #else
1608 #ifdef CONFIG_SMP
1609 /* Save PGD to pgd_current[smp_processor_id()] */
1610 UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG);
1611 UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT);
1612 UASM_i_LA_mostly(&p, a2, pgdc);
1613 UASM_i_ADDU(&p, a2, a2, a1);
1614 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
1615 #else
1616 UASM_i_LA_mostly(&p, a2, pgdc);
1617 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
1618 #endif /* SMP */
1619 uasm_i_jr(&p, 31);
1620
1621 /* if pgd_reg is allocated, save PGD also to scratch register */
1622 if (pgd_reg != -1)
1623 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
1624 else
1625 uasm_i_nop(&p);
1626 #endif
1627 if (p >= tlbmiss_handler_setup_pgd_end)
1628 panic("tlbmiss_handler_setup_pgd space exceeded");
1629
1630 uasm_resolve_relocs(relocs, labels);
1631 pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n",
1632 (unsigned int)(p - tlbmiss_handler_setup_pgd));
1633
1634 dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd,
1635 tlbmiss_handler_setup_pgd_size);
1636 }
1637
1638 static void
1639 iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
1640 {
1641 #ifdef CONFIG_SMP
1642 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1643 if (cpu_has_64bits)
1644 uasm_i_lld(p, pte, 0, ptr);
1645 else
1646 # endif
1647 UASM_i_LL(p, pte, 0, ptr);
1648 #else
1649 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1650 if (cpu_has_64bits)
1651 uasm_i_ld(p, pte, 0, ptr);
1652 else
1653 # endif
1654 UASM_i_LW(p, pte, 0, ptr);
1655 #endif
1656 }
1657
1658 static void
1659 iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
1660 unsigned int mode, unsigned int scratch)
1661 {
1662 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
1663 unsigned int swmode = mode & ~hwmode;
1664
1665 if (IS_ENABLED(CONFIG_XPA) && !cpu_has_64bits) {
1666 uasm_i_lui(p, scratch, swmode >> 16);
1667 uasm_i_or(p, pte, pte, scratch);
1668 BUG_ON(swmode & 0xffff);
1669 } else {
1670 uasm_i_ori(p, pte, pte, mode);
1671 }
1672
1673 #ifdef CONFIG_SMP
1674 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1675 if (cpu_has_64bits)
1676 uasm_i_scd(p, pte, 0, ptr);
1677 else
1678 # endif
1679 UASM_i_SC(p, pte, 0, ptr);
1680
1681 if (r10000_llsc_war())
1682 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change);
1683 else
1684 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1685
1686 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1687 if (!cpu_has_64bits) {
1688 /* no uasm_i_nop needed */
1689 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr);
1690 uasm_i_ori(p, pte, pte, hwmode);
1691 BUG_ON(hwmode & ~0xffff);
1692 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr);
1693 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1694 /* no uasm_i_nop needed */
1695 uasm_i_lw(p, pte, 0, ptr);
1696 } else
1697 uasm_i_nop(p);
1698 # else
1699 uasm_i_nop(p);
1700 # endif
1701 #else
1702 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1703 if (cpu_has_64bits)
1704 uasm_i_sd(p, pte, 0, ptr);
1705 else
1706 # endif
1707 UASM_i_SW(p, pte, 0, ptr);
1708
1709 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1710 if (!cpu_has_64bits) {
1711 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr);
1712 uasm_i_ori(p, pte, pte, hwmode);
1713 BUG_ON(hwmode & ~0xffff);
1714 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr);
1715 uasm_i_lw(p, pte, 0, ptr);
1716 }
1717 # endif
1718 #endif
1719 }
1720
1721 /*
1722 * Check if PTE is present, if not then jump to LABEL. PTR points to
1723 * the page table where this PTE is located, PTE will be re-loaded
1724 * with it's original value.
1725 */
1726 static void
1727 build_pte_present(u32 **p, struct uasm_reloc **r,
1728 int pte, int ptr, int scratch, enum label_id lid)
1729 {
1730 int t = scratch >= 0 ? scratch : pte;
1731 int cur = pte;
1732
1733 if (cpu_has_rixi) {
1734 if (use_bbit_insns()) {
1735 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid);
1736 uasm_i_nop(p);
1737 } else {
1738 if (_PAGE_PRESENT_SHIFT) {
1739 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
1740 cur = t;
1741 }
1742 uasm_i_andi(p, t, cur, 1);
1743 uasm_il_beqz(p, r, t, lid);
1744 if (pte == t)
1745 /* You lose the SMP race :-(*/
1746 iPTE_LW(p, pte, ptr);
1747 }
1748 } else {
1749 if (_PAGE_PRESENT_SHIFT) {
1750 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
1751 cur = t;
1752 }
1753 uasm_i_andi(p, t, cur,
1754 (_PAGE_PRESENT | _PAGE_NO_READ) >> _PAGE_PRESENT_SHIFT);
1755 uasm_i_xori(p, t, t, _PAGE_PRESENT >> _PAGE_PRESENT_SHIFT);
1756 uasm_il_bnez(p, r, t, lid);
1757 if (pte == t)
1758 /* You lose the SMP race :-(*/
1759 iPTE_LW(p, pte, ptr);
1760 }
1761 }
1762
1763 /* Make PTE valid, store result in PTR. */
1764 static void
1765 build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
1766 unsigned int ptr, unsigned int scratch)
1767 {
1768 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
1769
1770 iPTE_SW(p, r, pte, ptr, mode, scratch);
1771 }
1772
1773 /*
1774 * Check if PTE can be written to, if not branch to LABEL. Regardless
1775 * restore PTE with value from PTR when done.
1776 */
1777 static void
1778 build_pte_writable(u32 **p, struct uasm_reloc **r,
1779 unsigned int pte, unsigned int ptr, int scratch,
1780 enum label_id lid)
1781 {
1782 int t = scratch >= 0 ? scratch : pte;
1783 int cur = pte;
1784
1785 if (_PAGE_PRESENT_SHIFT) {
1786 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
1787 cur = t;
1788 }
1789 uasm_i_andi(p, t, cur,
1790 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT);
1791 uasm_i_xori(p, t, t,
1792 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT);
1793 uasm_il_bnez(p, r, t, lid);
1794 if (pte == t)
1795 /* You lose the SMP race :-(*/
1796 iPTE_LW(p, pte, ptr);
1797 else
1798 uasm_i_nop(p);
1799 }
1800
1801 /* Make PTE writable, update software status bits as well, then store
1802 * at PTR.
1803 */
1804 static void
1805 build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
1806 unsigned int ptr, unsigned int scratch)
1807 {
1808 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
1809 | _PAGE_DIRTY);
1810
1811 iPTE_SW(p, r, pte, ptr, mode, scratch);
1812 }
1813
1814 /*
1815 * Check if PTE can be modified, if not branch to LABEL. Regardless
1816 * restore PTE with value from PTR when done.
1817 */
1818 static void
1819 build_pte_modifiable(u32 **p, struct uasm_reloc **r,
1820 unsigned int pte, unsigned int ptr, int scratch,
1821 enum label_id lid)
1822 {
1823 if (use_bbit_insns()) {
1824 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid);
1825 uasm_i_nop(p);
1826 } else {
1827 int t = scratch >= 0 ? scratch : pte;
1828 uasm_i_srl(p, t, pte, _PAGE_WRITE_SHIFT);
1829 uasm_i_andi(p, t, t, 1);
1830 uasm_il_beqz(p, r, t, lid);
1831 if (pte == t)
1832 /* You lose the SMP race :-(*/
1833 iPTE_LW(p, pte, ptr);
1834 }
1835 }
1836
1837 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1838
1839
1840 /*
1841 * R3000 style TLB load/store/modify handlers.
1842 */
1843
1844 /*
1845 * This places the pte into ENTRYLO0 and writes it with tlbwi.
1846 * Then it returns.
1847 */
1848 static void
1849 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
1850 {
1851 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1852 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
1853 uasm_i_tlbwi(p);
1854 uasm_i_jr(p, tmp);
1855 uasm_i_rfe(p); /* branch delay */
1856 }
1857
1858 /*
1859 * This places the pte into ENTRYLO0 and writes it with tlbwi
1860 * or tlbwr as appropriate. This is because the index register
1861 * may have the probe fail bit set as a result of a trap on a
1862 * kseg2 access, i.e. without refill. Then it returns.
1863 */
1864 static void
1865 build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l,
1866 struct uasm_reloc **r, unsigned int pte,
1867 unsigned int tmp)
1868 {
1869 uasm_i_mfc0(p, tmp, C0_INDEX);
1870 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1871 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
1872 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */
1873 uasm_i_tlbwi(p); /* cp0 delay */
1874 uasm_i_jr(p, tmp);
1875 uasm_i_rfe(p); /* branch delay */
1876 uasm_l_r3000_write_probe_fail(l, *p);
1877 uasm_i_tlbwr(p); /* cp0 delay */
1878 uasm_i_jr(p, tmp);
1879 uasm_i_rfe(p); /* branch delay */
1880 }
1881
1882 static void
1883 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1884 unsigned int ptr)
1885 {
1886 long pgdc = (long)pgd_current;
1887
1888 uasm_i_mfc0(p, pte, C0_BADVADDR);
1889 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */
1890 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
1891 uasm_i_srl(p, pte, pte, 22); /* load delay */
1892 uasm_i_sll(p, pte, pte, 2);
1893 uasm_i_addu(p, ptr, ptr, pte);
1894 uasm_i_mfc0(p, pte, C0_CONTEXT);
1895 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */
1896 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */
1897 uasm_i_addu(p, ptr, ptr, pte);
1898 uasm_i_lw(p, pte, 0, ptr);
1899 uasm_i_tlbp(p); /* load delay */
1900 }
1901
1902 static void build_r3000_tlb_load_handler(void)
1903 {
1904 u32 *p = handle_tlbl;
1905 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl;
1906 struct uasm_label *l = labels;
1907 struct uasm_reloc *r = relocs;
1908
1909 memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0]));
1910 memset(labels, 0, sizeof(labels));
1911 memset(relocs, 0, sizeof(relocs));
1912
1913 build_r3000_tlbchange_handler_head(&p, K0, K1);
1914 build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl);
1915 uasm_i_nop(&p); /* load delay */
1916 build_make_valid(&p, &r, K0, K1, -1);
1917 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1918
1919 uasm_l_nopage_tlbl(&l, p);
1920 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1921 uasm_i_nop(&p);
1922
1923 if (p >= handle_tlbl_end)
1924 panic("TLB load handler fastpath space exceeded");
1925
1926 uasm_resolve_relocs(relocs, labels);
1927 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1928 (unsigned int)(p - handle_tlbl));
1929
1930 dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_size);
1931 }
1932
1933 static void build_r3000_tlb_store_handler(void)
1934 {
1935 u32 *p = handle_tlbs;
1936 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs;
1937 struct uasm_label *l = labels;
1938 struct uasm_reloc *r = relocs;
1939
1940 memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0]));
1941 memset(labels, 0, sizeof(labels));
1942 memset(relocs, 0, sizeof(relocs));
1943
1944 build_r3000_tlbchange_handler_head(&p, K0, K1);
1945 build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs);
1946 uasm_i_nop(&p); /* load delay */
1947 build_make_write(&p, &r, K0, K1, -1);
1948 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1949
1950 uasm_l_nopage_tlbs(&l, p);
1951 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1952 uasm_i_nop(&p);
1953
1954 if (p >= handle_tlbs_end)
1955 panic("TLB store handler fastpath space exceeded");
1956
1957 uasm_resolve_relocs(relocs, labels);
1958 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1959 (unsigned int)(p - handle_tlbs));
1960
1961 dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_size);
1962 }
1963
1964 static void build_r3000_tlb_modify_handler(void)
1965 {
1966 u32 *p = handle_tlbm;
1967 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm;
1968 struct uasm_label *l = labels;
1969 struct uasm_reloc *r = relocs;
1970
1971 memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0]));
1972 memset(labels, 0, sizeof(labels));
1973 memset(relocs, 0, sizeof(relocs));
1974
1975 build_r3000_tlbchange_handler_head(&p, K0, K1);
1976 build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm);
1977 uasm_i_nop(&p); /* load delay */
1978 build_make_write(&p, &r, K0, K1, -1);
1979 build_r3000_pte_reload_tlbwi(&p, K0, K1);
1980
1981 uasm_l_nopage_tlbm(&l, p);
1982 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1983 uasm_i_nop(&p);
1984
1985 if (p >= handle_tlbm_end)
1986 panic("TLB modify handler fastpath space exceeded");
1987
1988 uasm_resolve_relocs(relocs, labels);
1989 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
1990 (unsigned int)(p - handle_tlbm));
1991
1992 dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_size);
1993 }
1994 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
1995
1996 /*
1997 * R4000 style TLB load/store/modify handlers.
1998 */
1999 static struct work_registers
2000 build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
2001 struct uasm_reloc **r)
2002 {
2003 struct work_registers wr = build_get_work_registers(p);
2004
2005 #ifdef CONFIG_64BIT
2006 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
2007 #else
2008 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
2009 #endif
2010
2011 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2012 /*
2013 * For huge tlb entries, pmd doesn't contain an address but
2014 * instead contains the tlb pte. Check the PAGE_HUGE bit and
2015 * see if we need to jump to huge tlb processing.
2016 */
2017 build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update);
2018 #endif
2019
2020 UASM_i_MFC0(p, wr.r1, C0_BADVADDR);
2021 UASM_i_LW(p, wr.r2, 0, wr.r2);
2022 UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
2023 uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
2024 UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1);
2025
2026 #ifdef CONFIG_SMP
2027 uasm_l_smp_pgtable_change(l, *p);
2028 #endif
2029 iPTE_LW(p, wr.r1, wr.r2); /* get even pte */
2030 if (!m4kc_tlbp_war()) {
2031 build_tlb_probe_entry(p);
2032 if (cpu_has_htw) {
2033 /* race condition happens, leaving */
2034 uasm_i_ehb(p);
2035 uasm_i_mfc0(p, wr.r3, C0_INDEX);
2036 uasm_il_bltz(p, r, wr.r3, label_leave);
2037 uasm_i_nop(p);
2038 }
2039 }
2040 return wr;
2041 }
2042
2043 static void
2044 build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l,
2045 struct uasm_reloc **r, unsigned int tmp,
2046 unsigned int ptr)
2047 {
2048 uasm_i_ori(p, ptr, ptr, sizeof(pte_t));
2049 uasm_i_xori(p, ptr, ptr, sizeof(pte_t));
2050 build_update_entries(p, tmp, ptr);
2051 build_tlb_write_entry(p, l, r, tlb_indexed);
2052 uasm_l_leave(l, *p);
2053 build_restore_work_registers(p);
2054 uasm_i_eret(p); /* return from trap */
2055
2056 #ifdef CONFIG_64BIT
2057 build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill);
2058 #endif
2059 }
2060
2061 static void build_r4000_tlb_load_handler(void)
2062 {
2063 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbl);
2064 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl;
2065 struct uasm_label *l = labels;
2066 struct uasm_reloc *r = relocs;
2067 struct work_registers wr;
2068
2069 memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0]));
2070 memset(labels, 0, sizeof(labels));
2071 memset(relocs, 0, sizeof(relocs));
2072
2073 if (bcm1250_m3_war()) {
2074 unsigned int segbits = 44;
2075
2076 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
2077 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
2078 uasm_i_xor(&p, K0, K0, K1);
2079 uasm_i_dsrl_safe(&p, K1, K0, 62);
2080 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
2081 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
2082 uasm_i_or(&p, K0, K0, K1);
2083 uasm_il_bnez(&p, &r, K0, label_leave);
2084 /* No need for uasm_i_nop */
2085 }
2086
2087 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2088 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
2089 if (m4kc_tlbp_war())
2090 build_tlb_probe_entry(&p);
2091
2092 if (cpu_has_rixi && !cpu_has_rixiex) {
2093 /*
2094 * If the page is not _PAGE_VALID, RI or XI could not
2095 * have triggered it. Skip the expensive test..
2096 */
2097 if (use_bbit_insns()) {
2098 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
2099 label_tlbl_goaround1);
2100 } else {
2101 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
2102 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1);
2103 }
2104 uasm_i_nop(&p);
2105
2106 uasm_i_tlbr(&p);
2107
2108 switch (current_cpu_type()) {
2109 default:
2110 if (cpu_has_mips_r2_exec_hazard) {
2111 uasm_i_ehb(&p);
2112
2113 case CPU_CAVIUM_OCTEON:
2114 case CPU_CAVIUM_OCTEON_PLUS:
2115 case CPU_CAVIUM_OCTEON2:
2116 break;
2117 }
2118 }
2119
2120 /* Examine entrylo 0 or 1 based on ptr. */
2121 if (use_bbit_insns()) {
2122 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
2123 } else {
2124 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
2125 uasm_i_beqz(&p, wr.r3, 8);
2126 }
2127 /* load it in the delay slot*/
2128 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
2129 /* load it if ptr is odd */
2130 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
2131 /*
2132 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
2133 * XI must have triggered it.
2134 */
2135 if (use_bbit_insns()) {
2136 uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl);
2137 uasm_i_nop(&p);
2138 uasm_l_tlbl_goaround1(&l, p);
2139 } else {
2140 uasm_i_andi(&p, wr.r3, wr.r3, 2);
2141 uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl);
2142 uasm_i_nop(&p);
2143 }
2144 uasm_l_tlbl_goaround1(&l, p);
2145 }
2146 build_make_valid(&p, &r, wr.r1, wr.r2, wr.r3);
2147 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2148
2149 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2150 /*
2151 * This is the entry point when build_r4000_tlbchange_handler_head
2152 * spots a huge page.
2153 */
2154 uasm_l_tlb_huge_update(&l, p);
2155 iPTE_LW(&p, wr.r1, wr.r2);
2156 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
2157 build_tlb_probe_entry(&p);
2158
2159 if (cpu_has_rixi && !cpu_has_rixiex) {
2160 /*
2161 * If the page is not _PAGE_VALID, RI or XI could not
2162 * have triggered it. Skip the expensive test..
2163 */
2164 if (use_bbit_insns()) {
2165 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
2166 label_tlbl_goaround2);
2167 } else {
2168 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
2169 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
2170 }
2171 uasm_i_nop(&p);
2172
2173 uasm_i_tlbr(&p);
2174
2175 switch (current_cpu_type()) {
2176 default:
2177 if (cpu_has_mips_r2_exec_hazard) {
2178 uasm_i_ehb(&p);
2179
2180 case CPU_CAVIUM_OCTEON:
2181 case CPU_CAVIUM_OCTEON_PLUS:
2182 case CPU_CAVIUM_OCTEON2:
2183 break;
2184 }
2185 }
2186
2187 /* Examine entrylo 0 or 1 based on ptr. */
2188 if (use_bbit_insns()) {
2189 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
2190 } else {
2191 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
2192 uasm_i_beqz(&p, wr.r3, 8);
2193 }
2194 /* load it in the delay slot*/
2195 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
2196 /* load it if ptr is odd */
2197 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
2198 /*
2199 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
2200 * XI must have triggered it.
2201 */
2202 if (use_bbit_insns()) {
2203 uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2);
2204 } else {
2205 uasm_i_andi(&p, wr.r3, wr.r3, 2);
2206 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
2207 }
2208 if (PM_DEFAULT_MASK == 0)
2209 uasm_i_nop(&p);
2210 /*
2211 * We clobbered C0_PAGEMASK, restore it. On the other branch
2212 * it is restored in build_huge_tlb_write_entry.
2213 */
2214 build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0);
2215
2216 uasm_l_tlbl_goaround2(&l, p);
2217 }
2218 uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID));
2219 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1);
2220 #endif
2221
2222 uasm_l_nopage_tlbl(&l, p);
2223 build_restore_work_registers(&p);
2224 #ifdef CONFIG_CPU_MICROMIPS
2225 if ((unsigned long)tlb_do_page_fault_0 & 1) {
2226 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0));
2227 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0));
2228 uasm_i_jr(&p, K0);
2229 } else
2230 #endif
2231 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
2232 uasm_i_nop(&p);
2233
2234 if (p >= handle_tlbl_end)
2235 panic("TLB load handler fastpath space exceeded");
2236
2237 uasm_resolve_relocs(relocs, labels);
2238 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
2239 (unsigned int)(p - handle_tlbl));
2240
2241 dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_size);
2242 }
2243
2244 static void build_r4000_tlb_store_handler(void)
2245 {
2246 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbs);
2247 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs;
2248 struct uasm_label *l = labels;
2249 struct uasm_reloc *r = relocs;
2250 struct work_registers wr;
2251
2252 memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0]));
2253 memset(labels, 0, sizeof(labels));
2254 memset(relocs, 0, sizeof(relocs));
2255
2256 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2257 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2258 if (m4kc_tlbp_war())
2259 build_tlb_probe_entry(&p);
2260 build_make_write(&p, &r, wr.r1, wr.r2, wr.r3);
2261 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2262
2263 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2264 /*
2265 * This is the entry point when
2266 * build_r4000_tlbchange_handler_head spots a huge page.
2267 */
2268 uasm_l_tlb_huge_update(&l, p);
2269 iPTE_LW(&p, wr.r1, wr.r2);
2270 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2271 build_tlb_probe_entry(&p);
2272 uasm_i_ori(&p, wr.r1, wr.r1,
2273 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2274 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1);
2275 #endif
2276
2277 uasm_l_nopage_tlbs(&l, p);
2278 build_restore_work_registers(&p);
2279 #ifdef CONFIG_CPU_MICROMIPS
2280 if ((unsigned long)tlb_do_page_fault_1 & 1) {
2281 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
2282 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
2283 uasm_i_jr(&p, K0);
2284 } else
2285 #endif
2286 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2287 uasm_i_nop(&p);
2288
2289 if (p >= handle_tlbs_end)
2290 panic("TLB store handler fastpath space exceeded");
2291
2292 uasm_resolve_relocs(relocs, labels);
2293 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
2294 (unsigned int)(p - handle_tlbs));
2295
2296 dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_size);
2297 }
2298
2299 static void build_r4000_tlb_modify_handler(void)
2300 {
2301 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbm);
2302 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm;
2303 struct uasm_label *l = labels;
2304 struct uasm_reloc *r = relocs;
2305 struct work_registers wr;
2306
2307 memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0]));
2308 memset(labels, 0, sizeof(labels));
2309 memset(relocs, 0, sizeof(relocs));
2310
2311 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2312 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2313 if (m4kc_tlbp_war())
2314 build_tlb_probe_entry(&p);
2315 /* Present and writable bits set, set accessed and dirty bits. */
2316 build_make_write(&p, &r, wr.r1, wr.r2, wr.r3);
2317 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2318
2319 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2320 /*
2321 * This is the entry point when
2322 * build_r4000_tlbchange_handler_head spots a huge page.
2323 */
2324 uasm_l_tlb_huge_update(&l, p);
2325 iPTE_LW(&p, wr.r1, wr.r2);
2326 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2327 build_tlb_probe_entry(&p);
2328 uasm_i_ori(&p, wr.r1, wr.r1,
2329 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2330 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 0);
2331 #endif
2332
2333 uasm_l_nopage_tlbm(&l, p);
2334 build_restore_work_registers(&p);
2335 #ifdef CONFIG_CPU_MICROMIPS
2336 if ((unsigned long)tlb_do_page_fault_1 & 1) {
2337 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
2338 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
2339 uasm_i_jr(&p, K0);
2340 } else
2341 #endif
2342 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2343 uasm_i_nop(&p);
2344
2345 if (p >= handle_tlbm_end)
2346 panic("TLB modify handler fastpath space exceeded");
2347
2348 uasm_resolve_relocs(relocs, labels);
2349 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
2350 (unsigned int)(p - handle_tlbm));
2351
2352 dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_size);
2353 }
2354
2355 static void flush_tlb_handlers(void)
2356 {
2357 local_flush_icache_range((unsigned long)handle_tlbl,
2358 (unsigned long)handle_tlbl_end);
2359 local_flush_icache_range((unsigned long)handle_tlbs,
2360 (unsigned long)handle_tlbs_end);
2361 local_flush_icache_range((unsigned long)handle_tlbm,
2362 (unsigned long)handle_tlbm_end);
2363 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd,
2364 (unsigned long)tlbmiss_handler_setup_pgd_end);
2365 }
2366
2367 static void print_htw_config(void)
2368 {
2369 unsigned long config;
2370 unsigned int pwctl;
2371 const int field = 2 * sizeof(unsigned long);
2372
2373 config = read_c0_pwfield();
2374 pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n",
2375 field, config,
2376 (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT,
2377 (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT,
2378 (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT,
2379 (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT,
2380 (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT);
2381
2382 config = read_c0_pwsize();
2383 pr_debug("PWSize (0x%0*lx): PS: 0x%lx GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n",
2384 field, config,
2385 (config & MIPS_PWSIZE_PS_MASK) >> MIPS_PWSIZE_PS_SHIFT,
2386 (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT,
2387 (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT,
2388 (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT,
2389 (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT,
2390 (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT);
2391
2392 pwctl = read_c0_pwctl();
2393 pr_debug("PWCtl (0x%x): PWEn: 0x%x XK: 0x%x XS: 0x%x XU: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n",
2394 pwctl,
2395 (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT,
2396 (pwctl & MIPS_PWCTL_XK_MASK) >> MIPS_PWCTL_XK_SHIFT,
2397 (pwctl & MIPS_PWCTL_XS_MASK) >> MIPS_PWCTL_XS_SHIFT,
2398 (pwctl & MIPS_PWCTL_XU_MASK) >> MIPS_PWCTL_XU_SHIFT,
2399 (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT,
2400 (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT,
2401 (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT);
2402 }
2403
2404 static void config_htw_params(void)
2405 {
2406 unsigned long pwfield, pwsize, ptei;
2407 unsigned int config;
2408
2409 /*
2410 * We are using 2-level page tables, so we only need to
2411 * setup GDW and PTW appropriately. UDW and MDW will remain 0.
2412 * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to
2413 * write values less than 0xc in these fields because the entire
2414 * write will be dropped. As a result of which, we must preserve
2415 * the original reset values and overwrite only what we really want.
2416 */
2417
2418 pwfield = read_c0_pwfield();
2419 /* re-initialize the GDI field */
2420 pwfield &= ~MIPS_PWFIELD_GDI_MASK;
2421 pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT;
2422 /* re-initialize the PTI field including the even/odd bit */
2423 pwfield &= ~MIPS_PWFIELD_PTI_MASK;
2424 pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT;
2425 if (CONFIG_PGTABLE_LEVELS >= 3) {
2426 pwfield &= ~MIPS_PWFIELD_MDI_MASK;
2427 pwfield |= PMD_SHIFT << MIPS_PWFIELD_MDI_SHIFT;
2428 }
2429 /* Set the PTEI right shift */
2430 ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT;
2431 pwfield |= ptei;
2432 write_c0_pwfield(pwfield);
2433 /* Check whether the PTEI value is supported */
2434 back_to_back_c0_hazard();
2435 pwfield = read_c0_pwfield();
2436 if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT)
2437 != ptei) {
2438 pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled",
2439 ptei);
2440 /*
2441 * Drop option to avoid HTW being enabled via another path
2442 * (eg htw_reset())
2443 */
2444 current_cpu_data.options &= ~MIPS_CPU_HTW;
2445 return;
2446 }
2447
2448 pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT;
2449 pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT;
2450 if (CONFIG_PGTABLE_LEVELS >= 3)
2451 pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT;
2452
2453 /* Set pointer size to size of directory pointers */
2454 if (IS_ENABLED(CONFIG_64BIT))
2455 pwsize |= MIPS_PWSIZE_PS_MASK;
2456 /* PTEs may be multiple pointers long (e.g. with XPA) */
2457 pwsize |= ((PTE_T_LOG2 - PGD_T_LOG2) << MIPS_PWSIZE_PTEW_SHIFT)
2458 & MIPS_PWSIZE_PTEW_MASK;
2459
2460 write_c0_pwsize(pwsize);
2461
2462 /* Make sure everything is set before we enable the HTW */
2463 back_to_back_c0_hazard();
2464
2465 /*
2466 * Enable HTW (and only for XUSeg on 64-bit), and disable the rest of
2467 * the pwctl fields.
2468 */
2469 config = 1 << MIPS_PWCTL_PWEN_SHIFT;
2470 if (IS_ENABLED(CONFIG_64BIT))
2471 config |= MIPS_PWCTL_XU_MASK;
2472 write_c0_pwctl(config);
2473 pr_info("Hardware Page Table Walker enabled\n");
2474
2475 print_htw_config();
2476 }
2477
2478 static void config_xpa_params(void)
2479 {
2480 #ifdef CONFIG_XPA
2481 unsigned int pagegrain;
2482
2483 if (mips_xpa_disabled) {
2484 pr_info("Extended Physical Addressing (XPA) disabled\n");
2485 return;
2486 }
2487
2488 pagegrain = read_c0_pagegrain();
2489 write_c0_pagegrain(pagegrain | PG_ELPA);
2490 back_to_back_c0_hazard();
2491 pagegrain = read_c0_pagegrain();
2492
2493 if (pagegrain & PG_ELPA)
2494 pr_info("Extended Physical Addressing (XPA) enabled\n");
2495 else
2496 panic("Extended Physical Addressing (XPA) disabled");
2497 #endif
2498 }
2499
2500 static void check_pabits(void)
2501 {
2502 unsigned long entry;
2503 unsigned pabits, fillbits;
2504
2505 if (!cpu_has_rixi || !_PAGE_NO_EXEC) {
2506 /*
2507 * We'll only be making use of the fact that we can rotate bits
2508 * into the fill if the CPU supports RIXI, so don't bother
2509 * probing this for CPUs which don't.
2510 */
2511 return;
2512 }
2513
2514 write_c0_entrylo0(~0ul);
2515 back_to_back_c0_hazard();
2516 entry = read_c0_entrylo0();
2517
2518 /* clear all non-PFN bits */
2519 entry &= ~((1 << MIPS_ENTRYLO_PFN_SHIFT) - 1);
2520 entry &= ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);
2521
2522 /* find a lower bound on PABITS, and upper bound on fill bits */
2523 pabits = fls_long(entry) + 6;
2524 fillbits = max_t(int, (int)BITS_PER_LONG - pabits, 0);
2525
2526 /* minus the RI & XI bits */
2527 fillbits -= min_t(unsigned, fillbits, 2);
2528
2529 if (fillbits >= ilog2(_PAGE_NO_EXEC))
2530 fill_includes_sw_bits = true;
2531
2532 pr_debug("Entry* registers contain %u fill bits\n", fillbits);
2533 }
2534
2535 void build_tlb_refill_handler(void)
2536 {
2537 /*
2538 * The refill handler is generated per-CPU, multi-node systems
2539 * may have local storage for it. The other handlers are only
2540 * needed once.
2541 */
2542 static int run_once = 0;
2543
2544 if (IS_ENABLED(CONFIG_XPA) && !cpu_has_rixi)
2545 panic("Kernels supporting XPA currently require CPUs with RIXI");
2546
2547 output_pgtable_bits_defines();
2548 check_pabits();
2549
2550 #ifdef CONFIG_64BIT
2551 check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
2552 #endif
2553
2554 switch (current_cpu_type()) {
2555 case CPU_R2000:
2556 case CPU_R3000:
2557 case CPU_R3000A:
2558 case CPU_R3081E:
2559 case CPU_TX3912:
2560 case CPU_TX3922:
2561 case CPU_TX3927:
2562 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
2563 if (cpu_has_local_ebase)
2564 build_r3000_tlb_refill_handler();
2565 if (!run_once) {
2566 if (!cpu_has_local_ebase)
2567 build_r3000_tlb_refill_handler();
2568 build_setup_pgd();
2569 build_r3000_tlb_load_handler();
2570 build_r3000_tlb_store_handler();
2571 build_r3000_tlb_modify_handler();
2572 flush_tlb_handlers();
2573 run_once++;
2574 }
2575 #else
2576 panic("No R3000 TLB refill handler");
2577 #endif
2578 break;
2579
2580 case CPU_R6000:
2581 case CPU_R6000A:
2582 panic("No R6000 TLB refill handler yet");
2583 break;
2584
2585 case CPU_R8000:
2586 panic("No R8000 TLB refill handler yet");
2587 break;
2588
2589 default:
2590 if (cpu_has_ldpte)
2591 setup_pw();
2592
2593 if (!run_once) {
2594 scratch_reg = allocate_kscratch();
2595 build_setup_pgd();
2596 build_r4000_tlb_load_handler();
2597 build_r4000_tlb_store_handler();
2598 build_r4000_tlb_modify_handler();
2599 if (cpu_has_ldpte)
2600 build_loongson3_tlb_refill_handler();
2601 else if (!cpu_has_local_ebase)
2602 build_r4000_tlb_refill_handler();
2603 flush_tlb_handlers();
2604 run_once++;
2605 }
2606 if (cpu_has_local_ebase)
2607 build_r4000_tlb_refill_handler();
2608 if (cpu_has_xpa)
2609 config_xpa_params();
2610 if (cpu_has_htw)
2611 config_htw_params();
2612 }
2613 }
ubuntu-bionic-kernel mirror