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MIPS: Add R16000 detection
[mirror_ubuntu-focal-kernel.git] / arch / mips / mm / tlbex.c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Synthesize TLB refill handlers at runtime.
7 *
8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
11 * Copyright (C) 2008, 2009 Cavium Networks, Inc.
12 * Copyright (C) 2011 MIPS Technologies, Inc.
13 *
14 * ... and the days got worse and worse and now you see
15 * I've gone completly out of my mind.
16 *
17 * They're coming to take me a away haha
18 * they're coming to take me a away hoho hihi haha
19 * to the funny farm where code is beautiful all the time ...
20 *
21 * (Condolences to Napoleon XIV)
22 */
23
24 #include <linux/bug.h>
25 #include <linux/kernel.h>
26 #include <linux/types.h>
27 #include <linux/smp.h>
28 #include <linux/string.h>
29 #include <linux/cache.h>
30
31 #include <asm/cacheflush.h>
32 #include <asm/cpu-type.h>
33 #include <asm/pgtable.h>
34 #include <asm/war.h>
35 #include <asm/uasm.h>
36 #include <asm/setup.h>
37
38 /*
39 * TLB load/store/modify handlers.
40 *
41 * Only the fastpath gets synthesized at runtime, the slowpath for
42 * do_page_fault remains normal asm.
43 */
44 extern void tlb_do_page_fault_0(void);
45 extern void tlb_do_page_fault_1(void);
46
47 struct work_registers {
48 int r1;
49 int r2;
50 int r3;
51 };
52
53 struct tlb_reg_save {
54 unsigned long a;
55 unsigned long b;
56 } ____cacheline_aligned_in_smp;
57
58 static struct tlb_reg_save handler_reg_save[NR_CPUS];
59
60 static inline int r45k_bvahwbug(void)
61 {
62 /* XXX: We should probe for the presence of this bug, but we don't. */
63 return 0;
64 }
65
66 static inline int r4k_250MHZhwbug(void)
67 {
68 /* XXX: We should probe for the presence of this bug, but we don't. */
69 return 0;
70 }
71
72 static inline int __maybe_unused bcm1250_m3_war(void)
73 {
74 return BCM1250_M3_WAR;
75 }
76
77 static inline int __maybe_unused r10000_llsc_war(void)
78 {
79 return R10000_LLSC_WAR;
80 }
81
82 static int use_bbit_insns(void)
83 {
84 switch (current_cpu_type()) {
85 case CPU_CAVIUM_OCTEON:
86 case CPU_CAVIUM_OCTEON_PLUS:
87 case CPU_CAVIUM_OCTEON2:
88 case CPU_CAVIUM_OCTEON3:
89 return 1;
90 default:
91 return 0;
92 }
93 }
94
95 static int use_lwx_insns(void)
96 {
97 switch (current_cpu_type()) {
98 case CPU_CAVIUM_OCTEON2:
99 case CPU_CAVIUM_OCTEON3:
100 return 1;
101 default:
102 return 0;
103 }
104 }
105 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
106 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
107 static bool scratchpad_available(void)
108 {
109 return true;
110 }
111 static int scratchpad_offset(int i)
112 {
113 /*
114 * CVMSEG starts at address -32768 and extends for
115 * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines.
116 */
117 i += 1; /* Kernel use starts at the top and works down. */
118 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768;
119 }
120 #else
121 static bool scratchpad_available(void)
122 {
123 return false;
124 }
125 static int scratchpad_offset(int i)
126 {
127 BUG();
128 /* Really unreachable, but evidently some GCC want this. */
129 return 0;
130 }
131 #endif
132 /*
133 * Found by experiment: At least some revisions of the 4kc throw under
134 * some circumstances a machine check exception, triggered by invalid
135 * values in the index register. Delaying the tlbp instruction until
136 * after the next branch, plus adding an additional nop in front of
137 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
138 * why; it's not an issue caused by the core RTL.
139 *
140 */
141 static int m4kc_tlbp_war(void)
142 {
143 return (current_cpu_data.processor_id & 0xffff00) ==
144 (PRID_COMP_MIPS | PRID_IMP_4KC);
145 }
146
147 /* Handle labels (which must be positive integers). */
148 enum label_id {
149 label_second_part = 1,
150 label_leave,
151 label_vmalloc,
152 label_vmalloc_done,
153 label_tlbw_hazard_0,
154 label_split = label_tlbw_hazard_0 + 8,
155 label_tlbl_goaround1,
156 label_tlbl_goaround2,
157 label_nopage_tlbl,
158 label_nopage_tlbs,
159 label_nopage_tlbm,
160 label_smp_pgtable_change,
161 label_r3000_write_probe_fail,
162 label_large_segbits_fault,
163 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
164 label_tlb_huge_update,
165 #endif
166 };
167
168 UASM_L_LA(_second_part)
169 UASM_L_LA(_leave)
170 UASM_L_LA(_vmalloc)
171 UASM_L_LA(_vmalloc_done)
172 /* _tlbw_hazard_x is handled differently. */
173 UASM_L_LA(_split)
174 UASM_L_LA(_tlbl_goaround1)
175 UASM_L_LA(_tlbl_goaround2)
176 UASM_L_LA(_nopage_tlbl)
177 UASM_L_LA(_nopage_tlbs)
178 UASM_L_LA(_nopage_tlbm)
179 UASM_L_LA(_smp_pgtable_change)
180 UASM_L_LA(_r3000_write_probe_fail)
181 UASM_L_LA(_large_segbits_fault)
182 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
183 UASM_L_LA(_tlb_huge_update)
184 #endif
185
186 static int hazard_instance;
187
188 static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance)
189 {
190 switch (instance) {
191 case 0 ... 7:
192 uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance);
193 return;
194 default:
195 BUG();
196 }
197 }
198
199 static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance)
200 {
201 switch (instance) {
202 case 0 ... 7:
203 uasm_build_label(l, *p, label_tlbw_hazard_0 + instance);
204 break;
205 default:
206 BUG();
207 }
208 }
209
210 /*
211 * pgtable bits are assigned dynamically depending on processor feature
212 * and statically based on kernel configuration. This spits out the actual
213 * values the kernel is using. Required to make sense from disassembled
214 * TLB exception handlers.
215 */
216 static void output_pgtable_bits_defines(void)
217 {
218 #define pr_define(fmt, ...) \
219 pr_debug("#define " fmt, ##__VA_ARGS__)
220
221 pr_debug("#include <asm/asm.h>\n");
222 pr_debug("#include <asm/regdef.h>\n");
223 pr_debug("\n");
224
225 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT);
226 pr_define("_PAGE_READ_SHIFT %d\n", _PAGE_READ_SHIFT);
227 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT);
228 pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT);
229 pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT);
230 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
231 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT);
232 pr_define("_PAGE_SPLITTING_SHIFT %d\n", _PAGE_SPLITTING_SHIFT);
233 #endif
234 if (cpu_has_rixi) {
235 #ifdef _PAGE_NO_EXEC_SHIFT
236 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT);
237 #endif
238 #ifdef _PAGE_NO_READ_SHIFT
239 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT);
240 #endif
241 }
242 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT);
243 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT);
244 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT);
245 pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT);
246 pr_debug("\n");
247 }
248
249 static inline void dump_handler(const char *symbol, const u32 *handler, int count)
250 {
251 int i;
252
253 pr_debug("LEAF(%s)\n", symbol);
254
255 pr_debug("\t.set push\n");
256 pr_debug("\t.set noreorder\n");
257
258 for (i = 0; i < count; i++)
259 pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]);
260
261 pr_debug("\t.set\tpop\n");
262
263 pr_debug("\tEND(%s)\n", symbol);
264 }
265
266 /* The only general purpose registers allowed in TLB handlers. */
267 #define K0 26
268 #define K1 27
269
270 /* Some CP0 registers */
271 #define C0_INDEX 0, 0
272 #define C0_ENTRYLO0 2, 0
273 #define C0_TCBIND 2, 2
274 #define C0_ENTRYLO1 3, 0
275 #define C0_CONTEXT 4, 0
276 #define C0_PAGEMASK 5, 0
277 #define C0_BADVADDR 8, 0
278 #define C0_ENTRYHI 10, 0
279 #define C0_EPC 14, 0
280 #define C0_XCONTEXT 20, 0
281
282 #ifdef CONFIG_64BIT
283 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
284 #else
285 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT)
286 #endif
287
288 /* The worst case length of the handler is around 18 instructions for
289 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
290 * Maximum space available is 32 instructions for R3000 and 64
291 * instructions for R4000.
292 *
293 * We deliberately chose a buffer size of 128, so we won't scribble
294 * over anything important on overflow before we panic.
295 */
296 static u32 tlb_handler[128];
297
298 /* simply assume worst case size for labels and relocs */
299 static struct uasm_label labels[128];
300 static struct uasm_reloc relocs[128];
301
302 static int check_for_high_segbits;
303
304 static unsigned int kscratch_used_mask;
305
306 static inline int __maybe_unused c0_kscratch(void)
307 {
308 switch (current_cpu_type()) {
309 case CPU_XLP:
310 case CPU_XLR:
311 return 22;
312 default:
313 return 31;
314 }
315 }
316
317 static int allocate_kscratch(void)
318 {
319 int r;
320 unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask;
321
322 r = ffs(a);
323
324 if (r == 0)
325 return -1;
326
327 r--; /* make it zero based */
328
329 kscratch_used_mask |= (1 << r);
330
331 return r;
332 }
333
334 static int scratch_reg;
335 static int pgd_reg;
336 enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch};
337
338 static struct work_registers build_get_work_registers(u32 **p)
339 {
340 struct work_registers r;
341
342 if (scratch_reg >= 0) {
343 /* Save in CPU local C0_KScratch? */
344 UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg);
345 r.r1 = K0;
346 r.r2 = K1;
347 r.r3 = 1;
348 return r;
349 }
350
351 if (num_possible_cpus() > 1) {
352 /* Get smp_processor_id */
353 UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG);
354 UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT);
355
356 /* handler_reg_save index in K0 */
357 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save)));
358
359 UASM_i_LA(p, K1, (long)&handler_reg_save);
360 UASM_i_ADDU(p, K0, K0, K1);
361 } else {
362 UASM_i_LA(p, K0, (long)&handler_reg_save);
363 }
364 /* K0 now points to save area, save $1 and $2 */
365 UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0);
366 UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0);
367
368 r.r1 = K1;
369 r.r2 = 1;
370 r.r3 = 2;
371 return r;
372 }
373
374 static void build_restore_work_registers(u32 **p)
375 {
376 if (scratch_reg >= 0) {
377 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
378 return;
379 }
380 /* K0 already points to save area, restore $1 and $2 */
381 UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0);
382 UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0);
383 }
384
385 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
386
387 /*
388 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
389 * we cannot do r3000 under these circumstances.
390 *
391 * Declare pgd_current here instead of including mmu_context.h to avoid type
392 * conflicts for tlbmiss_handler_setup_pgd
393 */
394 extern unsigned long pgd_current[];
395
396 /*
397 * The R3000 TLB handler is simple.
398 */
399 static void build_r3000_tlb_refill_handler(void)
400 {
401 long pgdc = (long)pgd_current;
402 u32 *p;
403
404 memset(tlb_handler, 0, sizeof(tlb_handler));
405 p = tlb_handler;
406
407 uasm_i_mfc0(&p, K0, C0_BADVADDR);
408 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */
409 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1);
410 uasm_i_srl(&p, K0, K0, 22); /* load delay */
411 uasm_i_sll(&p, K0, K0, 2);
412 uasm_i_addu(&p, K1, K1, K0);
413 uasm_i_mfc0(&p, K0, C0_CONTEXT);
414 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */
415 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */
416 uasm_i_addu(&p, K1, K1, K0);
417 uasm_i_lw(&p, K0, 0, K1);
418 uasm_i_nop(&p); /* load delay */
419 uasm_i_mtc0(&p, K0, C0_ENTRYLO0);
420 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
421 uasm_i_tlbwr(&p); /* cp0 delay */
422 uasm_i_jr(&p, K1);
423 uasm_i_rfe(&p); /* branch delay */
424
425 if (p > tlb_handler + 32)
426 panic("TLB refill handler space exceeded");
427
428 pr_debug("Wrote TLB refill handler (%u instructions).\n",
429 (unsigned int)(p - tlb_handler));
430
431 memcpy((void *)ebase, tlb_handler, 0x80);
432 local_flush_icache_range(ebase, ebase + 0x80);
433
434 dump_handler("r3000_tlb_refill", (u32 *)ebase, 32);
435 }
436 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
437
438 /*
439 * The R4000 TLB handler is much more complicated. We have two
440 * consecutive handler areas with 32 instructions space each.
441 * Since they aren't used at the same time, we can overflow in the
442 * other one.To keep things simple, we first assume linear space,
443 * then we relocate it to the final handler layout as needed.
444 */
445 static u32 final_handler[64];
446
447 /*
448 * Hazards
449 *
450 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
451 * 2. A timing hazard exists for the TLBP instruction.
452 *
453 * stalling_instruction
454 * TLBP
455 *
456 * The JTLB is being read for the TLBP throughout the stall generated by the
457 * previous instruction. This is not really correct as the stalling instruction
458 * can modify the address used to access the JTLB. The failure symptom is that
459 * the TLBP instruction will use an address created for the stalling instruction
460 * and not the address held in C0_ENHI and thus report the wrong results.
461 *
462 * The software work-around is to not allow the instruction preceding the TLBP
463 * to stall - make it an NOP or some other instruction guaranteed not to stall.
464 *
465 * Errata 2 will not be fixed. This errata is also on the R5000.
466 *
467 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
468 */
469 static void __maybe_unused build_tlb_probe_entry(u32 **p)
470 {
471 switch (current_cpu_type()) {
472 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */
473 case CPU_R4600:
474 case CPU_R4700:
475 case CPU_R5000:
476 case CPU_NEVADA:
477 uasm_i_nop(p);
478 uasm_i_tlbp(p);
479 break;
480
481 default:
482 uasm_i_tlbp(p);
483 break;
484 }
485 }
486
487 /*
488 * Write random or indexed TLB entry, and care about the hazards from
489 * the preceding mtc0 and for the following eret.
490 */
491 enum tlb_write_entry { tlb_random, tlb_indexed };
492
493 static void build_tlb_write_entry(u32 **p, struct uasm_label **l,
494 struct uasm_reloc **r,
495 enum tlb_write_entry wmode)
496 {
497 void(*tlbw)(u32 **) = NULL;
498
499 switch (wmode) {
500 case tlb_random: tlbw = uasm_i_tlbwr; break;
501 case tlb_indexed: tlbw = uasm_i_tlbwi; break;
502 }
503
504 if (cpu_has_mips_r2_exec_hazard) {
505 /*
506 * The architecture spec says an ehb is required here,
507 * but a number of cores do not have the hazard and
508 * using an ehb causes an expensive pipeline stall.
509 */
510 switch (current_cpu_type()) {
511 case CPU_M14KC:
512 case CPU_74K:
513 case CPU_1074K:
514 case CPU_PROAPTIV:
515 case CPU_P5600:
516 case CPU_M5150:
517 case CPU_QEMU_GENERIC:
518 break;
519
520 default:
521 uasm_i_ehb(p);
522 break;
523 }
524 tlbw(p);
525 return;
526 }
527
528 switch (current_cpu_type()) {
529 case CPU_R4000PC:
530 case CPU_R4000SC:
531 case CPU_R4000MC:
532 case CPU_R4400PC:
533 case CPU_R4400SC:
534 case CPU_R4400MC:
535 /*
536 * This branch uses up a mtc0 hazard nop slot and saves
537 * two nops after the tlbw instruction.
538 */
539 uasm_bgezl_hazard(p, r, hazard_instance);
540 tlbw(p);
541 uasm_bgezl_label(l, p, hazard_instance);
542 hazard_instance++;
543 uasm_i_nop(p);
544 break;
545
546 case CPU_R4600:
547 case CPU_R4700:
548 uasm_i_nop(p);
549 tlbw(p);
550 uasm_i_nop(p);
551 break;
552
553 case CPU_R5000:
554 case CPU_NEVADA:
555 uasm_i_nop(p); /* QED specifies 2 nops hazard */
556 uasm_i_nop(p); /* QED specifies 2 nops hazard */
557 tlbw(p);
558 break;
559
560 case CPU_R4300:
561 case CPU_5KC:
562 case CPU_TX49XX:
563 case CPU_PR4450:
564 case CPU_XLR:
565 uasm_i_nop(p);
566 tlbw(p);
567 break;
568
569 case CPU_R10000:
570 case CPU_R12000:
571 case CPU_R14000:
572 case CPU_R16000:
573 case CPU_4KC:
574 case CPU_4KEC:
575 case CPU_M14KC:
576 case CPU_M14KEC:
577 case CPU_SB1:
578 case CPU_SB1A:
579 case CPU_4KSC:
580 case CPU_20KC:
581 case CPU_25KF:
582 case CPU_BMIPS32:
583 case CPU_BMIPS3300:
584 case CPU_BMIPS4350:
585 case CPU_BMIPS4380:
586 case CPU_BMIPS5000:
587 case CPU_LOONGSON2:
588 case CPU_LOONGSON3:
589 case CPU_R5500:
590 if (m4kc_tlbp_war())
591 uasm_i_nop(p);
592 case CPU_ALCHEMY:
593 tlbw(p);
594 break;
595
596 case CPU_RM7000:
597 uasm_i_nop(p);
598 uasm_i_nop(p);
599 uasm_i_nop(p);
600 uasm_i_nop(p);
601 tlbw(p);
602 break;
603
604 case CPU_VR4111:
605 case CPU_VR4121:
606 case CPU_VR4122:
607 case CPU_VR4181:
608 case CPU_VR4181A:
609 uasm_i_nop(p);
610 uasm_i_nop(p);
611 tlbw(p);
612 uasm_i_nop(p);
613 uasm_i_nop(p);
614 break;
615
616 case CPU_VR4131:
617 case CPU_VR4133:
618 case CPU_R5432:
619 uasm_i_nop(p);
620 uasm_i_nop(p);
621 tlbw(p);
622 break;
623
624 case CPU_JZRISC:
625 tlbw(p);
626 uasm_i_nop(p);
627 break;
628
629 default:
630 panic("No TLB refill handler yet (CPU type: %d)",
631 current_cpu_type());
632 break;
633 }
634 }
635
636 static __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
637 unsigned int reg)
638 {
639 if (cpu_has_rixi) {
640 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL));
641 } else {
642 #ifdef CONFIG_PHYS_ADDR_T_64BIT
643 uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL));
644 #else
645 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL));
646 #endif
647 }
648 }
649
650 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
651
652 static void build_restore_pagemask(u32 **p, struct uasm_reloc **r,
653 unsigned int tmp, enum label_id lid,
654 int restore_scratch)
655 {
656 if (restore_scratch) {
657 /* Reset default page size */
658 if (PM_DEFAULT_MASK >> 16) {
659 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
660 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
661 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
662 uasm_il_b(p, r, lid);
663 } else if (PM_DEFAULT_MASK) {
664 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
665 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
666 uasm_il_b(p, r, lid);
667 } else {
668 uasm_i_mtc0(p, 0, C0_PAGEMASK);
669 uasm_il_b(p, r, lid);
670 }
671 if (scratch_reg >= 0)
672 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
673 else
674 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
675 } else {
676 /* Reset default page size */
677 if (PM_DEFAULT_MASK >> 16) {
678 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
679 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
680 uasm_il_b(p, r, lid);
681 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
682 } else if (PM_DEFAULT_MASK) {
683 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
684 uasm_il_b(p, r, lid);
685 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
686 } else {
687 uasm_il_b(p, r, lid);
688 uasm_i_mtc0(p, 0, C0_PAGEMASK);
689 }
690 }
691 }
692
693 static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l,
694 struct uasm_reloc **r,
695 unsigned int tmp,
696 enum tlb_write_entry wmode,
697 int restore_scratch)
698 {
699 /* Set huge page tlb entry size */
700 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16);
701 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff);
702 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
703
704 build_tlb_write_entry(p, l, r, wmode);
705
706 build_restore_pagemask(p, r, tmp, label_leave, restore_scratch);
707 }
708
709 /*
710 * Check if Huge PTE is present, if so then jump to LABEL.
711 */
712 static void
713 build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp,
714 unsigned int pmd, int lid)
715 {
716 UASM_i_LW(p, tmp, 0, pmd);
717 if (use_bbit_insns()) {
718 uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid);
719 } else {
720 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE);
721 uasm_il_bnez(p, r, tmp, lid);
722 }
723 }
724
725 static void build_huge_update_entries(u32 **p, unsigned int pte,
726 unsigned int tmp)
727 {
728 int small_sequence;
729
730 /*
731 * A huge PTE describes an area the size of the
732 * configured huge page size. This is twice the
733 * of the large TLB entry size we intend to use.
734 * A TLB entry half the size of the configured
735 * huge page size is configured into entrylo0
736 * and entrylo1 to cover the contiguous huge PTE
737 * address space.
738 */
739 small_sequence = (HPAGE_SIZE >> 7) < 0x10000;
740
741 /* We can clobber tmp. It isn't used after this.*/
742 if (!small_sequence)
743 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16));
744
745 build_convert_pte_to_entrylo(p, pte);
746 UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */
747 /* convert to entrylo1 */
748 if (small_sequence)
749 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7);
750 else
751 UASM_i_ADDU(p, pte, pte, tmp);
752
753 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */
754 }
755
756 static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r,
757 struct uasm_label **l,
758 unsigned int pte,
759 unsigned int ptr)
760 {
761 #ifdef CONFIG_SMP
762 UASM_i_SC(p, pte, 0, ptr);
763 uasm_il_beqz(p, r, pte, label_tlb_huge_update);
764 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */
765 #else
766 UASM_i_SW(p, pte, 0, ptr);
767 #endif
768 build_huge_update_entries(p, pte, ptr);
769 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0);
770 }
771 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
772
773 #ifdef CONFIG_64BIT
774 /*
775 * TMP and PTR are scratch.
776 * TMP will be clobbered, PTR will hold the pmd entry.
777 */
778 static void
779 build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
780 unsigned int tmp, unsigned int ptr)
781 {
782 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
783 long pgdc = (long)pgd_current;
784 #endif
785 /*
786 * The vmalloc handling is not in the hotpath.
787 */
788 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
789
790 if (check_for_high_segbits) {
791 /*
792 * The kernel currently implicitely assumes that the
793 * MIPS SEGBITS parameter for the processor is
794 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never
795 * allocate virtual addresses outside the maximum
796 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But
797 * that doesn't prevent user code from accessing the
798 * higher xuseg addresses. Here, we make sure that
799 * everything but the lower xuseg addresses goes down
800 * the module_alloc/vmalloc path.
801 */
802 uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
803 uasm_il_bnez(p, r, ptr, label_vmalloc);
804 } else {
805 uasm_il_bltz(p, r, tmp, label_vmalloc);
806 }
807 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
808
809 if (pgd_reg != -1) {
810 /* pgd is in pgd_reg */
811 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
812 } else {
813 #if defined(CONFIG_MIPS_PGD_C0_CONTEXT)
814 /*
815 * &pgd << 11 stored in CONTEXT [23..63].
816 */
817 UASM_i_MFC0(p, ptr, C0_CONTEXT);
818
819 /* Clear lower 23 bits of context. */
820 uasm_i_dins(p, ptr, 0, 0, 23);
821
822 /* 1 0 1 0 1 << 6 xkphys cached */
823 uasm_i_ori(p, ptr, ptr, 0x540);
824 uasm_i_drotr(p, ptr, ptr, 11);
825 #elif defined(CONFIG_SMP)
826 UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG);
827 uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
828 UASM_i_LA_mostly(p, tmp, pgdc);
829 uasm_i_daddu(p, ptr, ptr, tmp);
830 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
831 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
832 #else
833 UASM_i_LA_mostly(p, ptr, pgdc);
834 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
835 #endif
836 }
837
838 uasm_l_vmalloc_done(l, *p);
839
840 /* get pgd offset in bytes */
841 uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3);
842
843 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
844 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
845 #ifndef __PAGETABLE_PMD_FOLDED
846 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
847 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */
848 uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
849 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
850 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
851 #endif
852 }
853
854 /*
855 * BVADDR is the faulting address, PTR is scratch.
856 * PTR will hold the pgd for vmalloc.
857 */
858 static void
859 build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
860 unsigned int bvaddr, unsigned int ptr,
861 enum vmalloc64_mode mode)
862 {
863 long swpd = (long)swapper_pg_dir;
864 int single_insn_swpd;
865 int did_vmalloc_branch = 0;
866
867 single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd);
868
869 uasm_l_vmalloc(l, *p);
870
871 if (mode != not_refill && check_for_high_segbits) {
872 if (single_insn_swpd) {
873 uasm_il_bltz(p, r, bvaddr, label_vmalloc_done);
874 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
875 did_vmalloc_branch = 1;
876 /* fall through */
877 } else {
878 uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault);
879 }
880 }
881 if (!did_vmalloc_branch) {
882 if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) {
883 uasm_il_b(p, r, label_vmalloc_done);
884 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
885 } else {
886 UASM_i_LA_mostly(p, ptr, swpd);
887 uasm_il_b(p, r, label_vmalloc_done);
888 if (uasm_in_compat_space_p(swpd))
889 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd));
890 else
891 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd));
892 }
893 }
894 if (mode != not_refill && check_for_high_segbits) {
895 uasm_l_large_segbits_fault(l, *p);
896 /*
897 * We get here if we are an xsseg address, or if we are
898 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary.
899 *
900 * Ignoring xsseg (assume disabled so would generate
901 * (address errors?), the only remaining possibility
902 * is the upper xuseg addresses. On processors with
903 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these
904 * addresses would have taken an address error. We try
905 * to mimic that here by taking a load/istream page
906 * fault.
907 */
908 UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0);
909 uasm_i_jr(p, ptr);
910
911 if (mode == refill_scratch) {
912 if (scratch_reg >= 0)
913 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
914 else
915 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
916 } else {
917 uasm_i_nop(p);
918 }
919 }
920 }
921
922 #else /* !CONFIG_64BIT */
923
924 /*
925 * TMP and PTR are scratch.
926 * TMP will be clobbered, PTR will hold the pgd entry.
927 */
928 static void __maybe_unused
929 build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
930 {
931 if (pgd_reg != -1) {
932 /* pgd is in pgd_reg */
933 uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg);
934 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
935 } else {
936 long pgdc = (long)pgd_current;
937
938 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
939 #ifdef CONFIG_SMP
940 uasm_i_mfc0(p, ptr, SMP_CPUID_REG);
941 UASM_i_LA_mostly(p, tmp, pgdc);
942 uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
943 uasm_i_addu(p, ptr, tmp, ptr);
944 #else
945 UASM_i_LA_mostly(p, ptr, pgdc);
946 #endif
947 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
948 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
949 }
950 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
951 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
952 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
953 }
954
955 #endif /* !CONFIG_64BIT */
956
957 static void build_adjust_context(u32 **p, unsigned int ctx)
958 {
959 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
960 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
961
962 switch (current_cpu_type()) {
963 case CPU_VR41XX:
964 case CPU_VR4111:
965 case CPU_VR4121:
966 case CPU_VR4122:
967 case CPU_VR4131:
968 case CPU_VR4181:
969 case CPU_VR4181A:
970 case CPU_VR4133:
971 shift += 2;
972 break;
973
974 default:
975 break;
976 }
977
978 if (shift)
979 UASM_i_SRL(p, ctx, ctx, shift);
980 uasm_i_andi(p, ctx, ctx, mask);
981 }
982
983 static void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
984 {
985 /*
986 * Bug workaround for the Nevada. It seems as if under certain
987 * circumstances the move from cp0_context might produce a
988 * bogus result when the mfc0 instruction and its consumer are
989 * in a different cacheline or a load instruction, probably any
990 * memory reference, is between them.
991 */
992 switch (current_cpu_type()) {
993 case CPU_NEVADA:
994 UASM_i_LW(p, ptr, 0, ptr);
995 GET_CONTEXT(p, tmp); /* get context reg */
996 break;
997
998 default:
999 GET_CONTEXT(p, tmp); /* get context reg */
1000 UASM_i_LW(p, ptr, 0, ptr);
1001 break;
1002 }
1003
1004 build_adjust_context(p, tmp);
1005 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */
1006 }
1007
1008 static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
1009 {
1010 /*
1011 * 64bit address support (36bit on a 32bit CPU) in a 32bit
1012 * Kernel is a special case. Only a few CPUs use it.
1013 */
1014 #ifdef CONFIG_PHYS_ADDR_T_64BIT
1015 if (cpu_has_64bits) {
1016 uasm_i_ld(p, tmp, 0, ptep); /* get even pte */
1017 uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
1018 if (cpu_has_rixi) {
1019 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
1020 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1021 UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL));
1022 } else {
1023 uasm_i_dsrl_safe(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */
1024 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1025 uasm_i_dsrl_safe(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */
1026 }
1027 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1028 } else {
1029 int pte_off_even = sizeof(pte_t) / 2;
1030 int pte_off_odd = pte_off_even + sizeof(pte_t);
1031
1032 /* The pte entries are pre-shifted */
1033 uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */
1034 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1035 uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */
1036 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1037 }
1038 #else
1039 UASM_i_LW(p, tmp, 0, ptep); /* get even pte */
1040 UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
1041 if (r45k_bvahwbug())
1042 build_tlb_probe_entry(p);
1043 if (cpu_has_rixi) {
1044 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
1045 if (r4k_250MHZhwbug())
1046 UASM_i_MTC0(p, 0, C0_ENTRYLO0);
1047 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1048 UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL));
1049 } else {
1050 UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */
1051 if (r4k_250MHZhwbug())
1052 UASM_i_MTC0(p, 0, C0_ENTRYLO0);
1053 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1054 UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */
1055 if (r45k_bvahwbug())
1056 uasm_i_mfc0(p, tmp, C0_INDEX);
1057 }
1058 if (r4k_250MHZhwbug())
1059 UASM_i_MTC0(p, 0, C0_ENTRYLO1);
1060 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1061 #endif
1062 }
1063
1064 struct mips_huge_tlb_info {
1065 int huge_pte;
1066 int restore_scratch;
1067 bool need_reload_pte;
1068 };
1069
1070 static struct mips_huge_tlb_info
1071 build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
1072 struct uasm_reloc **r, unsigned int tmp,
1073 unsigned int ptr, int c0_scratch_reg)
1074 {
1075 struct mips_huge_tlb_info rv;
1076 unsigned int even, odd;
1077 int vmalloc_branch_delay_filled = 0;
1078 const int scratch = 1; /* Our extra working register */
1079
1080 rv.huge_pte = scratch;
1081 rv.restore_scratch = 0;
1082 rv.need_reload_pte = false;
1083
1084 if (check_for_high_segbits) {
1085 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1086
1087 if (pgd_reg != -1)
1088 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
1089 else
1090 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1091
1092 if (c0_scratch_reg >= 0)
1093 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1094 else
1095 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1096
1097 uasm_i_dsrl_safe(p, scratch, tmp,
1098 PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
1099 uasm_il_bnez(p, r, scratch, label_vmalloc);
1100
1101 if (pgd_reg == -1) {
1102 vmalloc_branch_delay_filled = 1;
1103 /* Clear lower 23 bits of context. */
1104 uasm_i_dins(p, ptr, 0, 0, 23);
1105 }
1106 } else {
1107 if (pgd_reg != -1)
1108 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
1109 else
1110 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1111
1112 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1113
1114 if (c0_scratch_reg >= 0)
1115 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1116 else
1117 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1118
1119 if (pgd_reg == -1)
1120 /* Clear lower 23 bits of context. */
1121 uasm_i_dins(p, ptr, 0, 0, 23);
1122
1123 uasm_il_bltz(p, r, tmp, label_vmalloc);
1124 }
1125
1126 if (pgd_reg == -1) {
1127 vmalloc_branch_delay_filled = 1;
1128 /* 1 0 1 0 1 << 6 xkphys cached */
1129 uasm_i_ori(p, ptr, ptr, 0x540);
1130 uasm_i_drotr(p, ptr, ptr, 11);
1131 }
1132
1133 #ifdef __PAGETABLE_PMD_FOLDED
1134 #define LOC_PTEP scratch
1135 #else
1136 #define LOC_PTEP ptr
1137 #endif
1138
1139 if (!vmalloc_branch_delay_filled)
1140 /* get pgd offset in bytes */
1141 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1142
1143 uasm_l_vmalloc_done(l, *p);
1144
1145 /*
1146 * tmp ptr
1147 * fall-through case = badvaddr *pgd_current
1148 * vmalloc case = badvaddr swapper_pg_dir
1149 */
1150
1151 if (vmalloc_branch_delay_filled)
1152 /* get pgd offset in bytes */
1153 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1154
1155 #ifdef __PAGETABLE_PMD_FOLDED
1156 GET_CONTEXT(p, tmp); /* get context reg */
1157 #endif
1158 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3);
1159
1160 if (use_lwx_insns()) {
1161 UASM_i_LWX(p, LOC_PTEP, scratch, ptr);
1162 } else {
1163 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */
1164 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */
1165 }
1166
1167 #ifndef __PAGETABLE_PMD_FOLDED
1168 /* get pmd offset in bytes */
1169 uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3);
1170 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3);
1171 GET_CONTEXT(p, tmp); /* get context reg */
1172
1173 if (use_lwx_insns()) {
1174 UASM_i_LWX(p, scratch, scratch, ptr);
1175 } else {
1176 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */
1177 UASM_i_LW(p, scratch, 0, ptr);
1178 }
1179 #endif
1180 /* Adjust the context during the load latency. */
1181 build_adjust_context(p, tmp);
1182
1183 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1184 uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update);
1185 /*
1186 * The in the LWX case we don't want to do the load in the
1187 * delay slot. It cannot issue in the same cycle and may be
1188 * speculative and unneeded.
1189 */
1190 if (use_lwx_insns())
1191 uasm_i_nop(p);
1192 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
1193
1194
1195 /* build_update_entries */
1196 if (use_lwx_insns()) {
1197 even = ptr;
1198 odd = tmp;
1199 UASM_i_LWX(p, even, scratch, tmp);
1200 UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t));
1201 UASM_i_LWX(p, odd, scratch, tmp);
1202 } else {
1203 UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */
1204 even = tmp;
1205 odd = ptr;
1206 UASM_i_LW(p, even, 0, ptr); /* get even pte */
1207 UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */
1208 }
1209 if (cpu_has_rixi) {
1210 uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL));
1211 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1212 uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL));
1213 } else {
1214 uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL));
1215 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1216 uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL));
1217 }
1218 UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */
1219
1220 if (c0_scratch_reg >= 0) {
1221 UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1222 build_tlb_write_entry(p, l, r, tlb_random);
1223 uasm_l_leave(l, *p);
1224 rv.restore_scratch = 1;
1225 } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) {
1226 build_tlb_write_entry(p, l, r, tlb_random);
1227 uasm_l_leave(l, *p);
1228 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1229 } else {
1230 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1231 build_tlb_write_entry(p, l, r, tlb_random);
1232 uasm_l_leave(l, *p);
1233 rv.restore_scratch = 1;
1234 }
1235
1236 uasm_i_eret(p); /* return from trap */
1237
1238 return rv;
1239 }
1240
1241 /*
1242 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
1243 * because EXL == 0. If we wrap, we can also use the 32 instruction
1244 * slots before the XTLB refill exception handler which belong to the
1245 * unused TLB refill exception.
1246 */
1247 #define MIPS64_REFILL_INSNS 32
1248
1249 static void build_r4000_tlb_refill_handler(void)
1250 {
1251 u32 *p = tlb_handler;
1252 struct uasm_label *l = labels;
1253 struct uasm_reloc *r = relocs;
1254 u32 *f;
1255 unsigned int final_len;
1256 struct mips_huge_tlb_info htlb_info __maybe_unused;
1257 enum vmalloc64_mode vmalloc_mode __maybe_unused;
1258
1259 memset(tlb_handler, 0, sizeof(tlb_handler));
1260 memset(labels, 0, sizeof(labels));
1261 memset(relocs, 0, sizeof(relocs));
1262 memset(final_handler, 0, sizeof(final_handler));
1263
1264 if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) {
1265 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,
1266 scratch_reg);
1267 vmalloc_mode = refill_scratch;
1268 } else {
1269 htlb_info.huge_pte = K0;
1270 htlb_info.restore_scratch = 0;
1271 htlb_info.need_reload_pte = true;
1272 vmalloc_mode = refill_noscratch;
1273 /*
1274 * create the plain linear handler
1275 */
1276 if (bcm1250_m3_war()) {
1277 unsigned int segbits = 44;
1278
1279 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1280 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
1281 uasm_i_xor(&p, K0, K0, K1);
1282 uasm_i_dsrl_safe(&p, K1, K0, 62);
1283 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
1284 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
1285 uasm_i_or(&p, K0, K0, K1);
1286 uasm_il_bnez(&p, &r, K0, label_leave);
1287 /* No need for uasm_i_nop */
1288 }
1289
1290 #ifdef CONFIG_64BIT
1291 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
1292 #else
1293 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
1294 #endif
1295
1296 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1297 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update);
1298 #endif
1299
1300 build_get_ptep(&p, K0, K1);
1301 build_update_entries(&p, K0, K1);
1302 build_tlb_write_entry(&p, &l, &r, tlb_random);
1303 uasm_l_leave(&l, p);
1304 uasm_i_eret(&p); /* return from trap */
1305 }
1306 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1307 uasm_l_tlb_huge_update(&l, p);
1308 if (htlb_info.need_reload_pte)
1309 UASM_i_LW(&p, htlb_info.huge_pte, 0, K1);
1310 build_huge_update_entries(&p, htlb_info.huge_pte, K1);
1311 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random,
1312 htlb_info.restore_scratch);
1313 #endif
1314
1315 #ifdef CONFIG_64BIT
1316 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode);
1317 #endif
1318
1319 /*
1320 * Overflow check: For the 64bit handler, we need at least one
1321 * free instruction slot for the wrap-around branch. In worst
1322 * case, if the intended insertion point is a delay slot, we
1323 * need three, with the second nop'ed and the third being
1324 * unused.
1325 */
1326 switch (boot_cpu_type()) {
1327 default:
1328 if (sizeof(long) == 4) {
1329 case CPU_LOONGSON2:
1330 /* Loongson2 ebase is different than r4k, we have more space */
1331 if ((p - tlb_handler) > 64)
1332 panic("TLB refill handler space exceeded");
1333 /*
1334 * Now fold the handler in the TLB refill handler space.
1335 */
1336 f = final_handler;
1337 /* Simplest case, just copy the handler. */
1338 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1339 final_len = p - tlb_handler;
1340 break;
1341 } else {
1342 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1)
1343 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3)
1344 && uasm_insn_has_bdelay(relocs,
1345 tlb_handler + MIPS64_REFILL_INSNS - 3)))
1346 panic("TLB refill handler space exceeded");
1347 /*
1348 * Now fold the handler in the TLB refill handler space.
1349 */
1350 f = final_handler + MIPS64_REFILL_INSNS;
1351 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) {
1352 /* Just copy the handler. */
1353 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1354 final_len = p - tlb_handler;
1355 } else {
1356 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1357 const enum label_id ls = label_tlb_huge_update;
1358 #else
1359 const enum label_id ls = label_vmalloc;
1360 #endif
1361 u32 *split;
1362 int ov = 0;
1363 int i;
1364
1365 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++)
1366 ;
1367 BUG_ON(i == ARRAY_SIZE(labels));
1368 split = labels[i].addr;
1369
1370 /*
1371 * See if we have overflown one way or the other.
1372 */
1373 if (split > tlb_handler + MIPS64_REFILL_INSNS ||
1374 split < p - MIPS64_REFILL_INSNS)
1375 ov = 1;
1376
1377 if (ov) {
1378 /*
1379 * Split two instructions before the end. One
1380 * for the branch and one for the instruction
1381 * in the delay slot.
1382 */
1383 split = tlb_handler + MIPS64_REFILL_INSNS - 2;
1384
1385 /*
1386 * If the branch would fall in a delay slot,
1387 * we must back up an additional instruction
1388 * so that it is no longer in a delay slot.
1389 */
1390 if (uasm_insn_has_bdelay(relocs, split - 1))
1391 split--;
1392 }
1393 /* Copy first part of the handler. */
1394 uasm_copy_handler(relocs, labels, tlb_handler, split, f);
1395 f += split - tlb_handler;
1396
1397 if (ov) {
1398 /* Insert branch. */
1399 uasm_l_split(&l, final_handler);
1400 uasm_il_b(&f, &r, label_split);
1401 if (uasm_insn_has_bdelay(relocs, split))
1402 uasm_i_nop(&f);
1403 else {
1404 uasm_copy_handler(relocs, labels,
1405 split, split + 1, f);
1406 uasm_move_labels(labels, f, f + 1, -1);
1407 f++;
1408 split++;
1409 }
1410 }
1411
1412 /* Copy the rest of the handler. */
1413 uasm_copy_handler(relocs, labels, split, p, final_handler);
1414 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) +
1415 (p - split);
1416 }
1417 }
1418 break;
1419 }
1420
1421 uasm_resolve_relocs(relocs, labels);
1422 pr_debug("Wrote TLB refill handler (%u instructions).\n",
1423 final_len);
1424
1425 memcpy((void *)ebase, final_handler, 0x100);
1426 local_flush_icache_range(ebase, ebase + 0x100);
1427
1428 dump_handler("r4000_tlb_refill", (u32 *)ebase, 64);
1429 }
1430
1431 extern u32 handle_tlbl[], handle_tlbl_end[];
1432 extern u32 handle_tlbs[], handle_tlbs_end[];
1433 extern u32 handle_tlbm[], handle_tlbm_end[];
1434 extern u32 tlbmiss_handler_setup_pgd_start[], tlbmiss_handler_setup_pgd[];
1435 extern u32 tlbmiss_handler_setup_pgd_end[];
1436
1437 static void build_setup_pgd(void)
1438 {
1439 const int a0 = 4;
1440 const int __maybe_unused a1 = 5;
1441 const int __maybe_unused a2 = 6;
1442 u32 *p = tlbmiss_handler_setup_pgd_start;
1443 const int tlbmiss_handler_setup_pgd_size =
1444 tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd_start;
1445 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1446 long pgdc = (long)pgd_current;
1447 #endif
1448
1449 memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size *
1450 sizeof(tlbmiss_handler_setup_pgd[0]));
1451 memset(labels, 0, sizeof(labels));
1452 memset(relocs, 0, sizeof(relocs));
1453 pgd_reg = allocate_kscratch();
1454 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
1455 if (pgd_reg == -1) {
1456 struct uasm_label *l = labels;
1457 struct uasm_reloc *r = relocs;
1458
1459 /* PGD << 11 in c0_Context */
1460 /*
1461 * If it is a ckseg0 address, convert to a physical
1462 * address. Shifting right by 29 and adding 4 will
1463 * result in zero for these addresses.
1464 *
1465 */
1466 UASM_i_SRA(&p, a1, a0, 29);
1467 UASM_i_ADDIU(&p, a1, a1, 4);
1468 uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1);
1469 uasm_i_nop(&p);
1470 uasm_i_dinsm(&p, a0, 0, 29, 64 - 29);
1471 uasm_l_tlbl_goaround1(&l, p);
1472 UASM_i_SLL(&p, a0, a0, 11);
1473 uasm_i_jr(&p, 31);
1474 UASM_i_MTC0(&p, a0, C0_CONTEXT);
1475 } else {
1476 /* PGD in c0_KScratch */
1477 uasm_i_jr(&p, 31);
1478 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
1479 }
1480 #else
1481 #ifdef CONFIG_SMP
1482 /* Save PGD to pgd_current[smp_processor_id()] */
1483 UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG);
1484 UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT);
1485 UASM_i_LA_mostly(&p, a2, pgdc);
1486 UASM_i_ADDU(&p, a2, a2, a1);
1487 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
1488 #else
1489 UASM_i_LA_mostly(&p, a2, pgdc);
1490 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
1491 #endif /* SMP */
1492 uasm_i_jr(&p, 31);
1493
1494 /* if pgd_reg is allocated, save PGD also to scratch register */
1495 if (pgd_reg != -1)
1496 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
1497 else
1498 uasm_i_nop(&p);
1499 #endif
1500 if (p >= tlbmiss_handler_setup_pgd_end)
1501 panic("tlbmiss_handler_setup_pgd space exceeded");
1502
1503 uasm_resolve_relocs(relocs, labels);
1504 pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n",
1505 (unsigned int)(p - tlbmiss_handler_setup_pgd));
1506
1507 dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd,
1508 tlbmiss_handler_setup_pgd_size);
1509 }
1510
1511 static void
1512 iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
1513 {
1514 #ifdef CONFIG_SMP
1515 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1516 if (cpu_has_64bits)
1517 uasm_i_lld(p, pte, 0, ptr);
1518 else
1519 # endif
1520 UASM_i_LL(p, pte, 0, ptr);
1521 #else
1522 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1523 if (cpu_has_64bits)
1524 uasm_i_ld(p, pte, 0, ptr);
1525 else
1526 # endif
1527 UASM_i_LW(p, pte, 0, ptr);
1528 #endif
1529 }
1530
1531 static void
1532 iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
1533 unsigned int mode)
1534 {
1535 #ifdef CONFIG_PHYS_ADDR_T_64BIT
1536 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
1537 #endif
1538
1539 uasm_i_ori(p, pte, pte, mode);
1540 #ifdef CONFIG_SMP
1541 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1542 if (cpu_has_64bits)
1543 uasm_i_scd(p, pte, 0, ptr);
1544 else
1545 # endif
1546 UASM_i_SC(p, pte, 0, ptr);
1547
1548 if (r10000_llsc_war())
1549 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change);
1550 else
1551 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1552
1553 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1554 if (!cpu_has_64bits) {
1555 /* no uasm_i_nop needed */
1556 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr);
1557 uasm_i_ori(p, pte, pte, hwmode);
1558 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr);
1559 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1560 /* no uasm_i_nop needed */
1561 uasm_i_lw(p, pte, 0, ptr);
1562 } else
1563 uasm_i_nop(p);
1564 # else
1565 uasm_i_nop(p);
1566 # endif
1567 #else
1568 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1569 if (cpu_has_64bits)
1570 uasm_i_sd(p, pte, 0, ptr);
1571 else
1572 # endif
1573 UASM_i_SW(p, pte, 0, ptr);
1574
1575 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1576 if (!cpu_has_64bits) {
1577 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr);
1578 uasm_i_ori(p, pte, pte, hwmode);
1579 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr);
1580 uasm_i_lw(p, pte, 0, ptr);
1581 }
1582 # endif
1583 #endif
1584 }
1585
1586 /*
1587 * Check if PTE is present, if not then jump to LABEL. PTR points to
1588 * the page table where this PTE is located, PTE will be re-loaded
1589 * with it's original value.
1590 */
1591 static void
1592 build_pte_present(u32 **p, struct uasm_reloc **r,
1593 int pte, int ptr, int scratch, enum label_id lid)
1594 {
1595 int t = scratch >= 0 ? scratch : pte;
1596
1597 if (cpu_has_rixi) {
1598 if (use_bbit_insns()) {
1599 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid);
1600 uasm_i_nop(p);
1601 } else {
1602 uasm_i_andi(p, t, pte, _PAGE_PRESENT);
1603 uasm_il_beqz(p, r, t, lid);
1604 if (pte == t)
1605 /* You lose the SMP race :-(*/
1606 iPTE_LW(p, pte, ptr);
1607 }
1608 } else {
1609 uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_READ);
1610 uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_READ);
1611 uasm_il_bnez(p, r, t, lid);
1612 if (pte == t)
1613 /* You lose the SMP race :-(*/
1614 iPTE_LW(p, pte, ptr);
1615 }
1616 }
1617
1618 /* Make PTE valid, store result in PTR. */
1619 static void
1620 build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
1621 unsigned int ptr)
1622 {
1623 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
1624
1625 iPTE_SW(p, r, pte, ptr, mode);
1626 }
1627
1628 /*
1629 * Check if PTE can be written to, if not branch to LABEL. Regardless
1630 * restore PTE with value from PTR when done.
1631 */
1632 static void
1633 build_pte_writable(u32 **p, struct uasm_reloc **r,
1634 unsigned int pte, unsigned int ptr, int scratch,
1635 enum label_id lid)
1636 {
1637 int t = scratch >= 0 ? scratch : pte;
1638
1639 uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_WRITE);
1640 uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_WRITE);
1641 uasm_il_bnez(p, r, t, lid);
1642 if (pte == t)
1643 /* You lose the SMP race :-(*/
1644 iPTE_LW(p, pte, ptr);
1645 else
1646 uasm_i_nop(p);
1647 }
1648
1649 /* Make PTE writable, update software status bits as well, then store
1650 * at PTR.
1651 */
1652 static void
1653 build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
1654 unsigned int ptr)
1655 {
1656 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
1657 | _PAGE_DIRTY);
1658
1659 iPTE_SW(p, r, pte, ptr, mode);
1660 }
1661
1662 /*
1663 * Check if PTE can be modified, if not branch to LABEL. Regardless
1664 * restore PTE with value from PTR when done.
1665 */
1666 static void
1667 build_pte_modifiable(u32 **p, struct uasm_reloc **r,
1668 unsigned int pte, unsigned int ptr, int scratch,
1669 enum label_id lid)
1670 {
1671 if (use_bbit_insns()) {
1672 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid);
1673 uasm_i_nop(p);
1674 } else {
1675 int t = scratch >= 0 ? scratch : pte;
1676 uasm_i_andi(p, t, pte, _PAGE_WRITE);
1677 uasm_il_beqz(p, r, t, lid);
1678 if (pte == t)
1679 /* You lose the SMP race :-(*/
1680 iPTE_LW(p, pte, ptr);
1681 }
1682 }
1683
1684 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1685
1686
1687 /*
1688 * R3000 style TLB load/store/modify handlers.
1689 */
1690
1691 /*
1692 * This places the pte into ENTRYLO0 and writes it with tlbwi.
1693 * Then it returns.
1694 */
1695 static void
1696 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
1697 {
1698 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1699 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
1700 uasm_i_tlbwi(p);
1701 uasm_i_jr(p, tmp);
1702 uasm_i_rfe(p); /* branch delay */
1703 }
1704
1705 /*
1706 * This places the pte into ENTRYLO0 and writes it with tlbwi
1707 * or tlbwr as appropriate. This is because the index register
1708 * may have the probe fail bit set as a result of a trap on a
1709 * kseg2 access, i.e. without refill. Then it returns.
1710 */
1711 static void
1712 build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l,
1713 struct uasm_reloc **r, unsigned int pte,
1714 unsigned int tmp)
1715 {
1716 uasm_i_mfc0(p, tmp, C0_INDEX);
1717 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1718 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
1719 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */
1720 uasm_i_tlbwi(p); /* cp0 delay */
1721 uasm_i_jr(p, tmp);
1722 uasm_i_rfe(p); /* branch delay */
1723 uasm_l_r3000_write_probe_fail(l, *p);
1724 uasm_i_tlbwr(p); /* cp0 delay */
1725 uasm_i_jr(p, tmp);
1726 uasm_i_rfe(p); /* branch delay */
1727 }
1728
1729 static void
1730 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1731 unsigned int ptr)
1732 {
1733 long pgdc = (long)pgd_current;
1734
1735 uasm_i_mfc0(p, pte, C0_BADVADDR);
1736 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */
1737 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
1738 uasm_i_srl(p, pte, pte, 22); /* load delay */
1739 uasm_i_sll(p, pte, pte, 2);
1740 uasm_i_addu(p, ptr, ptr, pte);
1741 uasm_i_mfc0(p, pte, C0_CONTEXT);
1742 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */
1743 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */
1744 uasm_i_addu(p, ptr, ptr, pte);
1745 uasm_i_lw(p, pte, 0, ptr);
1746 uasm_i_tlbp(p); /* load delay */
1747 }
1748
1749 static void build_r3000_tlb_load_handler(void)
1750 {
1751 u32 *p = handle_tlbl;
1752 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl;
1753 struct uasm_label *l = labels;
1754 struct uasm_reloc *r = relocs;
1755
1756 memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0]));
1757 memset(labels, 0, sizeof(labels));
1758 memset(relocs, 0, sizeof(relocs));
1759
1760 build_r3000_tlbchange_handler_head(&p, K0, K1);
1761 build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl);
1762 uasm_i_nop(&p); /* load delay */
1763 build_make_valid(&p, &r, K0, K1);
1764 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1765
1766 uasm_l_nopage_tlbl(&l, p);
1767 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1768 uasm_i_nop(&p);
1769
1770 if (p >= handle_tlbl_end)
1771 panic("TLB load handler fastpath space exceeded");
1772
1773 uasm_resolve_relocs(relocs, labels);
1774 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1775 (unsigned int)(p - handle_tlbl));
1776
1777 dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_size);
1778 }
1779
1780 static void build_r3000_tlb_store_handler(void)
1781 {
1782 u32 *p = handle_tlbs;
1783 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs;
1784 struct uasm_label *l = labels;
1785 struct uasm_reloc *r = relocs;
1786
1787 memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0]));
1788 memset(labels, 0, sizeof(labels));
1789 memset(relocs, 0, sizeof(relocs));
1790
1791 build_r3000_tlbchange_handler_head(&p, K0, K1);
1792 build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs);
1793 uasm_i_nop(&p); /* load delay */
1794 build_make_write(&p, &r, K0, K1);
1795 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1796
1797 uasm_l_nopage_tlbs(&l, p);
1798 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1799 uasm_i_nop(&p);
1800
1801 if (p >= handle_tlbs_end)
1802 panic("TLB store handler fastpath space exceeded");
1803
1804 uasm_resolve_relocs(relocs, labels);
1805 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1806 (unsigned int)(p - handle_tlbs));
1807
1808 dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_size);
1809 }
1810
1811 static void build_r3000_tlb_modify_handler(void)
1812 {
1813 u32 *p = handle_tlbm;
1814 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm;
1815 struct uasm_label *l = labels;
1816 struct uasm_reloc *r = relocs;
1817
1818 memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0]));
1819 memset(labels, 0, sizeof(labels));
1820 memset(relocs, 0, sizeof(relocs));
1821
1822 build_r3000_tlbchange_handler_head(&p, K0, K1);
1823 build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm);
1824 uasm_i_nop(&p); /* load delay */
1825 build_make_write(&p, &r, K0, K1);
1826 build_r3000_pte_reload_tlbwi(&p, K0, K1);
1827
1828 uasm_l_nopage_tlbm(&l, p);
1829 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1830 uasm_i_nop(&p);
1831
1832 if (p >= handle_tlbm_end)
1833 panic("TLB modify handler fastpath space exceeded");
1834
1835 uasm_resolve_relocs(relocs, labels);
1836 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
1837 (unsigned int)(p - handle_tlbm));
1838
1839 dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_size);
1840 }
1841 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
1842
1843 /*
1844 * R4000 style TLB load/store/modify handlers.
1845 */
1846 static struct work_registers
1847 build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
1848 struct uasm_reloc **r)
1849 {
1850 struct work_registers wr = build_get_work_registers(p);
1851
1852 #ifdef CONFIG_64BIT
1853 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
1854 #else
1855 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
1856 #endif
1857
1858 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1859 /*
1860 * For huge tlb entries, pmd doesn't contain an address but
1861 * instead contains the tlb pte. Check the PAGE_HUGE bit and
1862 * see if we need to jump to huge tlb processing.
1863 */
1864 build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update);
1865 #endif
1866
1867 UASM_i_MFC0(p, wr.r1, C0_BADVADDR);
1868 UASM_i_LW(p, wr.r2, 0, wr.r2);
1869 UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
1870 uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
1871 UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1);
1872
1873 #ifdef CONFIG_SMP
1874 uasm_l_smp_pgtable_change(l, *p);
1875 #endif
1876 iPTE_LW(p, wr.r1, wr.r2); /* get even pte */
1877 if (!m4kc_tlbp_war()) {
1878 build_tlb_probe_entry(p);
1879 if (cpu_has_htw) {
1880 /* race condition happens, leaving */
1881 uasm_i_ehb(p);
1882 uasm_i_mfc0(p, wr.r3, C0_INDEX);
1883 uasm_il_bltz(p, r, wr.r3, label_leave);
1884 uasm_i_nop(p);
1885 }
1886 }
1887 return wr;
1888 }
1889
1890 static void
1891 build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l,
1892 struct uasm_reloc **r, unsigned int tmp,
1893 unsigned int ptr)
1894 {
1895 uasm_i_ori(p, ptr, ptr, sizeof(pte_t));
1896 uasm_i_xori(p, ptr, ptr, sizeof(pte_t));
1897 build_update_entries(p, tmp, ptr);
1898 build_tlb_write_entry(p, l, r, tlb_indexed);
1899 uasm_l_leave(l, *p);
1900 build_restore_work_registers(p);
1901 uasm_i_eret(p); /* return from trap */
1902
1903 #ifdef CONFIG_64BIT
1904 build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill);
1905 #endif
1906 }
1907
1908 static void build_r4000_tlb_load_handler(void)
1909 {
1910 u32 *p = handle_tlbl;
1911 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl;
1912 struct uasm_label *l = labels;
1913 struct uasm_reloc *r = relocs;
1914 struct work_registers wr;
1915
1916 memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0]));
1917 memset(labels, 0, sizeof(labels));
1918 memset(relocs, 0, sizeof(relocs));
1919
1920 if (bcm1250_m3_war()) {
1921 unsigned int segbits = 44;
1922
1923 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1924 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
1925 uasm_i_xor(&p, K0, K0, K1);
1926 uasm_i_dsrl_safe(&p, K1, K0, 62);
1927 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
1928 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
1929 uasm_i_or(&p, K0, K0, K1);
1930 uasm_il_bnez(&p, &r, K0, label_leave);
1931 /* No need for uasm_i_nop */
1932 }
1933
1934 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
1935 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
1936 if (m4kc_tlbp_war())
1937 build_tlb_probe_entry(&p);
1938
1939 if (cpu_has_rixi && !cpu_has_rixiex) {
1940 /*
1941 * If the page is not _PAGE_VALID, RI or XI could not
1942 * have triggered it. Skip the expensive test..
1943 */
1944 if (use_bbit_insns()) {
1945 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
1946 label_tlbl_goaround1);
1947 } else {
1948 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
1949 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1);
1950 }
1951 uasm_i_nop(&p);
1952
1953 uasm_i_tlbr(&p);
1954
1955 switch (current_cpu_type()) {
1956 default:
1957 if (cpu_has_mips_r2_exec_hazard) {
1958 uasm_i_ehb(&p);
1959
1960 case CPU_CAVIUM_OCTEON:
1961 case CPU_CAVIUM_OCTEON_PLUS:
1962 case CPU_CAVIUM_OCTEON2:
1963 break;
1964 }
1965 }
1966
1967 /* Examine entrylo 0 or 1 based on ptr. */
1968 if (use_bbit_insns()) {
1969 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
1970 } else {
1971 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
1972 uasm_i_beqz(&p, wr.r3, 8);
1973 }
1974 /* load it in the delay slot*/
1975 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
1976 /* load it if ptr is odd */
1977 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
1978 /*
1979 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
1980 * XI must have triggered it.
1981 */
1982 if (use_bbit_insns()) {
1983 uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl);
1984 uasm_i_nop(&p);
1985 uasm_l_tlbl_goaround1(&l, p);
1986 } else {
1987 uasm_i_andi(&p, wr.r3, wr.r3, 2);
1988 uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl);
1989 uasm_i_nop(&p);
1990 }
1991 uasm_l_tlbl_goaround1(&l, p);
1992 }
1993 build_make_valid(&p, &r, wr.r1, wr.r2);
1994 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
1995
1996 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1997 /*
1998 * This is the entry point when build_r4000_tlbchange_handler_head
1999 * spots a huge page.
2000 */
2001 uasm_l_tlb_huge_update(&l, p);
2002 iPTE_LW(&p, wr.r1, wr.r2);
2003 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
2004 build_tlb_probe_entry(&p);
2005
2006 if (cpu_has_rixi && !cpu_has_rixiex) {
2007 /*
2008 * If the page is not _PAGE_VALID, RI or XI could not
2009 * have triggered it. Skip the expensive test..
2010 */
2011 if (use_bbit_insns()) {
2012 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
2013 label_tlbl_goaround2);
2014 } else {
2015 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
2016 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
2017 }
2018 uasm_i_nop(&p);
2019
2020 uasm_i_tlbr(&p);
2021
2022 switch (current_cpu_type()) {
2023 default:
2024 if (cpu_has_mips_r2_exec_hazard) {
2025 uasm_i_ehb(&p);
2026
2027 case CPU_CAVIUM_OCTEON:
2028 case CPU_CAVIUM_OCTEON_PLUS:
2029 case CPU_CAVIUM_OCTEON2:
2030 break;
2031 }
2032 }
2033
2034 /* Examine entrylo 0 or 1 based on ptr. */
2035 if (use_bbit_insns()) {
2036 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
2037 } else {
2038 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
2039 uasm_i_beqz(&p, wr.r3, 8);
2040 }
2041 /* load it in the delay slot*/
2042 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
2043 /* load it if ptr is odd */
2044 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
2045 /*
2046 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
2047 * XI must have triggered it.
2048 */
2049 if (use_bbit_insns()) {
2050 uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2);
2051 } else {
2052 uasm_i_andi(&p, wr.r3, wr.r3, 2);
2053 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
2054 }
2055 if (PM_DEFAULT_MASK == 0)
2056 uasm_i_nop(&p);
2057 /*
2058 * We clobbered C0_PAGEMASK, restore it. On the other branch
2059 * it is restored in build_huge_tlb_write_entry.
2060 */
2061 build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0);
2062
2063 uasm_l_tlbl_goaround2(&l, p);
2064 }
2065 uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID));
2066 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
2067 #endif
2068
2069 uasm_l_nopage_tlbl(&l, p);
2070 build_restore_work_registers(&p);
2071 #ifdef CONFIG_CPU_MICROMIPS
2072 if ((unsigned long)tlb_do_page_fault_0 & 1) {
2073 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0));
2074 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0));
2075 uasm_i_jr(&p, K0);
2076 } else
2077 #endif
2078 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
2079 uasm_i_nop(&p);
2080
2081 if (p >= handle_tlbl_end)
2082 panic("TLB load handler fastpath space exceeded");
2083
2084 uasm_resolve_relocs(relocs, labels);
2085 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
2086 (unsigned int)(p - handle_tlbl));
2087
2088 dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_size);
2089 }
2090
2091 static void build_r4000_tlb_store_handler(void)
2092 {
2093 u32 *p = handle_tlbs;
2094 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs;
2095 struct uasm_label *l = labels;
2096 struct uasm_reloc *r = relocs;
2097 struct work_registers wr;
2098
2099 memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0]));
2100 memset(labels, 0, sizeof(labels));
2101 memset(relocs, 0, sizeof(relocs));
2102
2103 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2104 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2105 if (m4kc_tlbp_war())
2106 build_tlb_probe_entry(&p);
2107 build_make_write(&p, &r, wr.r1, wr.r2);
2108 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2109
2110 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2111 /*
2112 * This is the entry point when
2113 * build_r4000_tlbchange_handler_head spots a huge page.
2114 */
2115 uasm_l_tlb_huge_update(&l, p);
2116 iPTE_LW(&p, wr.r1, wr.r2);
2117 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2118 build_tlb_probe_entry(&p);
2119 uasm_i_ori(&p, wr.r1, wr.r1,
2120 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2121 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
2122 #endif
2123
2124 uasm_l_nopage_tlbs(&l, p);
2125 build_restore_work_registers(&p);
2126 #ifdef CONFIG_CPU_MICROMIPS
2127 if ((unsigned long)tlb_do_page_fault_1 & 1) {
2128 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
2129 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
2130 uasm_i_jr(&p, K0);
2131 } else
2132 #endif
2133 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2134 uasm_i_nop(&p);
2135
2136 if (p >= handle_tlbs_end)
2137 panic("TLB store handler fastpath space exceeded");
2138
2139 uasm_resolve_relocs(relocs, labels);
2140 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
2141 (unsigned int)(p - handle_tlbs));
2142
2143 dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_size);
2144 }
2145
2146 static void build_r4000_tlb_modify_handler(void)
2147 {
2148 u32 *p = handle_tlbm;
2149 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm;
2150 struct uasm_label *l = labels;
2151 struct uasm_reloc *r = relocs;
2152 struct work_registers wr;
2153
2154 memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0]));
2155 memset(labels, 0, sizeof(labels));
2156 memset(relocs, 0, sizeof(relocs));
2157
2158 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2159 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2160 if (m4kc_tlbp_war())
2161 build_tlb_probe_entry(&p);
2162 /* Present and writable bits set, set accessed and dirty bits. */
2163 build_make_write(&p, &r, wr.r1, wr.r2);
2164 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2165
2166 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2167 /*
2168 * This is the entry point when
2169 * build_r4000_tlbchange_handler_head spots a huge page.
2170 */
2171 uasm_l_tlb_huge_update(&l, p);
2172 iPTE_LW(&p, wr.r1, wr.r2);
2173 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2174 build_tlb_probe_entry(&p);
2175 uasm_i_ori(&p, wr.r1, wr.r1,
2176 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2177 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
2178 #endif
2179
2180 uasm_l_nopage_tlbm(&l, p);
2181 build_restore_work_registers(&p);
2182 #ifdef CONFIG_CPU_MICROMIPS
2183 if ((unsigned long)tlb_do_page_fault_1 & 1) {
2184 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
2185 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
2186 uasm_i_jr(&p, K0);
2187 } else
2188 #endif
2189 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2190 uasm_i_nop(&p);
2191
2192 if (p >= handle_tlbm_end)
2193 panic("TLB modify handler fastpath space exceeded");
2194
2195 uasm_resolve_relocs(relocs, labels);
2196 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
2197 (unsigned int)(p - handle_tlbm));
2198
2199 dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_size);
2200 }
2201
2202 static void flush_tlb_handlers(void)
2203 {
2204 local_flush_icache_range((unsigned long)handle_tlbl,
2205 (unsigned long)handle_tlbl_end);
2206 local_flush_icache_range((unsigned long)handle_tlbs,
2207 (unsigned long)handle_tlbs_end);
2208 local_flush_icache_range((unsigned long)handle_tlbm,
2209 (unsigned long)handle_tlbm_end);
2210 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd,
2211 (unsigned long)tlbmiss_handler_setup_pgd_end);
2212 }
2213
2214 static void print_htw_config(void)
2215 {
2216 unsigned long config;
2217 unsigned int pwctl;
2218 const int field = 2 * sizeof(unsigned long);
2219
2220 config = read_c0_pwfield();
2221 pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n",
2222 field, config,
2223 (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT,
2224 (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT,
2225 (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT,
2226 (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT,
2227 (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT);
2228
2229 config = read_c0_pwsize();
2230 pr_debug("PWSize (0x%0*lx): GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n",
2231 field, config,
2232 (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT,
2233 (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT,
2234 (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT,
2235 (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT,
2236 (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT);
2237
2238 pwctl = read_c0_pwctl();
2239 pr_debug("PWCtl (0x%x): PWEn: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n",
2240 pwctl,
2241 (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT,
2242 (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT,
2243 (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT,
2244 (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT);
2245 }
2246
2247 static void config_htw_params(void)
2248 {
2249 unsigned long pwfield, pwsize, ptei;
2250 unsigned int config;
2251
2252 /*
2253 * We are using 2-level page tables, so we only need to
2254 * setup GDW and PTW appropriately. UDW and MDW will remain 0.
2255 * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to
2256 * write values less than 0xc in these fields because the entire
2257 * write will be dropped. As a result of which, we must preserve
2258 * the original reset values and overwrite only what we really want.
2259 */
2260
2261 pwfield = read_c0_pwfield();
2262 /* re-initialize the GDI field */
2263 pwfield &= ~MIPS_PWFIELD_GDI_MASK;
2264 pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT;
2265 /* re-initialize the PTI field including the even/odd bit */
2266 pwfield &= ~MIPS_PWFIELD_PTI_MASK;
2267 pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT;
2268 /* Set the PTEI right shift */
2269 ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT;
2270 pwfield |= ptei;
2271 write_c0_pwfield(pwfield);
2272 /* Check whether the PTEI value is supported */
2273 back_to_back_c0_hazard();
2274 pwfield = read_c0_pwfield();
2275 if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT)
2276 != ptei) {
2277 pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled",
2278 ptei);
2279 /*
2280 * Drop option to avoid HTW being enabled via another path
2281 * (eg htw_reset())
2282 */
2283 current_cpu_data.options &= ~MIPS_CPU_HTW;
2284 return;
2285 }
2286
2287 pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT;
2288 pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT;
2289 write_c0_pwsize(pwsize);
2290
2291 /* Make sure everything is set before we enable the HTW */
2292 back_to_back_c0_hazard();
2293
2294 /* Enable HTW and disable the rest of the pwctl fields */
2295 config = 1 << MIPS_PWCTL_PWEN_SHIFT;
2296 write_c0_pwctl(config);
2297 pr_info("Hardware Page Table Walker enabled\n");
2298
2299 print_htw_config();
2300 }
2301
2302 void build_tlb_refill_handler(void)
2303 {
2304 /*
2305 * The refill handler is generated per-CPU, multi-node systems
2306 * may have local storage for it. The other handlers are only
2307 * needed once.
2308 */
2309 static int run_once = 0;
2310
2311 output_pgtable_bits_defines();
2312
2313 #ifdef CONFIG_64BIT
2314 check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
2315 #endif
2316
2317 switch (current_cpu_type()) {
2318 case CPU_R2000:
2319 case CPU_R3000:
2320 case CPU_R3000A:
2321 case CPU_R3081E:
2322 case CPU_TX3912:
2323 case CPU_TX3922:
2324 case CPU_TX3927:
2325 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
2326 if (cpu_has_local_ebase)
2327 build_r3000_tlb_refill_handler();
2328 if (!run_once) {
2329 if (!cpu_has_local_ebase)
2330 build_r3000_tlb_refill_handler();
2331 build_setup_pgd();
2332 build_r3000_tlb_load_handler();
2333 build_r3000_tlb_store_handler();
2334 build_r3000_tlb_modify_handler();
2335 flush_tlb_handlers();
2336 run_once++;
2337 }
2338 #else
2339 panic("No R3000 TLB refill handler");
2340 #endif
2341 break;
2342
2343 case CPU_R6000:
2344 case CPU_R6000A:
2345 panic("No R6000 TLB refill handler yet");
2346 break;
2347
2348 case CPU_R8000:
2349 panic("No R8000 TLB refill handler yet");
2350 break;
2351
2352 default:
2353 if (!run_once) {
2354 scratch_reg = allocate_kscratch();
2355 build_setup_pgd();
2356 build_r4000_tlb_load_handler();
2357 build_r4000_tlb_store_handler();
2358 build_r4000_tlb_modify_handler();
2359 if (!cpu_has_local_ebase)
2360 build_r4000_tlb_refill_handler();
2361 flush_tlb_handlers();
2362 run_once++;
2363 }
2364 if (cpu_has_local_ebase)
2365 build_r4000_tlb_refill_handler();
2366 if (cpu_has_htw)
2367 config_htw_params();
2368
2369 }
2370 }
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