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perf/x86/amd/ibs: Update IBS MSRs and feature definitions
[mirror_ubuntu-bionic-kernel.git] / arch / mips / mm / tlbex.c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Synthesize TLB refill handlers at runtime.
7 *
8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
11 * Copyright (C) 2008, 2009 Cavium Networks, Inc.
12 * Copyright (C) 2011 MIPS Technologies, Inc.
13 *
14 * ... and the days got worse and worse and now you see
15 * I've gone completly out of my mind.
16 *
17 * They're coming to take me a away haha
18 * they're coming to take me a away hoho hihi haha
19 * to the funny farm where code is beautiful all the time ...
20 *
21 * (Condolences to Napoleon XIV)
22 */
23
24 #include <linux/bug.h>
25 #include <linux/kernel.h>
26 #include <linux/types.h>
27 #include <linux/smp.h>
28 #include <linux/string.h>
29 #include <linux/cache.h>
30
31 #include <asm/cacheflush.h>
32 #include <asm/cpu-type.h>
33 #include <asm/pgtable.h>
34 #include <asm/war.h>
35 #include <asm/uasm.h>
36 #include <asm/setup.h>
37
38 /*
39 * TLB load/store/modify handlers.
40 *
41 * Only the fastpath gets synthesized at runtime, the slowpath for
42 * do_page_fault remains normal asm.
43 */
44 extern void tlb_do_page_fault_0(void);
45 extern void tlb_do_page_fault_1(void);
46
47 struct work_registers {
48 int r1;
49 int r2;
50 int r3;
51 };
52
53 struct tlb_reg_save {
54 unsigned long a;
55 unsigned long b;
56 } ____cacheline_aligned_in_smp;
57
58 static struct tlb_reg_save handler_reg_save[NR_CPUS];
59
60 static inline int r45k_bvahwbug(void)
61 {
62 /* XXX: We should probe for the presence of this bug, but we don't. */
63 return 0;
64 }
65
66 static inline int r4k_250MHZhwbug(void)
67 {
68 /* XXX: We should probe for the presence of this bug, but we don't. */
69 return 0;
70 }
71
72 static inline int __maybe_unused bcm1250_m3_war(void)
73 {
74 return BCM1250_M3_WAR;
75 }
76
77 static inline int __maybe_unused r10000_llsc_war(void)
78 {
79 return R10000_LLSC_WAR;
80 }
81
82 static int use_bbit_insns(void)
83 {
84 switch (current_cpu_type()) {
85 case CPU_CAVIUM_OCTEON:
86 case CPU_CAVIUM_OCTEON_PLUS:
87 case CPU_CAVIUM_OCTEON2:
88 case CPU_CAVIUM_OCTEON3:
89 return 1;
90 default:
91 return 0;
92 }
93 }
94
95 static int use_lwx_insns(void)
96 {
97 switch (current_cpu_type()) {
98 case CPU_CAVIUM_OCTEON2:
99 case CPU_CAVIUM_OCTEON3:
100 return 1;
101 default:
102 return 0;
103 }
104 }
105 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
106 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
107 static bool scratchpad_available(void)
108 {
109 return true;
110 }
111 static int scratchpad_offset(int i)
112 {
113 /*
114 * CVMSEG starts at address -32768 and extends for
115 * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines.
116 */
117 i += 1; /* Kernel use starts at the top and works down. */
118 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768;
119 }
120 #else
121 static bool scratchpad_available(void)
122 {
123 return false;
124 }
125 static int scratchpad_offset(int i)
126 {
127 BUG();
128 /* Really unreachable, but evidently some GCC want this. */
129 return 0;
130 }
131 #endif
132 /*
133 * Found by experiment: At least some revisions of the 4kc throw under
134 * some circumstances a machine check exception, triggered by invalid
135 * values in the index register. Delaying the tlbp instruction until
136 * after the next branch, plus adding an additional nop in front of
137 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
138 * why; it's not an issue caused by the core RTL.
139 *
140 */
141 static int m4kc_tlbp_war(void)
142 {
143 return (current_cpu_data.processor_id & 0xffff00) ==
144 (PRID_COMP_MIPS | PRID_IMP_4KC);
145 }
146
147 /* Handle labels (which must be positive integers). */
148 enum label_id {
149 label_second_part = 1,
150 label_leave,
151 label_vmalloc,
152 label_vmalloc_done,
153 label_tlbw_hazard_0,
154 label_split = label_tlbw_hazard_0 + 8,
155 label_tlbl_goaround1,
156 label_tlbl_goaround2,
157 label_nopage_tlbl,
158 label_nopage_tlbs,
159 label_nopage_tlbm,
160 label_smp_pgtable_change,
161 label_r3000_write_probe_fail,
162 label_large_segbits_fault,
163 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
164 label_tlb_huge_update,
165 #endif
166 };
167
168 UASM_L_LA(_second_part)
169 UASM_L_LA(_leave)
170 UASM_L_LA(_vmalloc)
171 UASM_L_LA(_vmalloc_done)
172 /* _tlbw_hazard_x is handled differently. */
173 UASM_L_LA(_split)
174 UASM_L_LA(_tlbl_goaround1)
175 UASM_L_LA(_tlbl_goaround2)
176 UASM_L_LA(_nopage_tlbl)
177 UASM_L_LA(_nopage_tlbs)
178 UASM_L_LA(_nopage_tlbm)
179 UASM_L_LA(_smp_pgtable_change)
180 UASM_L_LA(_r3000_write_probe_fail)
181 UASM_L_LA(_large_segbits_fault)
182 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
183 UASM_L_LA(_tlb_huge_update)
184 #endif
185
186 static int hazard_instance;
187
188 static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance)
189 {
190 switch (instance) {
191 case 0 ... 7:
192 uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance);
193 return;
194 default:
195 BUG();
196 }
197 }
198
199 static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance)
200 {
201 switch (instance) {
202 case 0 ... 7:
203 uasm_build_label(l, *p, label_tlbw_hazard_0 + instance);
204 break;
205 default:
206 BUG();
207 }
208 }
209
210 /*
211 * pgtable bits are assigned dynamically depending on processor feature
212 * and statically based on kernel configuration. This spits out the actual
213 * values the kernel is using. Required to make sense from disassembled
214 * TLB exception handlers.
215 */
216 static void output_pgtable_bits_defines(void)
217 {
218 #define pr_define(fmt, ...) \
219 pr_debug("#define " fmt, ##__VA_ARGS__)
220
221 pr_debug("#include <asm/asm.h>\n");
222 pr_debug("#include <asm/regdef.h>\n");
223 pr_debug("\n");
224
225 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT);
226 pr_define("_PAGE_READ_SHIFT %d\n", _PAGE_READ_SHIFT);
227 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT);
228 pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT);
229 pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT);
230 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
231 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT);
232 pr_define("_PAGE_SPLITTING_SHIFT %d\n", _PAGE_SPLITTING_SHIFT);
233 #endif
234 if (cpu_has_rixi) {
235 #ifdef _PAGE_NO_EXEC_SHIFT
236 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT);
237 #endif
238 #ifdef _PAGE_NO_READ_SHIFT
239 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT);
240 #endif
241 }
242 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT);
243 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT);
244 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT);
245 pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT);
246 pr_debug("\n");
247 }
248
249 static inline void dump_handler(const char *symbol, const u32 *handler, int count)
250 {
251 int i;
252
253 pr_debug("LEAF(%s)\n", symbol);
254
255 pr_debug("\t.set push\n");
256 pr_debug("\t.set noreorder\n");
257
258 for (i = 0; i < count; i++)
259 pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]);
260
261 pr_debug("\t.set\tpop\n");
262
263 pr_debug("\tEND(%s)\n", symbol);
264 }
265
266 /* The only general purpose registers allowed in TLB handlers. */
267 #define K0 26
268 #define K1 27
269
270 /* Some CP0 registers */
271 #define C0_INDEX 0, 0
272 #define C0_ENTRYLO0 2, 0
273 #define C0_TCBIND 2, 2
274 #define C0_ENTRYLO1 3, 0
275 #define C0_CONTEXT 4, 0
276 #define C0_PAGEMASK 5, 0
277 #define C0_BADVADDR 8, 0
278 #define C0_ENTRYHI 10, 0
279 #define C0_EPC 14, 0
280 #define C0_XCONTEXT 20, 0
281
282 #ifdef CONFIG_64BIT
283 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
284 #else
285 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT)
286 #endif
287
288 /* The worst case length of the handler is around 18 instructions for
289 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
290 * Maximum space available is 32 instructions for R3000 and 64
291 * instructions for R4000.
292 *
293 * We deliberately chose a buffer size of 128, so we won't scribble
294 * over anything important on overflow before we panic.
295 */
296 static u32 tlb_handler[128];
297
298 /* simply assume worst case size for labels and relocs */
299 static struct uasm_label labels[128];
300 static struct uasm_reloc relocs[128];
301
302 static int check_for_high_segbits;
303
304 static unsigned int kscratch_used_mask;
305
306 static inline int __maybe_unused c0_kscratch(void)
307 {
308 switch (current_cpu_type()) {
309 case CPU_XLP:
310 case CPU_XLR:
311 return 22;
312 default:
313 return 31;
314 }
315 }
316
317 static int allocate_kscratch(void)
318 {
319 int r;
320 unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask;
321
322 r = ffs(a);
323
324 if (r == 0)
325 return -1;
326
327 r--; /* make it zero based */
328
329 kscratch_used_mask |= (1 << r);
330
331 return r;
332 }
333
334 static int scratch_reg;
335 static int pgd_reg;
336 enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch};
337
338 static struct work_registers build_get_work_registers(u32 **p)
339 {
340 struct work_registers r;
341
342 if (scratch_reg >= 0) {
343 /* Save in CPU local C0_KScratch? */
344 UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg);
345 r.r1 = K0;
346 r.r2 = K1;
347 r.r3 = 1;
348 return r;
349 }
350
351 if (num_possible_cpus() > 1) {
352 /* Get smp_processor_id */
353 UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG);
354 UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT);
355
356 /* handler_reg_save index in K0 */
357 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save)));
358
359 UASM_i_LA(p, K1, (long)&handler_reg_save);
360 UASM_i_ADDU(p, K0, K0, K1);
361 } else {
362 UASM_i_LA(p, K0, (long)&handler_reg_save);
363 }
364 /* K0 now points to save area, save $1 and $2 */
365 UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0);
366 UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0);
367
368 r.r1 = K1;
369 r.r2 = 1;
370 r.r3 = 2;
371 return r;
372 }
373
374 static void build_restore_work_registers(u32 **p)
375 {
376 if (scratch_reg >= 0) {
377 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
378 return;
379 }
380 /* K0 already points to save area, restore $1 and $2 */
381 UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0);
382 UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0);
383 }
384
385 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
386
387 /*
388 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
389 * we cannot do r3000 under these circumstances.
390 *
391 * Declare pgd_current here instead of including mmu_context.h to avoid type
392 * conflicts for tlbmiss_handler_setup_pgd
393 */
394 extern unsigned long pgd_current[];
395
396 /*
397 * The R3000 TLB handler is simple.
398 */
399 static void build_r3000_tlb_refill_handler(void)
400 {
401 long pgdc = (long)pgd_current;
402 u32 *p;
403
404 memset(tlb_handler, 0, sizeof(tlb_handler));
405 p = tlb_handler;
406
407 uasm_i_mfc0(&p, K0, C0_BADVADDR);
408 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */
409 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1);
410 uasm_i_srl(&p, K0, K0, 22); /* load delay */
411 uasm_i_sll(&p, K0, K0, 2);
412 uasm_i_addu(&p, K1, K1, K0);
413 uasm_i_mfc0(&p, K0, C0_CONTEXT);
414 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */
415 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */
416 uasm_i_addu(&p, K1, K1, K0);
417 uasm_i_lw(&p, K0, 0, K1);
418 uasm_i_nop(&p); /* load delay */
419 uasm_i_mtc0(&p, K0, C0_ENTRYLO0);
420 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
421 uasm_i_tlbwr(&p); /* cp0 delay */
422 uasm_i_jr(&p, K1);
423 uasm_i_rfe(&p); /* branch delay */
424
425 if (p > tlb_handler + 32)
426 panic("TLB refill handler space exceeded");
427
428 pr_debug("Wrote TLB refill handler (%u instructions).\n",
429 (unsigned int)(p - tlb_handler));
430
431 memcpy((void *)ebase, tlb_handler, 0x80);
432 local_flush_icache_range(ebase, ebase + 0x80);
433
434 dump_handler("r3000_tlb_refill", (u32 *)ebase, 32);
435 }
436 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
437
438 /*
439 * The R4000 TLB handler is much more complicated. We have two
440 * consecutive handler areas with 32 instructions space each.
441 * Since they aren't used at the same time, we can overflow in the
442 * other one.To keep things simple, we first assume linear space,
443 * then we relocate it to the final handler layout as needed.
444 */
445 static u32 final_handler[64];
446
447 /*
448 * Hazards
449 *
450 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
451 * 2. A timing hazard exists for the TLBP instruction.
452 *
453 * stalling_instruction
454 * TLBP
455 *
456 * The JTLB is being read for the TLBP throughout the stall generated by the
457 * previous instruction. This is not really correct as the stalling instruction
458 * can modify the address used to access the JTLB. The failure symptom is that
459 * the TLBP instruction will use an address created for the stalling instruction
460 * and not the address held in C0_ENHI and thus report the wrong results.
461 *
462 * The software work-around is to not allow the instruction preceding the TLBP
463 * to stall - make it an NOP or some other instruction guaranteed not to stall.
464 *
465 * Errata 2 will not be fixed. This errata is also on the R5000.
466 *
467 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
468 */
469 static void __maybe_unused build_tlb_probe_entry(u32 **p)
470 {
471 switch (current_cpu_type()) {
472 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */
473 case CPU_R4600:
474 case CPU_R4700:
475 case CPU_R5000:
476 case CPU_NEVADA:
477 uasm_i_nop(p);
478 uasm_i_tlbp(p);
479 break;
480
481 default:
482 uasm_i_tlbp(p);
483 break;
484 }
485 }
486
487 /*
488 * Write random or indexed TLB entry, and care about the hazards from
489 * the preceding mtc0 and for the following eret.
490 */
491 enum tlb_write_entry { tlb_random, tlb_indexed };
492
493 static void build_tlb_write_entry(u32 **p, struct uasm_label **l,
494 struct uasm_reloc **r,
495 enum tlb_write_entry wmode)
496 {
497 void(*tlbw)(u32 **) = NULL;
498
499 switch (wmode) {
500 case tlb_random: tlbw = uasm_i_tlbwr; break;
501 case tlb_indexed: tlbw = uasm_i_tlbwi; break;
502 }
503
504 if (cpu_has_mips_r2) {
505 /*
506 * The architecture spec says an ehb is required here,
507 * but a number of cores do not have the hazard and
508 * using an ehb causes an expensive pipeline stall.
509 */
510 switch (current_cpu_type()) {
511 case CPU_M14KC:
512 case CPU_74K:
513 case CPU_1074K:
514 case CPU_PROAPTIV:
515 case CPU_P5600:
516 case CPU_M5150:
517 break;
518
519 default:
520 uasm_i_ehb(p);
521 break;
522 }
523 tlbw(p);
524 return;
525 }
526
527 switch (current_cpu_type()) {
528 case CPU_R4000PC:
529 case CPU_R4000SC:
530 case CPU_R4000MC:
531 case CPU_R4400PC:
532 case CPU_R4400SC:
533 case CPU_R4400MC:
534 /*
535 * This branch uses up a mtc0 hazard nop slot and saves
536 * two nops after the tlbw instruction.
537 */
538 uasm_bgezl_hazard(p, r, hazard_instance);
539 tlbw(p);
540 uasm_bgezl_label(l, p, hazard_instance);
541 hazard_instance++;
542 uasm_i_nop(p);
543 break;
544
545 case CPU_R4600:
546 case CPU_R4700:
547 uasm_i_nop(p);
548 tlbw(p);
549 uasm_i_nop(p);
550 break;
551
552 case CPU_R5000:
553 case CPU_NEVADA:
554 uasm_i_nop(p); /* QED specifies 2 nops hazard */
555 uasm_i_nop(p); /* QED specifies 2 nops hazard */
556 tlbw(p);
557 break;
558
559 case CPU_R4300:
560 case CPU_5KC:
561 case CPU_TX49XX:
562 case CPU_PR4450:
563 case CPU_XLR:
564 uasm_i_nop(p);
565 tlbw(p);
566 break;
567
568 case CPU_R10000:
569 case CPU_R12000:
570 case CPU_R14000:
571 case CPU_4KC:
572 case CPU_4KEC:
573 case CPU_M14KC:
574 case CPU_M14KEC:
575 case CPU_SB1:
576 case CPU_SB1A:
577 case CPU_4KSC:
578 case CPU_20KC:
579 case CPU_25KF:
580 case CPU_BMIPS32:
581 case CPU_BMIPS3300:
582 case CPU_BMIPS4350:
583 case CPU_BMIPS4380:
584 case CPU_BMIPS5000:
585 case CPU_LOONGSON2:
586 case CPU_LOONGSON3:
587 case CPU_R5500:
588 if (m4kc_tlbp_war())
589 uasm_i_nop(p);
590 case CPU_ALCHEMY:
591 tlbw(p);
592 break;
593
594 case CPU_RM7000:
595 uasm_i_nop(p);
596 uasm_i_nop(p);
597 uasm_i_nop(p);
598 uasm_i_nop(p);
599 tlbw(p);
600 break;
601
602 case CPU_VR4111:
603 case CPU_VR4121:
604 case CPU_VR4122:
605 case CPU_VR4181:
606 case CPU_VR4181A:
607 uasm_i_nop(p);
608 uasm_i_nop(p);
609 tlbw(p);
610 uasm_i_nop(p);
611 uasm_i_nop(p);
612 break;
613
614 case CPU_VR4131:
615 case CPU_VR4133:
616 case CPU_R5432:
617 uasm_i_nop(p);
618 uasm_i_nop(p);
619 tlbw(p);
620 break;
621
622 case CPU_JZRISC:
623 tlbw(p);
624 uasm_i_nop(p);
625 break;
626
627 default:
628 panic("No TLB refill handler yet (CPU type: %d)",
629 current_cpu_type());
630 break;
631 }
632 }
633
634 static __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
635 unsigned int reg)
636 {
637 if (cpu_has_rixi) {
638 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL));
639 } else {
640 #ifdef CONFIG_64BIT_PHYS_ADDR
641 uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL));
642 #else
643 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL));
644 #endif
645 }
646 }
647
648 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
649
650 static void build_restore_pagemask(u32 **p, struct uasm_reloc **r,
651 unsigned int tmp, enum label_id lid,
652 int restore_scratch)
653 {
654 if (restore_scratch) {
655 /* Reset default page size */
656 if (PM_DEFAULT_MASK >> 16) {
657 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
658 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
659 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
660 uasm_il_b(p, r, lid);
661 } else if (PM_DEFAULT_MASK) {
662 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
663 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
664 uasm_il_b(p, r, lid);
665 } else {
666 uasm_i_mtc0(p, 0, C0_PAGEMASK);
667 uasm_il_b(p, r, lid);
668 }
669 if (scratch_reg >= 0)
670 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
671 else
672 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
673 } else {
674 /* Reset default page size */
675 if (PM_DEFAULT_MASK >> 16) {
676 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
677 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
678 uasm_il_b(p, r, lid);
679 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
680 } else if (PM_DEFAULT_MASK) {
681 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
682 uasm_il_b(p, r, lid);
683 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
684 } else {
685 uasm_il_b(p, r, lid);
686 uasm_i_mtc0(p, 0, C0_PAGEMASK);
687 }
688 }
689 }
690
691 static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l,
692 struct uasm_reloc **r,
693 unsigned int tmp,
694 enum tlb_write_entry wmode,
695 int restore_scratch)
696 {
697 /* Set huge page tlb entry size */
698 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16);
699 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff);
700 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
701
702 build_tlb_write_entry(p, l, r, wmode);
703
704 build_restore_pagemask(p, r, tmp, label_leave, restore_scratch);
705 }
706
707 /*
708 * Check if Huge PTE is present, if so then jump to LABEL.
709 */
710 static void
711 build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp,
712 unsigned int pmd, int lid)
713 {
714 UASM_i_LW(p, tmp, 0, pmd);
715 if (use_bbit_insns()) {
716 uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid);
717 } else {
718 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE);
719 uasm_il_bnez(p, r, tmp, lid);
720 }
721 }
722
723 static void build_huge_update_entries(u32 **p, unsigned int pte,
724 unsigned int tmp)
725 {
726 int small_sequence;
727
728 /*
729 * A huge PTE describes an area the size of the
730 * configured huge page size. This is twice the
731 * of the large TLB entry size we intend to use.
732 * A TLB entry half the size of the configured
733 * huge page size is configured into entrylo0
734 * and entrylo1 to cover the contiguous huge PTE
735 * address space.
736 */
737 small_sequence = (HPAGE_SIZE >> 7) < 0x10000;
738
739 /* We can clobber tmp. It isn't used after this.*/
740 if (!small_sequence)
741 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16));
742
743 build_convert_pte_to_entrylo(p, pte);
744 UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */
745 /* convert to entrylo1 */
746 if (small_sequence)
747 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7);
748 else
749 UASM_i_ADDU(p, pte, pte, tmp);
750
751 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */
752 }
753
754 static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r,
755 struct uasm_label **l,
756 unsigned int pte,
757 unsigned int ptr)
758 {
759 #ifdef CONFIG_SMP
760 UASM_i_SC(p, pte, 0, ptr);
761 uasm_il_beqz(p, r, pte, label_tlb_huge_update);
762 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */
763 #else
764 UASM_i_SW(p, pte, 0, ptr);
765 #endif
766 build_huge_update_entries(p, pte, ptr);
767 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0);
768 }
769 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
770
771 #ifdef CONFIG_64BIT
772 /*
773 * TMP and PTR are scratch.
774 * TMP will be clobbered, PTR will hold the pmd entry.
775 */
776 static void
777 build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
778 unsigned int tmp, unsigned int ptr)
779 {
780 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
781 long pgdc = (long)pgd_current;
782 #endif
783 /*
784 * The vmalloc handling is not in the hotpath.
785 */
786 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
787
788 if (check_for_high_segbits) {
789 /*
790 * The kernel currently implicitely assumes that the
791 * MIPS SEGBITS parameter for the processor is
792 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never
793 * allocate virtual addresses outside the maximum
794 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But
795 * that doesn't prevent user code from accessing the
796 * higher xuseg addresses. Here, we make sure that
797 * everything but the lower xuseg addresses goes down
798 * the module_alloc/vmalloc path.
799 */
800 uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
801 uasm_il_bnez(p, r, ptr, label_vmalloc);
802 } else {
803 uasm_il_bltz(p, r, tmp, label_vmalloc);
804 }
805 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
806
807 if (pgd_reg != -1) {
808 /* pgd is in pgd_reg */
809 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
810 } else {
811 #if defined(CONFIG_MIPS_PGD_C0_CONTEXT)
812 /*
813 * &pgd << 11 stored in CONTEXT [23..63].
814 */
815 UASM_i_MFC0(p, ptr, C0_CONTEXT);
816
817 /* Clear lower 23 bits of context. */
818 uasm_i_dins(p, ptr, 0, 0, 23);
819
820 /* 1 0 1 0 1 << 6 xkphys cached */
821 uasm_i_ori(p, ptr, ptr, 0x540);
822 uasm_i_drotr(p, ptr, ptr, 11);
823 #elif defined(CONFIG_SMP)
824 UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG);
825 uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
826 UASM_i_LA_mostly(p, tmp, pgdc);
827 uasm_i_daddu(p, ptr, ptr, tmp);
828 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
829 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
830 #else
831 UASM_i_LA_mostly(p, ptr, pgdc);
832 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
833 #endif
834 }
835
836 uasm_l_vmalloc_done(l, *p);
837
838 /* get pgd offset in bytes */
839 uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3);
840
841 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
842 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
843 #ifndef __PAGETABLE_PMD_FOLDED
844 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
845 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */
846 uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
847 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
848 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
849 #endif
850 }
851
852 /*
853 * BVADDR is the faulting address, PTR is scratch.
854 * PTR will hold the pgd for vmalloc.
855 */
856 static void
857 build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
858 unsigned int bvaddr, unsigned int ptr,
859 enum vmalloc64_mode mode)
860 {
861 long swpd = (long)swapper_pg_dir;
862 int single_insn_swpd;
863 int did_vmalloc_branch = 0;
864
865 single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd);
866
867 uasm_l_vmalloc(l, *p);
868
869 if (mode != not_refill && check_for_high_segbits) {
870 if (single_insn_swpd) {
871 uasm_il_bltz(p, r, bvaddr, label_vmalloc_done);
872 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
873 did_vmalloc_branch = 1;
874 /* fall through */
875 } else {
876 uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault);
877 }
878 }
879 if (!did_vmalloc_branch) {
880 if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) {
881 uasm_il_b(p, r, label_vmalloc_done);
882 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
883 } else {
884 UASM_i_LA_mostly(p, ptr, swpd);
885 uasm_il_b(p, r, label_vmalloc_done);
886 if (uasm_in_compat_space_p(swpd))
887 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd));
888 else
889 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd));
890 }
891 }
892 if (mode != not_refill && check_for_high_segbits) {
893 uasm_l_large_segbits_fault(l, *p);
894 /*
895 * We get here if we are an xsseg address, or if we are
896 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary.
897 *
898 * Ignoring xsseg (assume disabled so would generate
899 * (address errors?), the only remaining possibility
900 * is the upper xuseg addresses. On processors with
901 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these
902 * addresses would have taken an address error. We try
903 * to mimic that here by taking a load/istream page
904 * fault.
905 */
906 UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0);
907 uasm_i_jr(p, ptr);
908
909 if (mode == refill_scratch) {
910 if (scratch_reg >= 0)
911 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
912 else
913 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
914 } else {
915 uasm_i_nop(p);
916 }
917 }
918 }
919
920 #else /* !CONFIG_64BIT */
921
922 /*
923 * TMP and PTR are scratch.
924 * TMP will be clobbered, PTR will hold the pgd entry.
925 */
926 static void __maybe_unused
927 build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
928 {
929 if (pgd_reg != -1) {
930 /* pgd is in pgd_reg */
931 uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg);
932 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
933 } else {
934 long pgdc = (long)pgd_current;
935
936 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
937 #ifdef CONFIG_SMP
938 uasm_i_mfc0(p, ptr, SMP_CPUID_REG);
939 UASM_i_LA_mostly(p, tmp, pgdc);
940 uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
941 uasm_i_addu(p, ptr, tmp, ptr);
942 #else
943 UASM_i_LA_mostly(p, ptr, pgdc);
944 #endif
945 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
946 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
947 }
948 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
949 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
950 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
951 }
952
953 #endif /* !CONFIG_64BIT */
954
955 static void build_adjust_context(u32 **p, unsigned int ctx)
956 {
957 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
958 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
959
960 switch (current_cpu_type()) {
961 case CPU_VR41XX:
962 case CPU_VR4111:
963 case CPU_VR4121:
964 case CPU_VR4122:
965 case CPU_VR4131:
966 case CPU_VR4181:
967 case CPU_VR4181A:
968 case CPU_VR4133:
969 shift += 2;
970 break;
971
972 default:
973 break;
974 }
975
976 if (shift)
977 UASM_i_SRL(p, ctx, ctx, shift);
978 uasm_i_andi(p, ctx, ctx, mask);
979 }
980
981 static void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
982 {
983 /*
984 * Bug workaround for the Nevada. It seems as if under certain
985 * circumstances the move from cp0_context might produce a
986 * bogus result when the mfc0 instruction and its consumer are
987 * in a different cacheline or a load instruction, probably any
988 * memory reference, is between them.
989 */
990 switch (current_cpu_type()) {
991 case CPU_NEVADA:
992 UASM_i_LW(p, ptr, 0, ptr);
993 GET_CONTEXT(p, tmp); /* get context reg */
994 break;
995
996 default:
997 GET_CONTEXT(p, tmp); /* get context reg */
998 UASM_i_LW(p, ptr, 0, ptr);
999 break;
1000 }
1001
1002 build_adjust_context(p, tmp);
1003 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */
1004 }
1005
1006 static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
1007 {
1008 /*
1009 * 64bit address support (36bit on a 32bit CPU) in a 32bit
1010 * Kernel is a special case. Only a few CPUs use it.
1011 */
1012 #ifdef CONFIG_64BIT_PHYS_ADDR
1013 if (cpu_has_64bits) {
1014 uasm_i_ld(p, tmp, 0, ptep); /* get even pte */
1015 uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
1016 if (cpu_has_rixi) {
1017 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
1018 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1019 UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL));
1020 } else {
1021 uasm_i_dsrl_safe(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */
1022 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1023 uasm_i_dsrl_safe(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */
1024 }
1025 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1026 } else {
1027 int pte_off_even = sizeof(pte_t) / 2;
1028 int pte_off_odd = pte_off_even + sizeof(pte_t);
1029
1030 /* The pte entries are pre-shifted */
1031 uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */
1032 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1033 uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */
1034 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1035 }
1036 #else
1037 UASM_i_LW(p, tmp, 0, ptep); /* get even pte */
1038 UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
1039 if (r45k_bvahwbug())
1040 build_tlb_probe_entry(p);
1041 if (cpu_has_rixi) {
1042 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
1043 if (r4k_250MHZhwbug())
1044 UASM_i_MTC0(p, 0, C0_ENTRYLO0);
1045 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1046 UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL));
1047 } else {
1048 UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */
1049 if (r4k_250MHZhwbug())
1050 UASM_i_MTC0(p, 0, C0_ENTRYLO0);
1051 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1052 UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */
1053 if (r45k_bvahwbug())
1054 uasm_i_mfc0(p, tmp, C0_INDEX);
1055 }
1056 if (r4k_250MHZhwbug())
1057 UASM_i_MTC0(p, 0, C0_ENTRYLO1);
1058 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1059 #endif
1060 }
1061
1062 struct mips_huge_tlb_info {
1063 int huge_pte;
1064 int restore_scratch;
1065 };
1066
1067 static struct mips_huge_tlb_info
1068 build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
1069 struct uasm_reloc **r, unsigned int tmp,
1070 unsigned int ptr, int c0_scratch_reg)
1071 {
1072 struct mips_huge_tlb_info rv;
1073 unsigned int even, odd;
1074 int vmalloc_branch_delay_filled = 0;
1075 const int scratch = 1; /* Our extra working register */
1076
1077 rv.huge_pte = scratch;
1078 rv.restore_scratch = 0;
1079
1080 if (check_for_high_segbits) {
1081 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1082
1083 if (pgd_reg != -1)
1084 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
1085 else
1086 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1087
1088 if (c0_scratch_reg >= 0)
1089 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1090 else
1091 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1092
1093 uasm_i_dsrl_safe(p, scratch, tmp,
1094 PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
1095 uasm_il_bnez(p, r, scratch, label_vmalloc);
1096
1097 if (pgd_reg == -1) {
1098 vmalloc_branch_delay_filled = 1;
1099 /* Clear lower 23 bits of context. */
1100 uasm_i_dins(p, ptr, 0, 0, 23);
1101 }
1102 } else {
1103 if (pgd_reg != -1)
1104 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
1105 else
1106 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1107
1108 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1109
1110 if (c0_scratch_reg >= 0)
1111 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1112 else
1113 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1114
1115 if (pgd_reg == -1)
1116 /* Clear lower 23 bits of context. */
1117 uasm_i_dins(p, ptr, 0, 0, 23);
1118
1119 uasm_il_bltz(p, r, tmp, label_vmalloc);
1120 }
1121
1122 if (pgd_reg == -1) {
1123 vmalloc_branch_delay_filled = 1;
1124 /* 1 0 1 0 1 << 6 xkphys cached */
1125 uasm_i_ori(p, ptr, ptr, 0x540);
1126 uasm_i_drotr(p, ptr, ptr, 11);
1127 }
1128
1129 #ifdef __PAGETABLE_PMD_FOLDED
1130 #define LOC_PTEP scratch
1131 #else
1132 #define LOC_PTEP ptr
1133 #endif
1134
1135 if (!vmalloc_branch_delay_filled)
1136 /* get pgd offset in bytes */
1137 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1138
1139 uasm_l_vmalloc_done(l, *p);
1140
1141 /*
1142 * tmp ptr
1143 * fall-through case = badvaddr *pgd_current
1144 * vmalloc case = badvaddr swapper_pg_dir
1145 */
1146
1147 if (vmalloc_branch_delay_filled)
1148 /* get pgd offset in bytes */
1149 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1150
1151 #ifdef __PAGETABLE_PMD_FOLDED
1152 GET_CONTEXT(p, tmp); /* get context reg */
1153 #endif
1154 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3);
1155
1156 if (use_lwx_insns()) {
1157 UASM_i_LWX(p, LOC_PTEP, scratch, ptr);
1158 } else {
1159 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */
1160 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */
1161 }
1162
1163 #ifndef __PAGETABLE_PMD_FOLDED
1164 /* get pmd offset in bytes */
1165 uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3);
1166 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3);
1167 GET_CONTEXT(p, tmp); /* get context reg */
1168
1169 if (use_lwx_insns()) {
1170 UASM_i_LWX(p, scratch, scratch, ptr);
1171 } else {
1172 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */
1173 UASM_i_LW(p, scratch, 0, ptr);
1174 }
1175 #endif
1176 /* Adjust the context during the load latency. */
1177 build_adjust_context(p, tmp);
1178
1179 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1180 uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update);
1181 /*
1182 * The in the LWX case we don't want to do the load in the
1183 * delay slot. It cannot issue in the same cycle and may be
1184 * speculative and unneeded.
1185 */
1186 if (use_lwx_insns())
1187 uasm_i_nop(p);
1188 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
1189
1190
1191 /* build_update_entries */
1192 if (use_lwx_insns()) {
1193 even = ptr;
1194 odd = tmp;
1195 UASM_i_LWX(p, even, scratch, tmp);
1196 UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t));
1197 UASM_i_LWX(p, odd, scratch, tmp);
1198 } else {
1199 UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */
1200 even = tmp;
1201 odd = ptr;
1202 UASM_i_LW(p, even, 0, ptr); /* get even pte */
1203 UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */
1204 }
1205 if (cpu_has_rixi) {
1206 uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL));
1207 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1208 uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL));
1209 } else {
1210 uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL));
1211 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1212 uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL));
1213 }
1214 UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */
1215
1216 if (c0_scratch_reg >= 0) {
1217 UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg);
1218 build_tlb_write_entry(p, l, r, tlb_random);
1219 uasm_l_leave(l, *p);
1220 rv.restore_scratch = 1;
1221 } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) {
1222 build_tlb_write_entry(p, l, r, tlb_random);
1223 uasm_l_leave(l, *p);
1224 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1225 } else {
1226 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1227 build_tlb_write_entry(p, l, r, tlb_random);
1228 uasm_l_leave(l, *p);
1229 rv.restore_scratch = 1;
1230 }
1231
1232 uasm_i_eret(p); /* return from trap */
1233
1234 return rv;
1235 }
1236
1237 /*
1238 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
1239 * because EXL == 0. If we wrap, we can also use the 32 instruction
1240 * slots before the XTLB refill exception handler which belong to the
1241 * unused TLB refill exception.
1242 */
1243 #define MIPS64_REFILL_INSNS 32
1244
1245 static void build_r4000_tlb_refill_handler(void)
1246 {
1247 u32 *p = tlb_handler;
1248 struct uasm_label *l = labels;
1249 struct uasm_reloc *r = relocs;
1250 u32 *f;
1251 unsigned int final_len;
1252 struct mips_huge_tlb_info htlb_info __maybe_unused;
1253 enum vmalloc64_mode vmalloc_mode __maybe_unused;
1254
1255 memset(tlb_handler, 0, sizeof(tlb_handler));
1256 memset(labels, 0, sizeof(labels));
1257 memset(relocs, 0, sizeof(relocs));
1258 memset(final_handler, 0, sizeof(final_handler));
1259
1260 if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) {
1261 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,
1262 scratch_reg);
1263 vmalloc_mode = refill_scratch;
1264 } else {
1265 htlb_info.huge_pte = K0;
1266 htlb_info.restore_scratch = 0;
1267 vmalloc_mode = refill_noscratch;
1268 /*
1269 * create the plain linear handler
1270 */
1271 if (bcm1250_m3_war()) {
1272 unsigned int segbits = 44;
1273
1274 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1275 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
1276 uasm_i_xor(&p, K0, K0, K1);
1277 uasm_i_dsrl_safe(&p, K1, K0, 62);
1278 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
1279 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
1280 uasm_i_or(&p, K0, K0, K1);
1281 uasm_il_bnez(&p, &r, K0, label_leave);
1282 /* No need for uasm_i_nop */
1283 }
1284
1285 #ifdef CONFIG_64BIT
1286 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
1287 #else
1288 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
1289 #endif
1290
1291 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1292 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update);
1293 #endif
1294
1295 build_get_ptep(&p, K0, K1);
1296 build_update_entries(&p, K0, K1);
1297 build_tlb_write_entry(&p, &l, &r, tlb_random);
1298 uasm_l_leave(&l, p);
1299 uasm_i_eret(&p); /* return from trap */
1300 }
1301 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1302 uasm_l_tlb_huge_update(&l, p);
1303 UASM_i_LW(&p, K0, 0, K1);
1304 build_huge_update_entries(&p, htlb_info.huge_pte, K1);
1305 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random,
1306 htlb_info.restore_scratch);
1307 #endif
1308
1309 #ifdef CONFIG_64BIT
1310 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode);
1311 #endif
1312
1313 /*
1314 * Overflow check: For the 64bit handler, we need at least one
1315 * free instruction slot for the wrap-around branch. In worst
1316 * case, if the intended insertion point is a delay slot, we
1317 * need three, with the second nop'ed and the third being
1318 * unused.
1319 */
1320 switch (boot_cpu_type()) {
1321 default:
1322 if (sizeof(long) == 4) {
1323 case CPU_LOONGSON2:
1324 /* Loongson2 ebase is different than r4k, we have more space */
1325 if ((p - tlb_handler) > 64)
1326 panic("TLB refill handler space exceeded");
1327 /*
1328 * Now fold the handler in the TLB refill handler space.
1329 */
1330 f = final_handler;
1331 /* Simplest case, just copy the handler. */
1332 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1333 final_len = p - tlb_handler;
1334 break;
1335 } else {
1336 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1)
1337 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3)
1338 && uasm_insn_has_bdelay(relocs,
1339 tlb_handler + MIPS64_REFILL_INSNS - 3)))
1340 panic("TLB refill handler space exceeded");
1341 /*
1342 * Now fold the handler in the TLB refill handler space.
1343 */
1344 f = final_handler + MIPS64_REFILL_INSNS;
1345 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) {
1346 /* Just copy the handler. */
1347 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1348 final_len = p - tlb_handler;
1349 } else {
1350 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1351 const enum label_id ls = label_tlb_huge_update;
1352 #else
1353 const enum label_id ls = label_vmalloc;
1354 #endif
1355 u32 *split;
1356 int ov = 0;
1357 int i;
1358
1359 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++)
1360 ;
1361 BUG_ON(i == ARRAY_SIZE(labels));
1362 split = labels[i].addr;
1363
1364 /*
1365 * See if we have overflown one way or the other.
1366 */
1367 if (split > tlb_handler + MIPS64_REFILL_INSNS ||
1368 split < p - MIPS64_REFILL_INSNS)
1369 ov = 1;
1370
1371 if (ov) {
1372 /*
1373 * Split two instructions before the end. One
1374 * for the branch and one for the instruction
1375 * in the delay slot.
1376 */
1377 split = tlb_handler + MIPS64_REFILL_INSNS - 2;
1378
1379 /*
1380 * If the branch would fall in a delay slot,
1381 * we must back up an additional instruction
1382 * so that it is no longer in a delay slot.
1383 */
1384 if (uasm_insn_has_bdelay(relocs, split - 1))
1385 split--;
1386 }
1387 /* Copy first part of the handler. */
1388 uasm_copy_handler(relocs, labels, tlb_handler, split, f);
1389 f += split - tlb_handler;
1390
1391 if (ov) {
1392 /* Insert branch. */
1393 uasm_l_split(&l, final_handler);
1394 uasm_il_b(&f, &r, label_split);
1395 if (uasm_insn_has_bdelay(relocs, split))
1396 uasm_i_nop(&f);
1397 else {
1398 uasm_copy_handler(relocs, labels,
1399 split, split + 1, f);
1400 uasm_move_labels(labels, f, f + 1, -1);
1401 f++;
1402 split++;
1403 }
1404 }
1405
1406 /* Copy the rest of the handler. */
1407 uasm_copy_handler(relocs, labels, split, p, final_handler);
1408 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) +
1409 (p - split);
1410 }
1411 }
1412 break;
1413 }
1414
1415 uasm_resolve_relocs(relocs, labels);
1416 pr_debug("Wrote TLB refill handler (%u instructions).\n",
1417 final_len);
1418
1419 memcpy((void *)ebase, final_handler, 0x100);
1420 local_flush_icache_range(ebase, ebase + 0x100);
1421
1422 dump_handler("r4000_tlb_refill", (u32 *)ebase, 64);
1423 }
1424
1425 extern u32 handle_tlbl[], handle_tlbl_end[];
1426 extern u32 handle_tlbs[], handle_tlbs_end[];
1427 extern u32 handle_tlbm[], handle_tlbm_end[];
1428 extern u32 tlbmiss_handler_setup_pgd_start[], tlbmiss_handler_setup_pgd[];
1429 extern u32 tlbmiss_handler_setup_pgd_end[];
1430
1431 static void build_setup_pgd(void)
1432 {
1433 const int a0 = 4;
1434 const int __maybe_unused a1 = 5;
1435 const int __maybe_unused a2 = 6;
1436 u32 *p = tlbmiss_handler_setup_pgd_start;
1437 const int tlbmiss_handler_setup_pgd_size =
1438 tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd_start;
1439 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1440 long pgdc = (long)pgd_current;
1441 #endif
1442
1443 memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size *
1444 sizeof(tlbmiss_handler_setup_pgd[0]));
1445 memset(labels, 0, sizeof(labels));
1446 memset(relocs, 0, sizeof(relocs));
1447 pgd_reg = allocate_kscratch();
1448 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
1449 if (pgd_reg == -1) {
1450 struct uasm_label *l = labels;
1451 struct uasm_reloc *r = relocs;
1452
1453 /* PGD << 11 in c0_Context */
1454 /*
1455 * If it is a ckseg0 address, convert to a physical
1456 * address. Shifting right by 29 and adding 4 will
1457 * result in zero for these addresses.
1458 *
1459 */
1460 UASM_i_SRA(&p, a1, a0, 29);
1461 UASM_i_ADDIU(&p, a1, a1, 4);
1462 uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1);
1463 uasm_i_nop(&p);
1464 uasm_i_dinsm(&p, a0, 0, 29, 64 - 29);
1465 uasm_l_tlbl_goaround1(&l, p);
1466 UASM_i_SLL(&p, a0, a0, 11);
1467 uasm_i_jr(&p, 31);
1468 UASM_i_MTC0(&p, a0, C0_CONTEXT);
1469 } else {
1470 /* PGD in c0_KScratch */
1471 uasm_i_jr(&p, 31);
1472 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
1473 }
1474 #else
1475 #ifdef CONFIG_SMP
1476 /* Save PGD to pgd_current[smp_processor_id()] */
1477 UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG);
1478 UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT);
1479 UASM_i_LA_mostly(&p, a2, pgdc);
1480 UASM_i_ADDU(&p, a2, a2, a1);
1481 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
1482 #else
1483 UASM_i_LA_mostly(&p, a2, pgdc);
1484 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
1485 #endif /* SMP */
1486 uasm_i_jr(&p, 31);
1487
1488 /* if pgd_reg is allocated, save PGD also to scratch register */
1489 if (pgd_reg != -1)
1490 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
1491 else
1492 uasm_i_nop(&p);
1493 #endif
1494 if (p >= tlbmiss_handler_setup_pgd_end)
1495 panic("tlbmiss_handler_setup_pgd space exceeded");
1496
1497 uasm_resolve_relocs(relocs, labels);
1498 pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n",
1499 (unsigned int)(p - tlbmiss_handler_setup_pgd));
1500
1501 dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd,
1502 tlbmiss_handler_setup_pgd_size);
1503 }
1504
1505 static void
1506 iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
1507 {
1508 #ifdef CONFIG_SMP
1509 # ifdef CONFIG_64BIT_PHYS_ADDR
1510 if (cpu_has_64bits)
1511 uasm_i_lld(p, pte, 0, ptr);
1512 else
1513 # endif
1514 UASM_i_LL(p, pte, 0, ptr);
1515 #else
1516 # ifdef CONFIG_64BIT_PHYS_ADDR
1517 if (cpu_has_64bits)
1518 uasm_i_ld(p, pte, 0, ptr);
1519 else
1520 # endif
1521 UASM_i_LW(p, pte, 0, ptr);
1522 #endif
1523 }
1524
1525 static void
1526 iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
1527 unsigned int mode)
1528 {
1529 #ifdef CONFIG_64BIT_PHYS_ADDR
1530 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
1531 #endif
1532
1533 uasm_i_ori(p, pte, pte, mode);
1534 #ifdef CONFIG_SMP
1535 # ifdef CONFIG_64BIT_PHYS_ADDR
1536 if (cpu_has_64bits)
1537 uasm_i_scd(p, pte, 0, ptr);
1538 else
1539 # endif
1540 UASM_i_SC(p, pte, 0, ptr);
1541
1542 if (r10000_llsc_war())
1543 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change);
1544 else
1545 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1546
1547 # ifdef CONFIG_64BIT_PHYS_ADDR
1548 if (!cpu_has_64bits) {
1549 /* no uasm_i_nop needed */
1550 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr);
1551 uasm_i_ori(p, pte, pte, hwmode);
1552 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr);
1553 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1554 /* no uasm_i_nop needed */
1555 uasm_i_lw(p, pte, 0, ptr);
1556 } else
1557 uasm_i_nop(p);
1558 # else
1559 uasm_i_nop(p);
1560 # endif
1561 #else
1562 # ifdef CONFIG_64BIT_PHYS_ADDR
1563 if (cpu_has_64bits)
1564 uasm_i_sd(p, pte, 0, ptr);
1565 else
1566 # endif
1567 UASM_i_SW(p, pte, 0, ptr);
1568
1569 # ifdef CONFIG_64BIT_PHYS_ADDR
1570 if (!cpu_has_64bits) {
1571 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr);
1572 uasm_i_ori(p, pte, pte, hwmode);
1573 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr);
1574 uasm_i_lw(p, pte, 0, ptr);
1575 }
1576 # endif
1577 #endif
1578 }
1579
1580 /*
1581 * Check if PTE is present, if not then jump to LABEL. PTR points to
1582 * the page table where this PTE is located, PTE will be re-loaded
1583 * with it's original value.
1584 */
1585 static void
1586 build_pte_present(u32 **p, struct uasm_reloc **r,
1587 int pte, int ptr, int scratch, enum label_id lid)
1588 {
1589 int t = scratch >= 0 ? scratch : pte;
1590
1591 if (cpu_has_rixi) {
1592 if (use_bbit_insns()) {
1593 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid);
1594 uasm_i_nop(p);
1595 } else {
1596 uasm_i_andi(p, t, pte, _PAGE_PRESENT);
1597 uasm_il_beqz(p, r, t, lid);
1598 if (pte == t)
1599 /* You lose the SMP race :-(*/
1600 iPTE_LW(p, pte, ptr);
1601 }
1602 } else {
1603 uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_READ);
1604 uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_READ);
1605 uasm_il_bnez(p, r, t, lid);
1606 if (pte == t)
1607 /* You lose the SMP race :-(*/
1608 iPTE_LW(p, pte, ptr);
1609 }
1610 }
1611
1612 /* Make PTE valid, store result in PTR. */
1613 static void
1614 build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
1615 unsigned int ptr)
1616 {
1617 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
1618
1619 iPTE_SW(p, r, pte, ptr, mode);
1620 }
1621
1622 /*
1623 * Check if PTE can be written to, if not branch to LABEL. Regardless
1624 * restore PTE with value from PTR when done.
1625 */
1626 static void
1627 build_pte_writable(u32 **p, struct uasm_reloc **r,
1628 unsigned int pte, unsigned int ptr, int scratch,
1629 enum label_id lid)
1630 {
1631 int t = scratch >= 0 ? scratch : pte;
1632
1633 uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_WRITE);
1634 uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_WRITE);
1635 uasm_il_bnez(p, r, t, lid);
1636 if (pte == t)
1637 /* You lose the SMP race :-(*/
1638 iPTE_LW(p, pte, ptr);
1639 else
1640 uasm_i_nop(p);
1641 }
1642
1643 /* Make PTE writable, update software status bits as well, then store
1644 * at PTR.
1645 */
1646 static void
1647 build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
1648 unsigned int ptr)
1649 {
1650 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
1651 | _PAGE_DIRTY);
1652
1653 iPTE_SW(p, r, pte, ptr, mode);
1654 }
1655
1656 /*
1657 * Check if PTE can be modified, if not branch to LABEL. Regardless
1658 * restore PTE with value from PTR when done.
1659 */
1660 static void
1661 build_pte_modifiable(u32 **p, struct uasm_reloc **r,
1662 unsigned int pte, unsigned int ptr, int scratch,
1663 enum label_id lid)
1664 {
1665 if (use_bbit_insns()) {
1666 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid);
1667 uasm_i_nop(p);
1668 } else {
1669 int t = scratch >= 0 ? scratch : pte;
1670 uasm_i_andi(p, t, pte, _PAGE_WRITE);
1671 uasm_il_beqz(p, r, t, lid);
1672 if (pte == t)
1673 /* You lose the SMP race :-(*/
1674 iPTE_LW(p, pte, ptr);
1675 }
1676 }
1677
1678 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1679
1680
1681 /*
1682 * R3000 style TLB load/store/modify handlers.
1683 */
1684
1685 /*
1686 * This places the pte into ENTRYLO0 and writes it with tlbwi.
1687 * Then it returns.
1688 */
1689 static void
1690 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
1691 {
1692 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1693 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
1694 uasm_i_tlbwi(p);
1695 uasm_i_jr(p, tmp);
1696 uasm_i_rfe(p); /* branch delay */
1697 }
1698
1699 /*
1700 * This places the pte into ENTRYLO0 and writes it with tlbwi
1701 * or tlbwr as appropriate. This is because the index register
1702 * may have the probe fail bit set as a result of a trap on a
1703 * kseg2 access, i.e. without refill. Then it returns.
1704 */
1705 static void
1706 build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l,
1707 struct uasm_reloc **r, unsigned int pte,
1708 unsigned int tmp)
1709 {
1710 uasm_i_mfc0(p, tmp, C0_INDEX);
1711 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1712 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
1713 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */
1714 uasm_i_tlbwi(p); /* cp0 delay */
1715 uasm_i_jr(p, tmp);
1716 uasm_i_rfe(p); /* branch delay */
1717 uasm_l_r3000_write_probe_fail(l, *p);
1718 uasm_i_tlbwr(p); /* cp0 delay */
1719 uasm_i_jr(p, tmp);
1720 uasm_i_rfe(p); /* branch delay */
1721 }
1722
1723 static void
1724 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1725 unsigned int ptr)
1726 {
1727 long pgdc = (long)pgd_current;
1728
1729 uasm_i_mfc0(p, pte, C0_BADVADDR);
1730 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */
1731 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
1732 uasm_i_srl(p, pte, pte, 22); /* load delay */
1733 uasm_i_sll(p, pte, pte, 2);
1734 uasm_i_addu(p, ptr, ptr, pte);
1735 uasm_i_mfc0(p, pte, C0_CONTEXT);
1736 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */
1737 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */
1738 uasm_i_addu(p, ptr, ptr, pte);
1739 uasm_i_lw(p, pte, 0, ptr);
1740 uasm_i_tlbp(p); /* load delay */
1741 }
1742
1743 static void build_r3000_tlb_load_handler(void)
1744 {
1745 u32 *p = handle_tlbl;
1746 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl;
1747 struct uasm_label *l = labels;
1748 struct uasm_reloc *r = relocs;
1749
1750 memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0]));
1751 memset(labels, 0, sizeof(labels));
1752 memset(relocs, 0, sizeof(relocs));
1753
1754 build_r3000_tlbchange_handler_head(&p, K0, K1);
1755 build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl);
1756 uasm_i_nop(&p); /* load delay */
1757 build_make_valid(&p, &r, K0, K1);
1758 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1759
1760 uasm_l_nopage_tlbl(&l, p);
1761 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1762 uasm_i_nop(&p);
1763
1764 if (p >= handle_tlbl_end)
1765 panic("TLB load handler fastpath space exceeded");
1766
1767 uasm_resolve_relocs(relocs, labels);
1768 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1769 (unsigned int)(p - handle_tlbl));
1770
1771 dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_size);
1772 }
1773
1774 static void build_r3000_tlb_store_handler(void)
1775 {
1776 u32 *p = handle_tlbs;
1777 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs;
1778 struct uasm_label *l = labels;
1779 struct uasm_reloc *r = relocs;
1780
1781 memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0]));
1782 memset(labels, 0, sizeof(labels));
1783 memset(relocs, 0, sizeof(relocs));
1784
1785 build_r3000_tlbchange_handler_head(&p, K0, K1);
1786 build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs);
1787 uasm_i_nop(&p); /* load delay */
1788 build_make_write(&p, &r, K0, K1);
1789 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1790
1791 uasm_l_nopage_tlbs(&l, p);
1792 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1793 uasm_i_nop(&p);
1794
1795 if (p >= handle_tlbs_end)
1796 panic("TLB store handler fastpath space exceeded");
1797
1798 uasm_resolve_relocs(relocs, labels);
1799 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1800 (unsigned int)(p - handle_tlbs));
1801
1802 dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_size);
1803 }
1804
1805 static void build_r3000_tlb_modify_handler(void)
1806 {
1807 u32 *p = handle_tlbm;
1808 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm;
1809 struct uasm_label *l = labels;
1810 struct uasm_reloc *r = relocs;
1811
1812 memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0]));
1813 memset(labels, 0, sizeof(labels));
1814 memset(relocs, 0, sizeof(relocs));
1815
1816 build_r3000_tlbchange_handler_head(&p, K0, K1);
1817 build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm);
1818 uasm_i_nop(&p); /* load delay */
1819 build_make_write(&p, &r, K0, K1);
1820 build_r3000_pte_reload_tlbwi(&p, K0, K1);
1821
1822 uasm_l_nopage_tlbm(&l, p);
1823 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1824 uasm_i_nop(&p);
1825
1826 if (p >= handle_tlbm_end)
1827 panic("TLB modify handler fastpath space exceeded");
1828
1829 uasm_resolve_relocs(relocs, labels);
1830 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
1831 (unsigned int)(p - handle_tlbm));
1832
1833 dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_size);
1834 }
1835 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
1836
1837 /*
1838 * R4000 style TLB load/store/modify handlers.
1839 */
1840 static struct work_registers
1841 build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
1842 struct uasm_reloc **r)
1843 {
1844 struct work_registers wr = build_get_work_registers(p);
1845
1846 #ifdef CONFIG_64BIT
1847 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
1848 #else
1849 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
1850 #endif
1851
1852 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1853 /*
1854 * For huge tlb entries, pmd doesn't contain an address but
1855 * instead contains the tlb pte. Check the PAGE_HUGE bit and
1856 * see if we need to jump to huge tlb processing.
1857 */
1858 build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update);
1859 #endif
1860
1861 UASM_i_MFC0(p, wr.r1, C0_BADVADDR);
1862 UASM_i_LW(p, wr.r2, 0, wr.r2);
1863 UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
1864 uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
1865 UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1);
1866
1867 #ifdef CONFIG_SMP
1868 uasm_l_smp_pgtable_change(l, *p);
1869 #endif
1870 iPTE_LW(p, wr.r1, wr.r2); /* get even pte */
1871 if (!m4kc_tlbp_war())
1872 build_tlb_probe_entry(p);
1873 return wr;
1874 }
1875
1876 static void
1877 build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l,
1878 struct uasm_reloc **r, unsigned int tmp,
1879 unsigned int ptr)
1880 {
1881 uasm_i_ori(p, ptr, ptr, sizeof(pte_t));
1882 uasm_i_xori(p, ptr, ptr, sizeof(pte_t));
1883 build_update_entries(p, tmp, ptr);
1884 build_tlb_write_entry(p, l, r, tlb_indexed);
1885 uasm_l_leave(l, *p);
1886 build_restore_work_registers(p);
1887 uasm_i_eret(p); /* return from trap */
1888
1889 #ifdef CONFIG_64BIT
1890 build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill);
1891 #endif
1892 }
1893
1894 static void build_r4000_tlb_load_handler(void)
1895 {
1896 u32 *p = handle_tlbl;
1897 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl;
1898 struct uasm_label *l = labels;
1899 struct uasm_reloc *r = relocs;
1900 struct work_registers wr;
1901
1902 memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0]));
1903 memset(labels, 0, sizeof(labels));
1904 memset(relocs, 0, sizeof(relocs));
1905
1906 if (bcm1250_m3_war()) {
1907 unsigned int segbits = 44;
1908
1909 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1910 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
1911 uasm_i_xor(&p, K0, K0, K1);
1912 uasm_i_dsrl_safe(&p, K1, K0, 62);
1913 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
1914 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
1915 uasm_i_or(&p, K0, K0, K1);
1916 uasm_il_bnez(&p, &r, K0, label_leave);
1917 /* No need for uasm_i_nop */
1918 }
1919
1920 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
1921 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
1922 if (m4kc_tlbp_war())
1923 build_tlb_probe_entry(&p);
1924
1925 if (cpu_has_rixi && !cpu_has_rixiex) {
1926 /*
1927 * If the page is not _PAGE_VALID, RI or XI could not
1928 * have triggered it. Skip the expensive test..
1929 */
1930 if (use_bbit_insns()) {
1931 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
1932 label_tlbl_goaround1);
1933 } else {
1934 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
1935 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1);
1936 }
1937 uasm_i_nop(&p);
1938
1939 uasm_i_tlbr(&p);
1940
1941 switch (current_cpu_type()) {
1942 default:
1943 if (cpu_has_mips_r2) {
1944 uasm_i_ehb(&p);
1945
1946 case CPU_CAVIUM_OCTEON:
1947 case CPU_CAVIUM_OCTEON_PLUS:
1948 case CPU_CAVIUM_OCTEON2:
1949 break;
1950 }
1951 }
1952
1953 /* Examine entrylo 0 or 1 based on ptr. */
1954 if (use_bbit_insns()) {
1955 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
1956 } else {
1957 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
1958 uasm_i_beqz(&p, wr.r3, 8);
1959 }
1960 /* load it in the delay slot*/
1961 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
1962 /* load it if ptr is odd */
1963 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
1964 /*
1965 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
1966 * XI must have triggered it.
1967 */
1968 if (use_bbit_insns()) {
1969 uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl);
1970 uasm_i_nop(&p);
1971 uasm_l_tlbl_goaround1(&l, p);
1972 } else {
1973 uasm_i_andi(&p, wr.r3, wr.r3, 2);
1974 uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl);
1975 uasm_i_nop(&p);
1976 }
1977 uasm_l_tlbl_goaround1(&l, p);
1978 }
1979 build_make_valid(&p, &r, wr.r1, wr.r2);
1980 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
1981
1982 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1983 /*
1984 * This is the entry point when build_r4000_tlbchange_handler_head
1985 * spots a huge page.
1986 */
1987 uasm_l_tlb_huge_update(&l, p);
1988 iPTE_LW(&p, wr.r1, wr.r2);
1989 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
1990 build_tlb_probe_entry(&p);
1991
1992 if (cpu_has_rixi && !cpu_has_rixiex) {
1993 /*
1994 * If the page is not _PAGE_VALID, RI or XI could not
1995 * have triggered it. Skip the expensive test..
1996 */
1997 if (use_bbit_insns()) {
1998 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
1999 label_tlbl_goaround2);
2000 } else {
2001 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
2002 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
2003 }
2004 uasm_i_nop(&p);
2005
2006 uasm_i_tlbr(&p);
2007
2008 switch (current_cpu_type()) {
2009 default:
2010 if (cpu_has_mips_r2) {
2011 uasm_i_ehb(&p);
2012
2013 case CPU_CAVIUM_OCTEON:
2014 case CPU_CAVIUM_OCTEON_PLUS:
2015 case CPU_CAVIUM_OCTEON2:
2016 break;
2017 }
2018 }
2019
2020 /* Examine entrylo 0 or 1 based on ptr. */
2021 if (use_bbit_insns()) {
2022 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
2023 } else {
2024 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
2025 uasm_i_beqz(&p, wr.r3, 8);
2026 }
2027 /* load it in the delay slot*/
2028 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
2029 /* load it if ptr is odd */
2030 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
2031 /*
2032 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
2033 * XI must have triggered it.
2034 */
2035 if (use_bbit_insns()) {
2036 uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2);
2037 } else {
2038 uasm_i_andi(&p, wr.r3, wr.r3, 2);
2039 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
2040 }
2041 if (PM_DEFAULT_MASK == 0)
2042 uasm_i_nop(&p);
2043 /*
2044 * We clobbered C0_PAGEMASK, restore it. On the other branch
2045 * it is restored in build_huge_tlb_write_entry.
2046 */
2047 build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0);
2048
2049 uasm_l_tlbl_goaround2(&l, p);
2050 }
2051 uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID));
2052 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
2053 #endif
2054
2055 uasm_l_nopage_tlbl(&l, p);
2056 build_restore_work_registers(&p);
2057 #ifdef CONFIG_CPU_MICROMIPS
2058 if ((unsigned long)tlb_do_page_fault_0 & 1) {
2059 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0));
2060 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0));
2061 uasm_i_jr(&p, K0);
2062 } else
2063 #endif
2064 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
2065 uasm_i_nop(&p);
2066
2067 if (p >= handle_tlbl_end)
2068 panic("TLB load handler fastpath space exceeded");
2069
2070 uasm_resolve_relocs(relocs, labels);
2071 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
2072 (unsigned int)(p - handle_tlbl));
2073
2074 dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_size);
2075 }
2076
2077 static void build_r4000_tlb_store_handler(void)
2078 {
2079 u32 *p = handle_tlbs;
2080 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs;
2081 struct uasm_label *l = labels;
2082 struct uasm_reloc *r = relocs;
2083 struct work_registers wr;
2084
2085 memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0]));
2086 memset(labels, 0, sizeof(labels));
2087 memset(relocs, 0, sizeof(relocs));
2088
2089 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2090 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2091 if (m4kc_tlbp_war())
2092 build_tlb_probe_entry(&p);
2093 build_make_write(&p, &r, wr.r1, wr.r2);
2094 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2095
2096 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2097 /*
2098 * This is the entry point when
2099 * build_r4000_tlbchange_handler_head spots a huge page.
2100 */
2101 uasm_l_tlb_huge_update(&l, p);
2102 iPTE_LW(&p, wr.r1, wr.r2);
2103 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2104 build_tlb_probe_entry(&p);
2105 uasm_i_ori(&p, wr.r1, wr.r1,
2106 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2107 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
2108 #endif
2109
2110 uasm_l_nopage_tlbs(&l, p);
2111 build_restore_work_registers(&p);
2112 #ifdef CONFIG_CPU_MICROMIPS
2113 if ((unsigned long)tlb_do_page_fault_1 & 1) {
2114 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
2115 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
2116 uasm_i_jr(&p, K0);
2117 } else
2118 #endif
2119 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2120 uasm_i_nop(&p);
2121
2122 if (p >= handle_tlbs_end)
2123 panic("TLB store handler fastpath space exceeded");
2124
2125 uasm_resolve_relocs(relocs, labels);
2126 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
2127 (unsigned int)(p - handle_tlbs));
2128
2129 dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_size);
2130 }
2131
2132 static void build_r4000_tlb_modify_handler(void)
2133 {
2134 u32 *p = handle_tlbm;
2135 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm;
2136 struct uasm_label *l = labels;
2137 struct uasm_reloc *r = relocs;
2138 struct work_registers wr;
2139
2140 memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0]));
2141 memset(labels, 0, sizeof(labels));
2142 memset(relocs, 0, sizeof(relocs));
2143
2144 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2145 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2146 if (m4kc_tlbp_war())
2147 build_tlb_probe_entry(&p);
2148 /* Present and writable bits set, set accessed and dirty bits. */
2149 build_make_write(&p, &r, wr.r1, wr.r2);
2150 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2151
2152 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2153 /*
2154 * This is the entry point when
2155 * build_r4000_tlbchange_handler_head spots a huge page.
2156 */
2157 uasm_l_tlb_huge_update(&l, p);
2158 iPTE_LW(&p, wr.r1, wr.r2);
2159 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2160 build_tlb_probe_entry(&p);
2161 uasm_i_ori(&p, wr.r1, wr.r1,
2162 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2163 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
2164 #endif
2165
2166 uasm_l_nopage_tlbm(&l, p);
2167 build_restore_work_registers(&p);
2168 #ifdef CONFIG_CPU_MICROMIPS
2169 if ((unsigned long)tlb_do_page_fault_1 & 1) {
2170 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
2171 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
2172 uasm_i_jr(&p, K0);
2173 } else
2174 #endif
2175 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2176 uasm_i_nop(&p);
2177
2178 if (p >= handle_tlbm_end)
2179 panic("TLB modify handler fastpath space exceeded");
2180
2181 uasm_resolve_relocs(relocs, labels);
2182 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
2183 (unsigned int)(p - handle_tlbm));
2184
2185 dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_size);
2186 }
2187
2188 static void flush_tlb_handlers(void)
2189 {
2190 local_flush_icache_range((unsigned long)handle_tlbl,
2191 (unsigned long)handle_tlbl_end);
2192 local_flush_icache_range((unsigned long)handle_tlbs,
2193 (unsigned long)handle_tlbs_end);
2194 local_flush_icache_range((unsigned long)handle_tlbm,
2195 (unsigned long)handle_tlbm_end);
2196 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd,
2197 (unsigned long)tlbmiss_handler_setup_pgd_end);
2198 }
2199
2200 static void print_htw_config(void)
2201 {
2202 unsigned long config;
2203 unsigned int pwctl;
2204 const int field = 2 * sizeof(unsigned long);
2205
2206 config = read_c0_pwfield();
2207 pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n",
2208 field, config,
2209 (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT,
2210 (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT,
2211 (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT,
2212 (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT,
2213 (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT);
2214
2215 config = read_c0_pwsize();
2216 pr_debug("PWSize (0x%0*lx): GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n",
2217 field, config,
2218 (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT,
2219 (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT,
2220 (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT,
2221 (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT,
2222 (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT);
2223
2224 pwctl = read_c0_pwctl();
2225 pr_debug("PWCtl (0x%x): PWEn: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n",
2226 pwctl,
2227 (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT,
2228 (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT,
2229 (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT,
2230 (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT);
2231 }
2232
2233 static void config_htw_params(void)
2234 {
2235 unsigned long pwfield, pwsize, ptei;
2236 unsigned int config;
2237
2238 /*
2239 * We are using 2-level page tables, so we only need to
2240 * setup GDW and PTW appropriately. UDW and MDW will remain 0.
2241 * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to
2242 * write values less than 0xc in these fields because the entire
2243 * write will be dropped. As a result of which, we must preserve
2244 * the original reset values and overwrite only what we really want.
2245 */
2246
2247 pwfield = read_c0_pwfield();
2248 /* re-initialize the GDI field */
2249 pwfield &= ~MIPS_PWFIELD_GDI_MASK;
2250 pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT;
2251 /* re-initialize the PTI field including the even/odd bit */
2252 pwfield &= ~MIPS_PWFIELD_PTI_MASK;
2253 pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT;
2254 /* Set the PTEI right shift */
2255 ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT;
2256 pwfield |= ptei;
2257 write_c0_pwfield(pwfield);
2258 /* Check whether the PTEI value is supported */
2259 back_to_back_c0_hazard();
2260 pwfield = read_c0_pwfield();
2261 if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT)
2262 != ptei) {
2263 pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled",
2264 ptei);
2265 /*
2266 * Drop option to avoid HTW being enabled via another path
2267 * (eg htw_reset())
2268 */
2269 current_cpu_data.options &= ~MIPS_CPU_HTW;
2270 return;
2271 }
2272
2273 pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT;
2274 pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT;
2275 write_c0_pwsize(pwsize);
2276
2277 /* Make sure everything is set before we enable the HTW */
2278 back_to_back_c0_hazard();
2279
2280 /* Enable HTW and disable the rest of the pwctl fields */
2281 config = 1 << MIPS_PWCTL_PWEN_SHIFT;
2282 write_c0_pwctl(config);
2283 pr_info("Hardware Page Table Walker enabled\n");
2284
2285 print_htw_config();
2286 }
2287
2288 void build_tlb_refill_handler(void)
2289 {
2290 /*
2291 * The refill handler is generated per-CPU, multi-node systems
2292 * may have local storage for it. The other handlers are only
2293 * needed once.
2294 */
2295 static int run_once = 0;
2296
2297 output_pgtable_bits_defines();
2298
2299 #ifdef CONFIG_64BIT
2300 check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
2301 #endif
2302
2303 switch (current_cpu_type()) {
2304 case CPU_R2000:
2305 case CPU_R3000:
2306 case CPU_R3000A:
2307 case CPU_R3081E:
2308 case CPU_TX3912:
2309 case CPU_TX3922:
2310 case CPU_TX3927:
2311 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
2312 if (cpu_has_local_ebase)
2313 build_r3000_tlb_refill_handler();
2314 if (!run_once) {
2315 if (!cpu_has_local_ebase)
2316 build_r3000_tlb_refill_handler();
2317 build_setup_pgd();
2318 build_r3000_tlb_load_handler();
2319 build_r3000_tlb_store_handler();
2320 build_r3000_tlb_modify_handler();
2321 flush_tlb_handlers();
2322 run_once++;
2323 }
2324 #else
2325 panic("No R3000 TLB refill handler");
2326 #endif
2327 break;
2328
2329 case CPU_R6000:
2330 case CPU_R6000A:
2331 panic("No R6000 TLB refill handler yet");
2332 break;
2333
2334 case CPU_R8000:
2335 panic("No R8000 TLB refill handler yet");
2336 break;
2337
2338 default:
2339 if (!run_once) {
2340 scratch_reg = allocate_kscratch();
2341 build_setup_pgd();
2342 build_r4000_tlb_load_handler();
2343 build_r4000_tlb_store_handler();
2344 build_r4000_tlb_modify_handler();
2345 if (!cpu_has_local_ebase)
2346 build_r4000_tlb_refill_handler();
2347 flush_tlb_handlers();
2348 run_once++;
2349 }
2350 if (cpu_has_local_ebase)
2351 build_r4000_tlb_refill_handler();
2352 if (cpu_has_htw)
2353 config_htw_params();
2354
2355 }
2356 }
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