2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Synthesize TLB refill handlers at runtime.
8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
11 * Copyright (C) 2008, 2009 Cavium Networks, Inc.
12 * Copyright (C) 2011 MIPS Technologies, Inc.
14 * ... and the days got worse and worse and now you see
15 * I've gone completely out of my mind.
17 * They're coming to take me a away haha
18 * they're coming to take me a away hoho hihi haha
19 * to the funny farm where code is beautiful all the time ...
21 * (Condolences to Napoleon XIV)
24 #include <linux/bug.h>
25 #include <linux/export.h>
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/smp.h>
29 #include <linux/string.h>
30 #include <linux/cache.h>
32 #include <asm/cacheflush.h>
33 #include <asm/cpu-type.h>
34 #include <asm/pgtable.h>
37 #include <asm/setup.h>
38 #include <asm/tlbex.h>
40 static int mips_xpa_disabled
;
42 static int __init
xpa_disable(char *s
)
44 mips_xpa_disabled
= 1;
49 __setup("noxpa", xpa_disable
);
52 * TLB load/store/modify handlers.
54 * Only the fastpath gets synthesized at runtime, the slowpath for
55 * do_page_fault remains normal asm.
57 extern void tlb_do_page_fault_0(void);
58 extern void tlb_do_page_fault_1(void);
60 struct work_registers
{
69 } ____cacheline_aligned_in_smp
;
71 static struct tlb_reg_save handler_reg_save
[NR_CPUS
];
73 static inline int r45k_bvahwbug(void)
75 /* XXX: We should probe for the presence of this bug, but we don't. */
79 static inline int r4k_250MHZhwbug(void)
81 /* XXX: We should probe for the presence of this bug, but we don't. */
85 static inline int __maybe_unused
bcm1250_m3_war(void)
87 return BCM1250_M3_WAR
;
90 static inline int __maybe_unused
r10000_llsc_war(void)
92 return R10000_LLSC_WAR
;
95 static int use_bbit_insns(void)
97 switch (current_cpu_type()) {
98 case CPU_CAVIUM_OCTEON
:
99 case CPU_CAVIUM_OCTEON_PLUS
:
100 case CPU_CAVIUM_OCTEON2
:
101 case CPU_CAVIUM_OCTEON3
:
108 static int use_lwx_insns(void)
110 switch (current_cpu_type()) {
111 case CPU_CAVIUM_OCTEON2
:
112 case CPU_CAVIUM_OCTEON3
:
118 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
119 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
120 static bool scratchpad_available(void)
124 static int scratchpad_offset(int i
)
127 * CVMSEG starts at address -32768 and extends for
128 * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines.
130 i
+= 1; /* Kernel use starts at the top and works down. */
131 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
* 128 - (8 * i
) - 32768;
134 static bool scratchpad_available(void)
138 static int scratchpad_offset(int i
)
141 /* Really unreachable, but evidently some GCC want this. */
146 * Found by experiment: At least some revisions of the 4kc throw under
147 * some circumstances a machine check exception, triggered by invalid
148 * values in the index register. Delaying the tlbp instruction until
149 * after the next branch, plus adding an additional nop in front of
150 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
151 * why; it's not an issue caused by the core RTL.
154 static int m4kc_tlbp_war(void)
156 return (current_cpu_data
.processor_id
& 0xffff00) ==
157 (PRID_COMP_MIPS
| PRID_IMP_4KC
);
160 /* Handle labels (which must be positive integers). */
162 label_second_part
= 1,
167 label_split
= label_tlbw_hazard_0
+ 8,
168 label_tlbl_goaround1
,
169 label_tlbl_goaround2
,
173 label_smp_pgtable_change
,
174 label_r3000_write_probe_fail
,
175 label_large_segbits_fault
,
176 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
177 label_tlb_huge_update
,
181 UASM_L_LA(_second_part
)
184 UASM_L_LA(_vmalloc_done
)
185 /* _tlbw_hazard_x is handled differently. */
187 UASM_L_LA(_tlbl_goaround1
)
188 UASM_L_LA(_tlbl_goaround2
)
189 UASM_L_LA(_nopage_tlbl
)
190 UASM_L_LA(_nopage_tlbs
)
191 UASM_L_LA(_nopage_tlbm
)
192 UASM_L_LA(_smp_pgtable_change
)
193 UASM_L_LA(_r3000_write_probe_fail
)
194 UASM_L_LA(_large_segbits_fault
)
195 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
196 UASM_L_LA(_tlb_huge_update
)
199 static int hazard_instance
;
201 static void uasm_bgezl_hazard(u32
**p
, struct uasm_reloc
**r
, int instance
)
205 uasm_il_bgezl(p
, r
, 0, label_tlbw_hazard_0
+ instance
);
212 static void uasm_bgezl_label(struct uasm_label
**l
, u32
**p
, int instance
)
216 uasm_build_label(l
, *p
, label_tlbw_hazard_0
+ instance
);
224 * pgtable bits are assigned dynamically depending on processor feature
225 * and statically based on kernel configuration. This spits out the actual
226 * values the kernel is using. Required to make sense from disassembled
227 * TLB exception handlers.
229 static void output_pgtable_bits_defines(void)
231 #define pr_define(fmt, ...) \
232 pr_debug("#define " fmt, ##__VA_ARGS__)
234 pr_debug("#include <asm/asm.h>\n");
235 pr_debug("#include <asm/regdef.h>\n");
238 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT
);
239 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT
);
240 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT
);
241 pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT
);
242 pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT
);
243 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
244 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT
);
246 #ifdef _PAGE_NO_EXEC_SHIFT
248 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT
);
250 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT
);
251 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT
);
252 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT
);
253 pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT
);
257 static inline void dump_handler(const char *symbol
, const u32
*handler
, int count
)
261 pr_debug("LEAF(%s)\n", symbol
);
263 pr_debug("\t.set push\n");
264 pr_debug("\t.set noreorder\n");
266 for (i
= 0; i
< count
; i
++)
267 pr_debug("\t.word\t0x%08x\t\t# %p\n", handler
[i
], &handler
[i
]);
269 pr_debug("\t.set\tpop\n");
271 pr_debug("\tEND(%s)\n", symbol
);
274 /* The only general purpose registers allowed in TLB handlers. */
278 /* Some CP0 registers */
279 #define C0_INDEX 0, 0
280 #define C0_ENTRYLO0 2, 0
281 #define C0_TCBIND 2, 2
282 #define C0_ENTRYLO1 3, 0
283 #define C0_CONTEXT 4, 0
284 #define C0_PAGEMASK 5, 0
285 #define C0_PWBASE 5, 5
286 #define C0_PWFIELD 5, 6
287 #define C0_PWSIZE 5, 7
288 #define C0_PWCTL 6, 6
289 #define C0_BADVADDR 8, 0
291 #define C0_ENTRYHI 10, 0
293 #define C0_XCONTEXT 20, 0
296 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
298 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT)
301 /* The worst case length of the handler is around 18 instructions for
302 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
303 * Maximum space available is 32 instructions for R3000 and 64
304 * instructions for R4000.
306 * We deliberately chose a buffer size of 128, so we won't scribble
307 * over anything important on overflow before we panic.
309 static u32 tlb_handler
[128];
311 /* simply assume worst case size for labels and relocs */
312 static struct uasm_label labels
[128];
313 static struct uasm_reloc relocs
[128];
315 static int check_for_high_segbits
;
316 static bool fill_includes_sw_bits
;
318 static unsigned int kscratch_used_mask
;
320 static inline int __maybe_unused
c0_kscratch(void)
322 switch (current_cpu_type()) {
331 static int allocate_kscratch(void)
334 unsigned int a
= cpu_data
[0].kscratch_mask
& ~kscratch_used_mask
;
341 r
--; /* make it zero based */
343 kscratch_used_mask
|= (1 << r
);
348 static int scratch_reg
;
350 EXPORT_SYMBOL_GPL(pgd_reg
);
351 enum vmalloc64_mode
{not_refill
, refill_scratch
, refill_noscratch
};
353 static struct work_registers
build_get_work_registers(u32
**p
)
355 struct work_registers r
;
357 if (scratch_reg
>= 0) {
358 /* Save in CPU local C0_KScratch? */
359 UASM_i_MTC0(p
, 1, c0_kscratch(), scratch_reg
);
366 if (num_possible_cpus() > 1) {
367 /* Get smp_processor_id */
368 UASM_i_CPUID_MFC0(p
, K0
, SMP_CPUID_REG
);
369 UASM_i_SRL_SAFE(p
, K0
, K0
, SMP_CPUID_REGSHIFT
);
371 /* handler_reg_save index in K0 */
372 UASM_i_SLL(p
, K0
, K0
, ilog2(sizeof(struct tlb_reg_save
)));
374 UASM_i_LA(p
, K1
, (long)&handler_reg_save
);
375 UASM_i_ADDU(p
, K0
, K0
, K1
);
377 UASM_i_LA(p
, K0
, (long)&handler_reg_save
);
379 /* K0 now points to save area, save $1 and $2 */
380 UASM_i_SW(p
, 1, offsetof(struct tlb_reg_save
, a
), K0
);
381 UASM_i_SW(p
, 2, offsetof(struct tlb_reg_save
, b
), K0
);
389 static void build_restore_work_registers(u32
**p
)
391 if (scratch_reg
>= 0) {
392 UASM_i_MFC0(p
, 1, c0_kscratch(), scratch_reg
);
395 /* K0 already points to save area, restore $1 and $2 */
396 UASM_i_LW(p
, 1, offsetof(struct tlb_reg_save
, a
), K0
);
397 UASM_i_LW(p
, 2, offsetof(struct tlb_reg_save
, b
), K0
);
400 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
403 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
404 * we cannot do r3000 under these circumstances.
406 * Declare pgd_current here instead of including mmu_context.h to avoid type
407 * conflicts for tlbmiss_handler_setup_pgd
409 extern unsigned long pgd_current
[];
412 * The R3000 TLB handler is simple.
414 static void build_r3000_tlb_refill_handler(void)
416 long pgdc
= (long)pgd_current
;
419 memset(tlb_handler
, 0, sizeof(tlb_handler
));
422 uasm_i_mfc0(&p
, K0
, C0_BADVADDR
);
423 uasm_i_lui(&p
, K1
, uasm_rel_hi(pgdc
)); /* cp0 delay */
424 uasm_i_lw(&p
, K1
, uasm_rel_lo(pgdc
), K1
);
425 uasm_i_srl(&p
, K0
, K0
, 22); /* load delay */
426 uasm_i_sll(&p
, K0
, K0
, 2);
427 uasm_i_addu(&p
, K1
, K1
, K0
);
428 uasm_i_mfc0(&p
, K0
, C0_CONTEXT
);
429 uasm_i_lw(&p
, K1
, 0, K1
); /* cp0 delay */
430 uasm_i_andi(&p
, K0
, K0
, 0xffc); /* load delay */
431 uasm_i_addu(&p
, K1
, K1
, K0
);
432 uasm_i_lw(&p
, K0
, 0, K1
);
433 uasm_i_nop(&p
); /* load delay */
434 uasm_i_mtc0(&p
, K0
, C0_ENTRYLO0
);
435 uasm_i_mfc0(&p
, K1
, C0_EPC
); /* cp0 delay */
436 uasm_i_tlbwr(&p
); /* cp0 delay */
438 uasm_i_rfe(&p
); /* branch delay */
440 if (p
> tlb_handler
+ 32)
441 panic("TLB refill handler space exceeded");
443 pr_debug("Wrote TLB refill handler (%u instructions).\n",
444 (unsigned int)(p
- tlb_handler
));
446 memcpy((void *)ebase
, tlb_handler
, 0x80);
447 local_flush_icache_range(ebase
, ebase
+ 0x80);
449 dump_handler("r3000_tlb_refill", (u32
*)ebase
, 32);
451 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
454 * The R4000 TLB handler is much more complicated. We have two
455 * consecutive handler areas with 32 instructions space each.
456 * Since they aren't used at the same time, we can overflow in the
457 * other one.To keep things simple, we first assume linear space,
458 * then we relocate it to the final handler layout as needed.
460 static u32 final_handler
[64];
465 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
466 * 2. A timing hazard exists for the TLBP instruction.
468 * stalling_instruction
471 * The JTLB is being read for the TLBP throughout the stall generated by the
472 * previous instruction. This is not really correct as the stalling instruction
473 * can modify the address used to access the JTLB. The failure symptom is that
474 * the TLBP instruction will use an address created for the stalling instruction
475 * and not the address held in C0_ENHI and thus report the wrong results.
477 * The software work-around is to not allow the instruction preceding the TLBP
478 * to stall - make it an NOP or some other instruction guaranteed not to stall.
480 * Errata 2 will not be fixed. This errata is also on the R5000.
482 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
484 static void __maybe_unused
build_tlb_probe_entry(u32
**p
)
486 switch (current_cpu_type()) {
487 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */
502 void build_tlb_write_entry(u32
**p
, struct uasm_label
**l
,
503 struct uasm_reloc
**r
,
504 enum tlb_write_entry wmode
)
506 void(*tlbw
)(u32
**) = NULL
;
509 case tlb_random
: tlbw
= uasm_i_tlbwr
; break;
510 case tlb_indexed
: tlbw
= uasm_i_tlbwi
; break;
513 if (cpu_has_mips_r2_r6
) {
514 if (cpu_has_mips_r2_exec_hazard
)
520 switch (current_cpu_type()) {
528 * This branch uses up a mtc0 hazard nop slot and saves
529 * two nops after the tlbw instruction.
531 uasm_bgezl_hazard(p
, r
, hazard_instance
);
533 uasm_bgezl_label(l
, p
, hazard_instance
);
547 uasm_i_nop(p
); /* QED specifies 2 nops hazard */
548 uasm_i_nop(p
); /* QED specifies 2 nops hazard */
622 panic("No TLB refill handler yet (CPU type: %d)",
627 EXPORT_SYMBOL_GPL(build_tlb_write_entry
);
629 static __maybe_unused
void build_convert_pte_to_entrylo(u32
**p
,
632 if (_PAGE_GLOBAL_SHIFT
== 0) {
633 /* pte_t is already in EntryLo format */
637 if (cpu_has_rixi
&& _PAGE_NO_EXEC
) {
638 if (fill_includes_sw_bits
) {
639 UASM_i_ROTR(p
, reg
, reg
, ilog2(_PAGE_GLOBAL
));
641 UASM_i_SRL(p
, reg
, reg
, ilog2(_PAGE_NO_EXEC
));
642 UASM_i_ROTR(p
, reg
, reg
,
643 ilog2(_PAGE_GLOBAL
) - ilog2(_PAGE_NO_EXEC
));
646 #ifdef CONFIG_PHYS_ADDR_T_64BIT
647 uasm_i_dsrl_safe(p
, reg
, reg
, ilog2(_PAGE_GLOBAL
));
649 UASM_i_SRL(p
, reg
, reg
, ilog2(_PAGE_GLOBAL
));
654 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
656 static void build_restore_pagemask(u32
**p
, struct uasm_reloc
**r
,
657 unsigned int tmp
, enum label_id lid
,
660 if (restore_scratch
) {
661 /* Reset default page size */
662 if (PM_DEFAULT_MASK
>> 16) {
663 uasm_i_lui(p
, tmp
, PM_DEFAULT_MASK
>> 16);
664 uasm_i_ori(p
, tmp
, tmp
, PM_DEFAULT_MASK
& 0xffff);
665 uasm_i_mtc0(p
, tmp
, C0_PAGEMASK
);
666 uasm_il_b(p
, r
, lid
);
667 } else if (PM_DEFAULT_MASK
) {
668 uasm_i_ori(p
, tmp
, 0, PM_DEFAULT_MASK
);
669 uasm_i_mtc0(p
, tmp
, C0_PAGEMASK
);
670 uasm_il_b(p
, r
, lid
);
672 uasm_i_mtc0(p
, 0, C0_PAGEMASK
);
673 uasm_il_b(p
, r
, lid
);
675 if (scratch_reg
>= 0)
676 UASM_i_MFC0(p
, 1, c0_kscratch(), scratch_reg
);
678 UASM_i_LW(p
, 1, scratchpad_offset(0), 0);
680 /* Reset default page size */
681 if (PM_DEFAULT_MASK
>> 16) {
682 uasm_i_lui(p
, tmp
, PM_DEFAULT_MASK
>> 16);
683 uasm_i_ori(p
, tmp
, tmp
, PM_DEFAULT_MASK
& 0xffff);
684 uasm_il_b(p
, r
, lid
);
685 uasm_i_mtc0(p
, tmp
, C0_PAGEMASK
);
686 } else if (PM_DEFAULT_MASK
) {
687 uasm_i_ori(p
, tmp
, 0, PM_DEFAULT_MASK
);
688 uasm_il_b(p
, r
, lid
);
689 uasm_i_mtc0(p
, tmp
, C0_PAGEMASK
);
691 uasm_il_b(p
, r
, lid
);
692 uasm_i_mtc0(p
, 0, C0_PAGEMASK
);
697 static void build_huge_tlb_write_entry(u32
**p
, struct uasm_label
**l
,
698 struct uasm_reloc
**r
,
700 enum tlb_write_entry wmode
,
703 /* Set huge page tlb entry size */
704 uasm_i_lui(p
, tmp
, PM_HUGE_MASK
>> 16);
705 uasm_i_ori(p
, tmp
, tmp
, PM_HUGE_MASK
& 0xffff);
706 uasm_i_mtc0(p
, tmp
, C0_PAGEMASK
);
708 build_tlb_write_entry(p
, l
, r
, wmode
);
710 build_restore_pagemask(p
, r
, tmp
, label_leave
, restore_scratch
);
714 * Check if Huge PTE is present, if so then jump to LABEL.
717 build_is_huge_pte(u32
**p
, struct uasm_reloc
**r
, unsigned int tmp
,
718 unsigned int pmd
, int lid
)
720 UASM_i_LW(p
, tmp
, 0, pmd
);
721 if (use_bbit_insns()) {
722 uasm_il_bbit1(p
, r
, tmp
, ilog2(_PAGE_HUGE
), lid
);
724 uasm_i_andi(p
, tmp
, tmp
, _PAGE_HUGE
);
725 uasm_il_bnez(p
, r
, tmp
, lid
);
729 static void build_huge_update_entries(u32
**p
, unsigned int pte
,
735 * A huge PTE describes an area the size of the
736 * configured huge page size. This is twice the
737 * of the large TLB entry size we intend to use.
738 * A TLB entry half the size of the configured
739 * huge page size is configured into entrylo0
740 * and entrylo1 to cover the contiguous huge PTE
743 small_sequence
= (HPAGE_SIZE
>> 7) < 0x10000;
745 /* We can clobber tmp. It isn't used after this.*/
747 uasm_i_lui(p
, tmp
, HPAGE_SIZE
>> (7 + 16));
749 build_convert_pte_to_entrylo(p
, pte
);
750 UASM_i_MTC0(p
, pte
, C0_ENTRYLO0
); /* load it */
751 /* convert to entrylo1 */
753 UASM_i_ADDIU(p
, pte
, pte
, HPAGE_SIZE
>> 7);
755 UASM_i_ADDU(p
, pte
, pte
, tmp
);
757 UASM_i_MTC0(p
, pte
, C0_ENTRYLO1
); /* load it */
760 static void build_huge_handler_tail(u32
**p
, struct uasm_reloc
**r
,
761 struct uasm_label
**l
,
767 UASM_i_SC(p
, pte
, 0, ptr
);
768 uasm_il_beqz(p
, r
, pte
, label_tlb_huge_update
);
769 UASM_i_LW(p
, pte
, 0, ptr
); /* Needed because SC killed our PTE */
771 UASM_i_SW(p
, pte
, 0, ptr
);
773 if (cpu_has_ftlb
&& flush
) {
774 BUG_ON(!cpu_has_tlbinv
);
776 UASM_i_MFC0(p
, ptr
, C0_ENTRYHI
);
777 uasm_i_ori(p
, ptr
, ptr
, MIPS_ENTRYHI_EHINV
);
778 UASM_i_MTC0(p
, ptr
, C0_ENTRYHI
);
779 build_tlb_write_entry(p
, l
, r
, tlb_indexed
);
781 uasm_i_xori(p
, ptr
, ptr
, MIPS_ENTRYHI_EHINV
);
782 UASM_i_MTC0(p
, ptr
, C0_ENTRYHI
);
783 build_huge_update_entries(p
, pte
, ptr
);
784 build_huge_tlb_write_entry(p
, l
, r
, pte
, tlb_random
, 0);
789 build_huge_update_entries(p
, pte
, ptr
);
790 build_huge_tlb_write_entry(p
, l
, r
, pte
, tlb_indexed
, 0);
792 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
796 * TMP and PTR are scratch.
797 * TMP will be clobbered, PTR will hold the pmd entry.
799 void build_get_pmde64(u32
**p
, struct uasm_label
**l
, struct uasm_reloc
**r
,
800 unsigned int tmp
, unsigned int ptr
)
802 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
803 long pgdc
= (long)pgd_current
;
806 * The vmalloc handling is not in the hotpath.
808 uasm_i_dmfc0(p
, tmp
, C0_BADVADDR
);
810 if (check_for_high_segbits
) {
812 * The kernel currently implicitely assumes that the
813 * MIPS SEGBITS parameter for the processor is
814 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never
815 * allocate virtual addresses outside the maximum
816 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But
817 * that doesn't prevent user code from accessing the
818 * higher xuseg addresses. Here, we make sure that
819 * everything but the lower xuseg addresses goes down
820 * the module_alloc/vmalloc path.
822 uasm_i_dsrl_safe(p
, ptr
, tmp
, PGDIR_SHIFT
+ PGD_ORDER
+ PAGE_SHIFT
- 3);
823 uasm_il_bnez(p
, r
, ptr
, label_vmalloc
);
825 uasm_il_bltz(p
, r
, tmp
, label_vmalloc
);
827 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
830 /* pgd is in pgd_reg */
832 UASM_i_MFC0(p
, ptr
, C0_PWBASE
);
834 UASM_i_MFC0(p
, ptr
, c0_kscratch(), pgd_reg
);
836 #if defined(CONFIG_MIPS_PGD_C0_CONTEXT)
838 * &pgd << 11 stored in CONTEXT [23..63].
840 UASM_i_MFC0(p
, ptr
, C0_CONTEXT
);
842 /* Clear lower 23 bits of context. */
843 uasm_i_dins(p
, ptr
, 0, 0, 23);
845 /* 1 0 1 0 1 << 6 xkphys cached */
846 uasm_i_ori(p
, ptr
, ptr
, 0x540);
847 uasm_i_drotr(p
, ptr
, ptr
, 11);
848 #elif defined(CONFIG_SMP)
849 UASM_i_CPUID_MFC0(p
, ptr
, SMP_CPUID_REG
);
850 uasm_i_dsrl_safe(p
, ptr
, ptr
, SMP_CPUID_PTRSHIFT
);
851 UASM_i_LA_mostly(p
, tmp
, pgdc
);
852 uasm_i_daddu(p
, ptr
, ptr
, tmp
);
853 uasm_i_dmfc0(p
, tmp
, C0_BADVADDR
);
854 uasm_i_ld(p
, ptr
, uasm_rel_lo(pgdc
), ptr
);
856 UASM_i_LA_mostly(p
, ptr
, pgdc
);
857 uasm_i_ld(p
, ptr
, uasm_rel_lo(pgdc
), ptr
);
861 uasm_l_vmalloc_done(l
, *p
);
863 /* get pgd offset in bytes */
864 uasm_i_dsrl_safe(p
, tmp
, tmp
, PGDIR_SHIFT
- 3);
866 uasm_i_andi(p
, tmp
, tmp
, (PTRS_PER_PGD
- 1)<<3);
867 uasm_i_daddu(p
, ptr
, ptr
, tmp
); /* add in pgd offset */
868 #ifndef __PAGETABLE_PUD_FOLDED
869 uasm_i_dmfc0(p
, tmp
, C0_BADVADDR
); /* get faulting address */
870 uasm_i_ld(p
, ptr
, 0, ptr
); /* get pud pointer */
871 uasm_i_dsrl_safe(p
, tmp
, tmp
, PUD_SHIFT
- 3); /* get pud offset in bytes */
872 uasm_i_andi(p
, tmp
, tmp
, (PTRS_PER_PUD
- 1) << 3);
873 uasm_i_daddu(p
, ptr
, ptr
, tmp
); /* add in pud offset */
875 #ifndef __PAGETABLE_PMD_FOLDED
876 uasm_i_dmfc0(p
, tmp
, C0_BADVADDR
); /* get faulting address */
877 uasm_i_ld(p
, ptr
, 0, ptr
); /* get pmd pointer */
878 uasm_i_dsrl_safe(p
, tmp
, tmp
, PMD_SHIFT
-3); /* get pmd offset in bytes */
879 uasm_i_andi(p
, tmp
, tmp
, (PTRS_PER_PMD
- 1)<<3);
880 uasm_i_daddu(p
, ptr
, ptr
, tmp
); /* add in pmd offset */
883 EXPORT_SYMBOL_GPL(build_get_pmde64
);
886 * BVADDR is the faulting address, PTR is scratch.
887 * PTR will hold the pgd for vmalloc.
890 build_get_pgd_vmalloc64(u32
**p
, struct uasm_label
**l
, struct uasm_reloc
**r
,
891 unsigned int bvaddr
, unsigned int ptr
,
892 enum vmalloc64_mode mode
)
894 long swpd
= (long)swapper_pg_dir
;
895 int single_insn_swpd
;
896 int did_vmalloc_branch
= 0;
898 single_insn_swpd
= uasm_in_compat_space_p(swpd
) && !uasm_rel_lo(swpd
);
900 uasm_l_vmalloc(l
, *p
);
902 if (mode
!= not_refill
&& check_for_high_segbits
) {
903 if (single_insn_swpd
) {
904 uasm_il_bltz(p
, r
, bvaddr
, label_vmalloc_done
);
905 uasm_i_lui(p
, ptr
, uasm_rel_hi(swpd
));
906 did_vmalloc_branch
= 1;
909 uasm_il_bgez(p
, r
, bvaddr
, label_large_segbits_fault
);
912 if (!did_vmalloc_branch
) {
913 if (single_insn_swpd
) {
914 uasm_il_b(p
, r
, label_vmalloc_done
);
915 uasm_i_lui(p
, ptr
, uasm_rel_hi(swpd
));
917 UASM_i_LA_mostly(p
, ptr
, swpd
);
918 uasm_il_b(p
, r
, label_vmalloc_done
);
919 if (uasm_in_compat_space_p(swpd
))
920 uasm_i_addiu(p
, ptr
, ptr
, uasm_rel_lo(swpd
));
922 uasm_i_daddiu(p
, ptr
, ptr
, uasm_rel_lo(swpd
));
925 if (mode
!= not_refill
&& check_for_high_segbits
) {
926 uasm_l_large_segbits_fault(l
, *p
);
928 * We get here if we are an xsseg address, or if we are
929 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary.
931 * Ignoring xsseg (assume disabled so would generate
932 * (address errors?), the only remaining possibility
933 * is the upper xuseg addresses. On processors with
934 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these
935 * addresses would have taken an address error. We try
936 * to mimic that here by taking a load/istream page
939 UASM_i_LA(p
, ptr
, (unsigned long)tlb_do_page_fault_0
);
942 if (mode
== refill_scratch
) {
943 if (scratch_reg
>= 0)
944 UASM_i_MFC0(p
, 1, c0_kscratch(), scratch_reg
);
946 UASM_i_LW(p
, 1, scratchpad_offset(0), 0);
953 #else /* !CONFIG_64BIT */
956 * TMP and PTR are scratch.
957 * TMP will be clobbered, PTR will hold the pgd entry.
959 void build_get_pgde32(u32
**p
, unsigned int tmp
, unsigned int ptr
)
962 /* pgd is in pgd_reg */
963 uasm_i_mfc0(p
, ptr
, c0_kscratch(), pgd_reg
);
964 uasm_i_mfc0(p
, tmp
, C0_BADVADDR
); /* get faulting address */
966 long pgdc
= (long)pgd_current
;
968 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
970 uasm_i_mfc0(p
, ptr
, SMP_CPUID_REG
);
971 UASM_i_LA_mostly(p
, tmp
, pgdc
);
972 uasm_i_srl(p
, ptr
, ptr
, SMP_CPUID_PTRSHIFT
);
973 uasm_i_addu(p
, ptr
, tmp
, ptr
);
975 UASM_i_LA_mostly(p
, ptr
, pgdc
);
977 uasm_i_mfc0(p
, tmp
, C0_BADVADDR
); /* get faulting address */
978 uasm_i_lw(p
, ptr
, uasm_rel_lo(pgdc
), ptr
);
980 uasm_i_srl(p
, tmp
, tmp
, PGDIR_SHIFT
); /* get pgd only bits */
981 uasm_i_sll(p
, tmp
, tmp
, PGD_T_LOG2
);
982 uasm_i_addu(p
, ptr
, ptr
, tmp
); /* add in pgd offset */
984 EXPORT_SYMBOL_GPL(build_get_pgde32
);
986 #endif /* !CONFIG_64BIT */
988 static void build_adjust_context(u32
**p
, unsigned int ctx
)
990 unsigned int shift
= 4 - (PTE_T_LOG2
+ 1) + PAGE_SHIFT
- 12;
991 unsigned int mask
= (PTRS_PER_PTE
/ 2 - 1) << (PTE_T_LOG2
+ 1);
993 switch (current_cpu_type()) {
1010 UASM_i_SRL(p
, ctx
, ctx
, shift
);
1011 uasm_i_andi(p
, ctx
, ctx
, mask
);
1014 void build_get_ptep(u32
**p
, unsigned int tmp
, unsigned int ptr
)
1017 * Bug workaround for the Nevada. It seems as if under certain
1018 * circumstances the move from cp0_context might produce a
1019 * bogus result when the mfc0 instruction and its consumer are
1020 * in a different cacheline or a load instruction, probably any
1021 * memory reference, is between them.
1023 switch (current_cpu_type()) {
1025 UASM_i_LW(p
, ptr
, 0, ptr
);
1026 GET_CONTEXT(p
, tmp
); /* get context reg */
1030 GET_CONTEXT(p
, tmp
); /* get context reg */
1031 UASM_i_LW(p
, ptr
, 0, ptr
);
1035 build_adjust_context(p
, tmp
);
1036 UASM_i_ADDU(p
, ptr
, ptr
, tmp
); /* add in offset */
1038 EXPORT_SYMBOL_GPL(build_get_ptep
);
1040 void build_update_entries(u32
**p
, unsigned int tmp
, unsigned int ptep
)
1042 int pte_off_even
= 0;
1043 int pte_off_odd
= sizeof(pte_t
);
1045 #if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_PHYS_ADDR_T_64BIT)
1046 /* The low 32 bits of EntryLo is stored in pte_high */
1047 pte_off_even
+= offsetof(pte_t
, pte_high
);
1048 pte_off_odd
+= offsetof(pte_t
, pte_high
);
1051 if (IS_ENABLED(CONFIG_XPA
)) {
1052 uasm_i_lw(p
, tmp
, pte_off_even
, ptep
); /* even pte */
1053 UASM_i_ROTR(p
, tmp
, tmp
, ilog2(_PAGE_GLOBAL
));
1054 UASM_i_MTC0(p
, tmp
, C0_ENTRYLO0
);
1056 if (cpu_has_xpa
&& !mips_xpa_disabled
) {
1057 uasm_i_lw(p
, tmp
, 0, ptep
);
1058 uasm_i_ext(p
, tmp
, tmp
, 0, 24);
1059 uasm_i_mthc0(p
, tmp
, C0_ENTRYLO0
);
1062 uasm_i_lw(p
, tmp
, pte_off_odd
, ptep
); /* odd pte */
1063 UASM_i_ROTR(p
, tmp
, tmp
, ilog2(_PAGE_GLOBAL
));
1064 UASM_i_MTC0(p
, tmp
, C0_ENTRYLO1
);
1066 if (cpu_has_xpa
&& !mips_xpa_disabled
) {
1067 uasm_i_lw(p
, tmp
, sizeof(pte_t
), ptep
);
1068 uasm_i_ext(p
, tmp
, tmp
, 0, 24);
1069 uasm_i_mthc0(p
, tmp
, C0_ENTRYLO1
);
1074 UASM_i_LW(p
, tmp
, pte_off_even
, ptep
); /* get even pte */
1075 UASM_i_LW(p
, ptep
, pte_off_odd
, ptep
); /* get odd pte */
1076 if (r45k_bvahwbug())
1077 build_tlb_probe_entry(p
);
1078 build_convert_pte_to_entrylo(p
, tmp
);
1079 if (r4k_250MHZhwbug())
1080 UASM_i_MTC0(p
, 0, C0_ENTRYLO0
);
1081 UASM_i_MTC0(p
, tmp
, C0_ENTRYLO0
); /* load it */
1082 build_convert_pte_to_entrylo(p
, ptep
);
1083 if (r45k_bvahwbug())
1084 uasm_i_mfc0(p
, tmp
, C0_INDEX
);
1085 if (r4k_250MHZhwbug())
1086 UASM_i_MTC0(p
, 0, C0_ENTRYLO1
);
1087 UASM_i_MTC0(p
, ptep
, C0_ENTRYLO1
); /* load it */
1089 EXPORT_SYMBOL_GPL(build_update_entries
);
1091 struct mips_huge_tlb_info
{
1093 int restore_scratch
;
1094 bool need_reload_pte
;
1097 static struct mips_huge_tlb_info
1098 build_fast_tlb_refill_handler (u32
**p
, struct uasm_label
**l
,
1099 struct uasm_reloc
**r
, unsigned int tmp
,
1100 unsigned int ptr
, int c0_scratch_reg
)
1102 struct mips_huge_tlb_info rv
;
1103 unsigned int even
, odd
;
1104 int vmalloc_branch_delay_filled
= 0;
1105 const int scratch
= 1; /* Our extra working register */
1107 rv
.huge_pte
= scratch
;
1108 rv
.restore_scratch
= 0;
1109 rv
.need_reload_pte
= false;
1111 if (check_for_high_segbits
) {
1112 UASM_i_MFC0(p
, tmp
, C0_BADVADDR
);
1115 UASM_i_MFC0(p
, ptr
, c0_kscratch(), pgd_reg
);
1117 UASM_i_MFC0(p
, ptr
, C0_CONTEXT
);
1119 if (c0_scratch_reg
>= 0)
1120 UASM_i_MTC0(p
, scratch
, c0_kscratch(), c0_scratch_reg
);
1122 UASM_i_SW(p
, scratch
, scratchpad_offset(0), 0);
1124 uasm_i_dsrl_safe(p
, scratch
, tmp
,
1125 PGDIR_SHIFT
+ PGD_ORDER
+ PAGE_SHIFT
- 3);
1126 uasm_il_bnez(p
, r
, scratch
, label_vmalloc
);
1128 if (pgd_reg
== -1) {
1129 vmalloc_branch_delay_filled
= 1;
1130 /* Clear lower 23 bits of context. */
1131 uasm_i_dins(p
, ptr
, 0, 0, 23);
1135 UASM_i_MFC0(p
, ptr
, c0_kscratch(), pgd_reg
);
1137 UASM_i_MFC0(p
, ptr
, C0_CONTEXT
);
1139 UASM_i_MFC0(p
, tmp
, C0_BADVADDR
);
1141 if (c0_scratch_reg
>= 0)
1142 UASM_i_MTC0(p
, scratch
, c0_kscratch(), c0_scratch_reg
);
1144 UASM_i_SW(p
, scratch
, scratchpad_offset(0), 0);
1147 /* Clear lower 23 bits of context. */
1148 uasm_i_dins(p
, ptr
, 0, 0, 23);
1150 uasm_il_bltz(p
, r
, tmp
, label_vmalloc
);
1153 if (pgd_reg
== -1) {
1154 vmalloc_branch_delay_filled
= 1;
1155 /* 1 0 1 0 1 << 6 xkphys cached */
1156 uasm_i_ori(p
, ptr
, ptr
, 0x540);
1157 uasm_i_drotr(p
, ptr
, ptr
, 11);
1160 #ifdef __PAGETABLE_PMD_FOLDED
1161 #define LOC_PTEP scratch
1163 #define LOC_PTEP ptr
1166 if (!vmalloc_branch_delay_filled
)
1167 /* get pgd offset in bytes */
1168 uasm_i_dsrl_safe(p
, scratch
, tmp
, PGDIR_SHIFT
- 3);
1170 uasm_l_vmalloc_done(l
, *p
);
1174 * fall-through case = badvaddr *pgd_current
1175 * vmalloc case = badvaddr swapper_pg_dir
1178 if (vmalloc_branch_delay_filled
)
1179 /* get pgd offset in bytes */
1180 uasm_i_dsrl_safe(p
, scratch
, tmp
, PGDIR_SHIFT
- 3);
1182 #ifdef __PAGETABLE_PMD_FOLDED
1183 GET_CONTEXT(p
, tmp
); /* get context reg */
1185 uasm_i_andi(p
, scratch
, scratch
, (PTRS_PER_PGD
- 1) << 3);
1187 if (use_lwx_insns()) {
1188 UASM_i_LWX(p
, LOC_PTEP
, scratch
, ptr
);
1190 uasm_i_daddu(p
, ptr
, ptr
, scratch
); /* add in pgd offset */
1191 uasm_i_ld(p
, LOC_PTEP
, 0, ptr
); /* get pmd pointer */
1194 #ifndef __PAGETABLE_PUD_FOLDED
1195 /* get pud offset in bytes */
1196 uasm_i_dsrl_safe(p
, scratch
, tmp
, PUD_SHIFT
- 3);
1197 uasm_i_andi(p
, scratch
, scratch
, (PTRS_PER_PUD
- 1) << 3);
1199 if (use_lwx_insns()) {
1200 UASM_i_LWX(p
, ptr
, scratch
, ptr
);
1202 uasm_i_daddu(p
, ptr
, ptr
, scratch
); /* add in pmd offset */
1203 UASM_i_LW(p
, ptr
, 0, ptr
);
1205 /* ptr contains a pointer to PMD entry */
1206 /* tmp contains the address */
1209 #ifndef __PAGETABLE_PMD_FOLDED
1210 /* get pmd offset in bytes */
1211 uasm_i_dsrl_safe(p
, scratch
, tmp
, PMD_SHIFT
- 3);
1212 uasm_i_andi(p
, scratch
, scratch
, (PTRS_PER_PMD
- 1) << 3);
1213 GET_CONTEXT(p
, tmp
); /* get context reg */
1215 if (use_lwx_insns()) {
1216 UASM_i_LWX(p
, scratch
, scratch
, ptr
);
1218 uasm_i_daddu(p
, ptr
, ptr
, scratch
); /* add in pmd offset */
1219 UASM_i_LW(p
, scratch
, 0, ptr
);
1222 /* Adjust the context during the load latency. */
1223 build_adjust_context(p
, tmp
);
1225 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1226 uasm_il_bbit1(p
, r
, scratch
, ilog2(_PAGE_HUGE
), label_tlb_huge_update
);
1228 * The in the LWX case we don't want to do the load in the
1229 * delay slot. It cannot issue in the same cycle and may be
1230 * speculative and unneeded.
1232 if (use_lwx_insns())
1234 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
1237 /* build_update_entries */
1238 if (use_lwx_insns()) {
1241 UASM_i_LWX(p
, even
, scratch
, tmp
);
1242 UASM_i_ADDIU(p
, tmp
, tmp
, sizeof(pte_t
));
1243 UASM_i_LWX(p
, odd
, scratch
, tmp
);
1245 UASM_i_ADDU(p
, ptr
, scratch
, tmp
); /* add in offset */
1248 UASM_i_LW(p
, even
, 0, ptr
); /* get even pte */
1249 UASM_i_LW(p
, odd
, sizeof(pte_t
), ptr
); /* get odd pte */
1252 uasm_i_drotr(p
, even
, even
, ilog2(_PAGE_GLOBAL
));
1253 UASM_i_MTC0(p
, even
, C0_ENTRYLO0
); /* load it */
1254 uasm_i_drotr(p
, odd
, odd
, ilog2(_PAGE_GLOBAL
));
1256 uasm_i_dsrl_safe(p
, even
, even
, ilog2(_PAGE_GLOBAL
));
1257 UASM_i_MTC0(p
, even
, C0_ENTRYLO0
); /* load it */
1258 uasm_i_dsrl_safe(p
, odd
, odd
, ilog2(_PAGE_GLOBAL
));
1260 UASM_i_MTC0(p
, odd
, C0_ENTRYLO1
); /* load it */
1262 if (c0_scratch_reg
>= 0) {
1263 UASM_i_MFC0(p
, scratch
, c0_kscratch(), c0_scratch_reg
);
1264 build_tlb_write_entry(p
, l
, r
, tlb_random
);
1265 uasm_l_leave(l
, *p
);
1266 rv
.restore_scratch
= 1;
1267 } else if (PAGE_SHIFT
== 14 || PAGE_SHIFT
== 13) {
1268 build_tlb_write_entry(p
, l
, r
, tlb_random
);
1269 uasm_l_leave(l
, *p
);
1270 UASM_i_LW(p
, scratch
, scratchpad_offset(0), 0);
1272 UASM_i_LW(p
, scratch
, scratchpad_offset(0), 0);
1273 build_tlb_write_entry(p
, l
, r
, tlb_random
);
1274 uasm_l_leave(l
, *p
);
1275 rv
.restore_scratch
= 1;
1278 uasm_i_eret(p
); /* return from trap */
1284 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
1285 * because EXL == 0. If we wrap, we can also use the 32 instruction
1286 * slots before the XTLB refill exception handler which belong to the
1287 * unused TLB refill exception.
1289 #define MIPS64_REFILL_INSNS 32
1291 static void build_r4000_tlb_refill_handler(void)
1293 u32
*p
= tlb_handler
;
1294 struct uasm_label
*l
= labels
;
1295 struct uasm_reloc
*r
= relocs
;
1297 unsigned int final_len
;
1298 struct mips_huge_tlb_info htlb_info __maybe_unused
;
1299 enum vmalloc64_mode vmalloc_mode __maybe_unused
;
1301 memset(tlb_handler
, 0, sizeof(tlb_handler
));
1302 memset(labels
, 0, sizeof(labels
));
1303 memset(relocs
, 0, sizeof(relocs
));
1304 memset(final_handler
, 0, sizeof(final_handler
));
1306 if (IS_ENABLED(CONFIG_64BIT
) && (scratch_reg
>= 0 || scratchpad_available()) && use_bbit_insns()) {
1307 htlb_info
= build_fast_tlb_refill_handler(&p
, &l
, &r
, K0
, K1
,
1309 vmalloc_mode
= refill_scratch
;
1311 htlb_info
.huge_pte
= K0
;
1312 htlb_info
.restore_scratch
= 0;
1313 htlb_info
.need_reload_pte
= true;
1314 vmalloc_mode
= refill_noscratch
;
1316 * create the plain linear handler
1318 if (bcm1250_m3_war()) {
1319 unsigned int segbits
= 44;
1321 uasm_i_dmfc0(&p
, K0
, C0_BADVADDR
);
1322 uasm_i_dmfc0(&p
, K1
, C0_ENTRYHI
);
1323 uasm_i_xor(&p
, K0
, K0
, K1
);
1324 uasm_i_dsrl_safe(&p
, K1
, K0
, 62);
1325 uasm_i_dsrl_safe(&p
, K0
, K0
, 12 + 1);
1326 uasm_i_dsll_safe(&p
, K0
, K0
, 64 + 12 + 1 - segbits
);
1327 uasm_i_or(&p
, K0
, K0
, K1
);
1328 uasm_il_bnez(&p
, &r
, K0
, label_leave
);
1329 /* No need for uasm_i_nop */
1333 build_get_pmde64(&p
, &l
, &r
, K0
, K1
); /* get pmd in K1 */
1335 build_get_pgde32(&p
, K0
, K1
); /* get pgd in K1 */
1338 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1339 build_is_huge_pte(&p
, &r
, K0
, K1
, label_tlb_huge_update
);
1342 build_get_ptep(&p
, K0
, K1
);
1343 build_update_entries(&p
, K0
, K1
);
1344 build_tlb_write_entry(&p
, &l
, &r
, tlb_random
);
1345 uasm_l_leave(&l
, p
);
1346 uasm_i_eret(&p
); /* return from trap */
1348 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1349 uasm_l_tlb_huge_update(&l
, p
);
1350 if (htlb_info
.need_reload_pte
)
1351 UASM_i_LW(&p
, htlb_info
.huge_pte
, 0, K1
);
1352 build_huge_update_entries(&p
, htlb_info
.huge_pte
, K1
);
1353 build_huge_tlb_write_entry(&p
, &l
, &r
, K0
, tlb_random
,
1354 htlb_info
.restore_scratch
);
1358 build_get_pgd_vmalloc64(&p
, &l
, &r
, K0
, K1
, vmalloc_mode
);
1362 * Overflow check: For the 64bit handler, we need at least one
1363 * free instruction slot for the wrap-around branch. In worst
1364 * case, if the intended insertion point is a delay slot, we
1365 * need three, with the second nop'ed and the third being
1368 switch (boot_cpu_type()) {
1370 if (sizeof(long) == 4) {
1372 /* Loongson2 ebase is different than r4k, we have more space */
1373 if ((p
- tlb_handler
) > 64)
1374 panic("TLB refill handler space exceeded");
1376 * Now fold the handler in the TLB refill handler space.
1379 /* Simplest case, just copy the handler. */
1380 uasm_copy_handler(relocs
, labels
, tlb_handler
, p
, f
);
1381 final_len
= p
- tlb_handler
;
1384 if (((p
- tlb_handler
) > (MIPS64_REFILL_INSNS
* 2) - 1)
1385 || (((p
- tlb_handler
) > (MIPS64_REFILL_INSNS
* 2) - 3)
1386 && uasm_insn_has_bdelay(relocs
,
1387 tlb_handler
+ MIPS64_REFILL_INSNS
- 3)))
1388 panic("TLB refill handler space exceeded");
1390 * Now fold the handler in the TLB refill handler space.
1392 f
= final_handler
+ MIPS64_REFILL_INSNS
;
1393 if ((p
- tlb_handler
) <= MIPS64_REFILL_INSNS
) {
1394 /* Just copy the handler. */
1395 uasm_copy_handler(relocs
, labels
, tlb_handler
, p
, f
);
1396 final_len
= p
- tlb_handler
;
1398 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1399 const enum label_id ls
= label_tlb_huge_update
;
1401 const enum label_id ls
= label_vmalloc
;
1407 for (i
= 0; i
< ARRAY_SIZE(labels
) && labels
[i
].lab
!= ls
; i
++)
1409 BUG_ON(i
== ARRAY_SIZE(labels
));
1410 split
= labels
[i
].addr
;
1413 * See if we have overflown one way or the other.
1415 if (split
> tlb_handler
+ MIPS64_REFILL_INSNS
||
1416 split
< p
- MIPS64_REFILL_INSNS
)
1421 * Split two instructions before the end. One
1422 * for the branch and one for the instruction
1423 * in the delay slot.
1425 split
= tlb_handler
+ MIPS64_REFILL_INSNS
- 2;
1428 * If the branch would fall in a delay slot,
1429 * we must back up an additional instruction
1430 * so that it is no longer in a delay slot.
1432 if (uasm_insn_has_bdelay(relocs
, split
- 1))
1435 /* Copy first part of the handler. */
1436 uasm_copy_handler(relocs
, labels
, tlb_handler
, split
, f
);
1437 f
+= split
- tlb_handler
;
1440 /* Insert branch. */
1441 uasm_l_split(&l
, final_handler
);
1442 uasm_il_b(&f
, &r
, label_split
);
1443 if (uasm_insn_has_bdelay(relocs
, split
))
1446 uasm_copy_handler(relocs
, labels
,
1447 split
, split
+ 1, f
);
1448 uasm_move_labels(labels
, f
, f
+ 1, -1);
1454 /* Copy the rest of the handler. */
1455 uasm_copy_handler(relocs
, labels
, split
, p
, final_handler
);
1456 final_len
= (f
- (final_handler
+ MIPS64_REFILL_INSNS
)) +
1463 uasm_resolve_relocs(relocs
, labels
);
1464 pr_debug("Wrote TLB refill handler (%u instructions).\n",
1467 memcpy((void *)ebase
, final_handler
, 0x100);
1468 local_flush_icache_range(ebase
, ebase
+ 0x100);
1470 dump_handler("r4000_tlb_refill", (u32
*)ebase
, 64);
1473 static void setup_pw(void)
1475 unsigned long pgd_i
, pgd_w
;
1476 #ifndef __PAGETABLE_PMD_FOLDED
1477 unsigned long pmd_i
, pmd_w
;
1479 unsigned long pt_i
, pt_w
;
1480 unsigned long pte_i
, pte_w
;
1481 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1484 psn
= ilog2(_PAGE_HUGE
); /* bit used to indicate huge page */
1486 pgd_i
= PGDIR_SHIFT
; /* 1st level PGD */
1487 #ifndef __PAGETABLE_PMD_FOLDED
1488 pgd_w
= PGDIR_SHIFT
- PMD_SHIFT
+ PGD_ORDER
;
1490 pmd_i
= PMD_SHIFT
; /* 2nd level PMD */
1491 pmd_w
= PMD_SHIFT
- PAGE_SHIFT
;
1493 pgd_w
= PGDIR_SHIFT
- PAGE_SHIFT
+ PGD_ORDER
;
1496 pt_i
= PAGE_SHIFT
; /* 3rd level PTE */
1497 pt_w
= PAGE_SHIFT
- 3;
1499 pte_i
= ilog2(_PAGE_GLOBAL
);
1502 #ifndef __PAGETABLE_PMD_FOLDED
1503 write_c0_pwfield(pgd_i
<< 24 | pmd_i
<< 12 | pt_i
<< 6 | pte_i
);
1504 write_c0_pwsize(1 << 30 | pgd_w
<< 24 | pmd_w
<< 12 | pt_w
<< 6 | pte_w
);
1506 write_c0_pwfield(pgd_i
<< 24 | pt_i
<< 6 | pte_i
);
1507 write_c0_pwsize(1 << 30 | pgd_w
<< 24 | pt_w
<< 6 | pte_w
);
1510 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1511 write_c0_pwctl(1 << 6 | psn
);
1513 write_c0_kpgd(swapper_pg_dir
);
1514 kscratch_used_mask
|= (1 << 7); /* KScratch6 is used for KPGD */
1517 static void build_loongson3_tlb_refill_handler(void)
1519 u32
*p
= tlb_handler
;
1520 struct uasm_label
*l
= labels
;
1521 struct uasm_reloc
*r
= relocs
;
1523 memset(labels
, 0, sizeof(labels
));
1524 memset(relocs
, 0, sizeof(relocs
));
1525 memset(tlb_handler
, 0, sizeof(tlb_handler
));
1527 if (check_for_high_segbits
) {
1528 uasm_i_dmfc0(&p
, K0
, C0_BADVADDR
);
1529 uasm_i_dsrl_safe(&p
, K1
, K0
, PGDIR_SHIFT
+ PGD_ORDER
+ PAGE_SHIFT
- 3);
1530 uasm_il_beqz(&p
, &r
, K1
, label_vmalloc
);
1533 uasm_il_bgez(&p
, &r
, K0
, label_large_segbits_fault
);
1535 uasm_l_vmalloc(&l
, p
);
1538 uasm_i_dmfc0(&p
, K1
, C0_PGD
);
1540 uasm_i_lddir(&p
, K0
, K1
, 3); /* global page dir */
1541 #ifndef __PAGETABLE_PMD_FOLDED
1542 uasm_i_lddir(&p
, K1
, K0
, 1); /* middle page dir */
1544 uasm_i_ldpte(&p
, K1
, 0); /* even */
1545 uasm_i_ldpte(&p
, K1
, 1); /* odd */
1548 /* restore page mask */
1549 if (PM_DEFAULT_MASK
>> 16) {
1550 uasm_i_lui(&p
, K0
, PM_DEFAULT_MASK
>> 16);
1551 uasm_i_ori(&p
, K0
, K0
, PM_DEFAULT_MASK
& 0xffff);
1552 uasm_i_mtc0(&p
, K0
, C0_PAGEMASK
);
1553 } else if (PM_DEFAULT_MASK
) {
1554 uasm_i_ori(&p
, K0
, 0, PM_DEFAULT_MASK
);
1555 uasm_i_mtc0(&p
, K0
, C0_PAGEMASK
);
1557 uasm_i_mtc0(&p
, 0, C0_PAGEMASK
);
1562 if (check_for_high_segbits
) {
1563 uasm_l_large_segbits_fault(&l
, p
);
1564 UASM_i_LA(&p
, K1
, (unsigned long)tlb_do_page_fault_0
);
1569 uasm_resolve_relocs(relocs
, labels
);
1570 memcpy((void *)(ebase
+ 0x80), tlb_handler
, 0x80);
1571 local_flush_icache_range(ebase
+ 0x80, ebase
+ 0x100);
1572 dump_handler("loongson3_tlb_refill", (u32
*)(ebase
+ 0x80), 32);
1575 extern u32 handle_tlbl
[], handle_tlbl_end
[];
1576 extern u32 handle_tlbs
[], handle_tlbs_end
[];
1577 extern u32 handle_tlbm
[], handle_tlbm_end
[];
1578 extern u32 tlbmiss_handler_setup_pgd_start
[];
1579 extern u32 tlbmiss_handler_setup_pgd
[];
1580 EXPORT_SYMBOL_GPL(tlbmiss_handler_setup_pgd
);
1581 extern u32 tlbmiss_handler_setup_pgd_end
[];
1583 static void build_setup_pgd(void)
1586 const int __maybe_unused a1
= 5;
1587 const int __maybe_unused a2
= 6;
1588 u32
*p
= tlbmiss_handler_setup_pgd_start
;
1589 const int tlbmiss_handler_setup_pgd_size
=
1590 tlbmiss_handler_setup_pgd_end
- tlbmiss_handler_setup_pgd_start
;
1591 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1592 long pgdc
= (long)pgd_current
;
1595 memset(tlbmiss_handler_setup_pgd
, 0, tlbmiss_handler_setup_pgd_size
*
1596 sizeof(tlbmiss_handler_setup_pgd
[0]));
1597 memset(labels
, 0, sizeof(labels
));
1598 memset(relocs
, 0, sizeof(relocs
));
1599 pgd_reg
= allocate_kscratch();
1600 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
1601 if (pgd_reg
== -1) {
1602 struct uasm_label
*l
= labels
;
1603 struct uasm_reloc
*r
= relocs
;
1605 /* PGD << 11 in c0_Context */
1607 * If it is a ckseg0 address, convert to a physical
1608 * address. Shifting right by 29 and adding 4 will
1609 * result in zero for these addresses.
1612 UASM_i_SRA(&p
, a1
, a0
, 29);
1613 UASM_i_ADDIU(&p
, a1
, a1
, 4);
1614 uasm_il_bnez(&p
, &r
, a1
, label_tlbl_goaround1
);
1616 uasm_i_dinsm(&p
, a0
, 0, 29, 64 - 29);
1617 uasm_l_tlbl_goaround1(&l
, p
);
1618 UASM_i_SLL(&p
, a0
, a0
, 11);
1620 UASM_i_MTC0(&p
, a0
, C0_CONTEXT
);
1622 /* PGD in c0_KScratch */
1625 UASM_i_MTC0(&p
, a0
, C0_PWBASE
);
1627 UASM_i_MTC0(&p
, a0
, c0_kscratch(), pgd_reg
);
1631 /* Save PGD to pgd_current[smp_processor_id()] */
1632 UASM_i_CPUID_MFC0(&p
, a1
, SMP_CPUID_REG
);
1633 UASM_i_SRL_SAFE(&p
, a1
, a1
, SMP_CPUID_PTRSHIFT
);
1634 UASM_i_LA_mostly(&p
, a2
, pgdc
);
1635 UASM_i_ADDU(&p
, a2
, a2
, a1
);
1636 UASM_i_SW(&p
, a0
, uasm_rel_lo(pgdc
), a2
);
1638 UASM_i_LA_mostly(&p
, a2
, pgdc
);
1639 UASM_i_SW(&p
, a0
, uasm_rel_lo(pgdc
), a2
);
1643 /* if pgd_reg is allocated, save PGD also to scratch register */
1645 UASM_i_MTC0(&p
, a0
, c0_kscratch(), pgd_reg
);
1649 if (p
>= tlbmiss_handler_setup_pgd_end
)
1650 panic("tlbmiss_handler_setup_pgd space exceeded");
1652 uasm_resolve_relocs(relocs
, labels
);
1653 pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n",
1654 (unsigned int)(p
- tlbmiss_handler_setup_pgd
));
1656 dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd
,
1657 tlbmiss_handler_setup_pgd_size
);
1661 iPTE_LW(u32
**p
, unsigned int pte
, unsigned int ptr
)
1664 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1666 uasm_i_lld(p
, pte
, 0, ptr
);
1669 UASM_i_LL(p
, pte
, 0, ptr
);
1671 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1673 uasm_i_ld(p
, pte
, 0, ptr
);
1676 UASM_i_LW(p
, pte
, 0, ptr
);
1681 iPTE_SW(u32
**p
, struct uasm_reloc
**r
, unsigned int pte
, unsigned int ptr
,
1682 unsigned int mode
, unsigned int scratch
)
1684 unsigned int hwmode
= mode
& (_PAGE_VALID
| _PAGE_DIRTY
);
1685 unsigned int swmode
= mode
& ~hwmode
;
1687 if (IS_ENABLED(CONFIG_XPA
) && !cpu_has_64bits
) {
1688 uasm_i_lui(p
, scratch
, swmode
>> 16);
1689 uasm_i_or(p
, pte
, pte
, scratch
);
1690 BUG_ON(swmode
& 0xffff);
1692 uasm_i_ori(p
, pte
, pte
, mode
);
1696 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1698 uasm_i_scd(p
, pte
, 0, ptr
);
1701 UASM_i_SC(p
, pte
, 0, ptr
);
1703 if (r10000_llsc_war())
1704 uasm_il_beqzl(p
, r
, pte
, label_smp_pgtable_change
);
1706 uasm_il_beqz(p
, r
, pte
, label_smp_pgtable_change
);
1708 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1709 if (!cpu_has_64bits
) {
1710 /* no uasm_i_nop needed */
1711 uasm_i_ll(p
, pte
, sizeof(pte_t
) / 2, ptr
);
1712 uasm_i_ori(p
, pte
, pte
, hwmode
);
1713 BUG_ON(hwmode
& ~0xffff);
1714 uasm_i_sc(p
, pte
, sizeof(pte_t
) / 2, ptr
);
1715 uasm_il_beqz(p
, r
, pte
, label_smp_pgtable_change
);
1716 /* no uasm_i_nop needed */
1717 uasm_i_lw(p
, pte
, 0, ptr
);
1724 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1726 uasm_i_sd(p
, pte
, 0, ptr
);
1729 UASM_i_SW(p
, pte
, 0, ptr
);
1731 # ifdef CONFIG_PHYS_ADDR_T_64BIT
1732 if (!cpu_has_64bits
) {
1733 uasm_i_lw(p
, pte
, sizeof(pte_t
) / 2, ptr
);
1734 uasm_i_ori(p
, pte
, pte
, hwmode
);
1735 BUG_ON(hwmode
& ~0xffff);
1736 uasm_i_sw(p
, pte
, sizeof(pte_t
) / 2, ptr
);
1737 uasm_i_lw(p
, pte
, 0, ptr
);
1744 * Check if PTE is present, if not then jump to LABEL. PTR points to
1745 * the page table where this PTE is located, PTE will be re-loaded
1746 * with it's original value.
1749 build_pte_present(u32
**p
, struct uasm_reloc
**r
,
1750 int pte
, int ptr
, int scratch
, enum label_id lid
)
1752 int t
= scratch
>= 0 ? scratch
: pte
;
1756 if (use_bbit_insns()) {
1757 uasm_il_bbit0(p
, r
, pte
, ilog2(_PAGE_PRESENT
), lid
);
1760 if (_PAGE_PRESENT_SHIFT
) {
1761 uasm_i_srl(p
, t
, cur
, _PAGE_PRESENT_SHIFT
);
1764 uasm_i_andi(p
, t
, cur
, 1);
1765 uasm_il_beqz(p
, r
, t
, lid
);
1767 /* You lose the SMP race :-(*/
1768 iPTE_LW(p
, pte
, ptr
);
1771 if (_PAGE_PRESENT_SHIFT
) {
1772 uasm_i_srl(p
, t
, cur
, _PAGE_PRESENT_SHIFT
);
1775 uasm_i_andi(p
, t
, cur
,
1776 (_PAGE_PRESENT
| _PAGE_NO_READ
) >> _PAGE_PRESENT_SHIFT
);
1777 uasm_i_xori(p
, t
, t
, _PAGE_PRESENT
>> _PAGE_PRESENT_SHIFT
);
1778 uasm_il_bnez(p
, r
, t
, lid
);
1780 /* You lose the SMP race :-(*/
1781 iPTE_LW(p
, pte
, ptr
);
1785 /* Make PTE valid, store result in PTR. */
1787 build_make_valid(u32
**p
, struct uasm_reloc
**r
, unsigned int pte
,
1788 unsigned int ptr
, unsigned int scratch
)
1790 unsigned int mode
= _PAGE_VALID
| _PAGE_ACCESSED
;
1792 iPTE_SW(p
, r
, pte
, ptr
, mode
, scratch
);
1796 * Check if PTE can be written to, if not branch to LABEL. Regardless
1797 * restore PTE with value from PTR when done.
1800 build_pte_writable(u32
**p
, struct uasm_reloc
**r
,
1801 unsigned int pte
, unsigned int ptr
, int scratch
,
1804 int t
= scratch
>= 0 ? scratch
: pte
;
1807 if (_PAGE_PRESENT_SHIFT
) {
1808 uasm_i_srl(p
, t
, cur
, _PAGE_PRESENT_SHIFT
);
1811 uasm_i_andi(p
, t
, cur
,
1812 (_PAGE_PRESENT
| _PAGE_WRITE
) >> _PAGE_PRESENT_SHIFT
);
1813 uasm_i_xori(p
, t
, t
,
1814 (_PAGE_PRESENT
| _PAGE_WRITE
) >> _PAGE_PRESENT_SHIFT
);
1815 uasm_il_bnez(p
, r
, t
, lid
);
1817 /* You lose the SMP race :-(*/
1818 iPTE_LW(p
, pte
, ptr
);
1823 /* Make PTE writable, update software status bits as well, then store
1827 build_make_write(u32
**p
, struct uasm_reloc
**r
, unsigned int pte
,
1828 unsigned int ptr
, unsigned int scratch
)
1830 unsigned int mode
= (_PAGE_ACCESSED
| _PAGE_MODIFIED
| _PAGE_VALID
1833 iPTE_SW(p
, r
, pte
, ptr
, mode
, scratch
);
1837 * Check if PTE can be modified, if not branch to LABEL. Regardless
1838 * restore PTE with value from PTR when done.
1841 build_pte_modifiable(u32
**p
, struct uasm_reloc
**r
,
1842 unsigned int pte
, unsigned int ptr
, int scratch
,
1845 if (use_bbit_insns()) {
1846 uasm_il_bbit0(p
, r
, pte
, ilog2(_PAGE_WRITE
), lid
);
1849 int t
= scratch
>= 0 ? scratch
: pte
;
1850 uasm_i_srl(p
, t
, pte
, _PAGE_WRITE_SHIFT
);
1851 uasm_i_andi(p
, t
, t
, 1);
1852 uasm_il_beqz(p
, r
, t
, lid
);
1854 /* You lose the SMP race :-(*/
1855 iPTE_LW(p
, pte
, ptr
);
1859 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1863 * R3000 style TLB load/store/modify handlers.
1867 * This places the pte into ENTRYLO0 and writes it with tlbwi.
1871 build_r3000_pte_reload_tlbwi(u32
**p
, unsigned int pte
, unsigned int tmp
)
1873 uasm_i_mtc0(p
, pte
, C0_ENTRYLO0
); /* cp0 delay */
1874 uasm_i_mfc0(p
, tmp
, C0_EPC
); /* cp0 delay */
1877 uasm_i_rfe(p
); /* branch delay */
1881 * This places the pte into ENTRYLO0 and writes it with tlbwi
1882 * or tlbwr as appropriate. This is because the index register
1883 * may have the probe fail bit set as a result of a trap on a
1884 * kseg2 access, i.e. without refill. Then it returns.
1887 build_r3000_tlb_reload_write(u32
**p
, struct uasm_label
**l
,
1888 struct uasm_reloc
**r
, unsigned int pte
,
1891 uasm_i_mfc0(p
, tmp
, C0_INDEX
);
1892 uasm_i_mtc0(p
, pte
, C0_ENTRYLO0
); /* cp0 delay */
1893 uasm_il_bltz(p
, r
, tmp
, label_r3000_write_probe_fail
); /* cp0 delay */
1894 uasm_i_mfc0(p
, tmp
, C0_EPC
); /* branch delay */
1895 uasm_i_tlbwi(p
); /* cp0 delay */
1897 uasm_i_rfe(p
); /* branch delay */
1898 uasm_l_r3000_write_probe_fail(l
, *p
);
1899 uasm_i_tlbwr(p
); /* cp0 delay */
1901 uasm_i_rfe(p
); /* branch delay */
1905 build_r3000_tlbchange_handler_head(u32
**p
, unsigned int pte
,
1908 long pgdc
= (long)pgd_current
;
1910 uasm_i_mfc0(p
, pte
, C0_BADVADDR
);
1911 uasm_i_lui(p
, ptr
, uasm_rel_hi(pgdc
)); /* cp0 delay */
1912 uasm_i_lw(p
, ptr
, uasm_rel_lo(pgdc
), ptr
);
1913 uasm_i_srl(p
, pte
, pte
, 22); /* load delay */
1914 uasm_i_sll(p
, pte
, pte
, 2);
1915 uasm_i_addu(p
, ptr
, ptr
, pte
);
1916 uasm_i_mfc0(p
, pte
, C0_CONTEXT
);
1917 uasm_i_lw(p
, ptr
, 0, ptr
); /* cp0 delay */
1918 uasm_i_andi(p
, pte
, pte
, 0xffc); /* load delay */
1919 uasm_i_addu(p
, ptr
, ptr
, pte
);
1920 uasm_i_lw(p
, pte
, 0, ptr
);
1921 uasm_i_tlbp(p
); /* load delay */
1924 static void build_r3000_tlb_load_handler(void)
1926 u32
*p
= handle_tlbl
;
1927 const int handle_tlbl_size
= handle_tlbl_end
- handle_tlbl
;
1928 struct uasm_label
*l
= labels
;
1929 struct uasm_reloc
*r
= relocs
;
1931 memset(handle_tlbl
, 0, handle_tlbl_size
* sizeof(handle_tlbl
[0]));
1932 memset(labels
, 0, sizeof(labels
));
1933 memset(relocs
, 0, sizeof(relocs
));
1935 build_r3000_tlbchange_handler_head(&p
, K0
, K1
);
1936 build_pte_present(&p
, &r
, K0
, K1
, -1, label_nopage_tlbl
);
1937 uasm_i_nop(&p
); /* load delay */
1938 build_make_valid(&p
, &r
, K0
, K1
, -1);
1939 build_r3000_tlb_reload_write(&p
, &l
, &r
, K0
, K1
);
1941 uasm_l_nopage_tlbl(&l
, p
);
1942 uasm_i_j(&p
, (unsigned long)tlb_do_page_fault_0
& 0x0fffffff);
1945 if (p
>= handle_tlbl_end
)
1946 panic("TLB load handler fastpath space exceeded");
1948 uasm_resolve_relocs(relocs
, labels
);
1949 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1950 (unsigned int)(p
- handle_tlbl
));
1952 dump_handler("r3000_tlb_load", handle_tlbl
, handle_tlbl_size
);
1955 static void build_r3000_tlb_store_handler(void)
1957 u32
*p
= handle_tlbs
;
1958 const int handle_tlbs_size
= handle_tlbs_end
- handle_tlbs
;
1959 struct uasm_label
*l
= labels
;
1960 struct uasm_reloc
*r
= relocs
;
1962 memset(handle_tlbs
, 0, handle_tlbs_size
* sizeof(handle_tlbs
[0]));
1963 memset(labels
, 0, sizeof(labels
));
1964 memset(relocs
, 0, sizeof(relocs
));
1966 build_r3000_tlbchange_handler_head(&p
, K0
, K1
);
1967 build_pte_writable(&p
, &r
, K0
, K1
, -1, label_nopage_tlbs
);
1968 uasm_i_nop(&p
); /* load delay */
1969 build_make_write(&p
, &r
, K0
, K1
, -1);
1970 build_r3000_tlb_reload_write(&p
, &l
, &r
, K0
, K1
);
1972 uasm_l_nopage_tlbs(&l
, p
);
1973 uasm_i_j(&p
, (unsigned long)tlb_do_page_fault_1
& 0x0fffffff);
1976 if (p
>= handle_tlbs_end
)
1977 panic("TLB store handler fastpath space exceeded");
1979 uasm_resolve_relocs(relocs
, labels
);
1980 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1981 (unsigned int)(p
- handle_tlbs
));
1983 dump_handler("r3000_tlb_store", handle_tlbs
, handle_tlbs_size
);
1986 static void build_r3000_tlb_modify_handler(void)
1988 u32
*p
= handle_tlbm
;
1989 const int handle_tlbm_size
= handle_tlbm_end
- handle_tlbm
;
1990 struct uasm_label
*l
= labels
;
1991 struct uasm_reloc
*r
= relocs
;
1993 memset(handle_tlbm
, 0, handle_tlbm_size
* sizeof(handle_tlbm
[0]));
1994 memset(labels
, 0, sizeof(labels
));
1995 memset(relocs
, 0, sizeof(relocs
));
1997 build_r3000_tlbchange_handler_head(&p
, K0
, K1
);
1998 build_pte_modifiable(&p
, &r
, K0
, K1
, -1, label_nopage_tlbm
);
1999 uasm_i_nop(&p
); /* load delay */
2000 build_make_write(&p
, &r
, K0
, K1
, -1);
2001 build_r3000_pte_reload_tlbwi(&p
, K0
, K1
);
2003 uasm_l_nopage_tlbm(&l
, p
);
2004 uasm_i_j(&p
, (unsigned long)tlb_do_page_fault_1
& 0x0fffffff);
2007 if (p
>= handle_tlbm_end
)
2008 panic("TLB modify handler fastpath space exceeded");
2010 uasm_resolve_relocs(relocs
, labels
);
2011 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
2012 (unsigned int)(p
- handle_tlbm
));
2014 dump_handler("r3000_tlb_modify", handle_tlbm
, handle_tlbm_size
);
2016 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
2019 * R4000 style TLB load/store/modify handlers.
2021 static struct work_registers
2022 build_r4000_tlbchange_handler_head(u32
**p
, struct uasm_label
**l
,
2023 struct uasm_reloc
**r
)
2025 struct work_registers wr
= build_get_work_registers(p
);
2028 build_get_pmde64(p
, l
, r
, wr
.r1
, wr
.r2
); /* get pmd in ptr */
2030 build_get_pgde32(p
, wr
.r1
, wr
.r2
); /* get pgd in ptr */
2033 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2035 * For huge tlb entries, pmd doesn't contain an address but
2036 * instead contains the tlb pte. Check the PAGE_HUGE bit and
2037 * see if we need to jump to huge tlb processing.
2039 build_is_huge_pte(p
, r
, wr
.r1
, wr
.r2
, label_tlb_huge_update
);
2042 UASM_i_MFC0(p
, wr
.r1
, C0_BADVADDR
);
2043 UASM_i_LW(p
, wr
.r2
, 0, wr
.r2
);
2044 UASM_i_SRL(p
, wr
.r1
, wr
.r1
, PAGE_SHIFT
+ PTE_ORDER
- PTE_T_LOG2
);
2045 uasm_i_andi(p
, wr
.r1
, wr
.r1
, (PTRS_PER_PTE
- 1) << PTE_T_LOG2
);
2046 UASM_i_ADDU(p
, wr
.r2
, wr
.r2
, wr
.r1
);
2049 uasm_l_smp_pgtable_change(l
, *p
);
2051 iPTE_LW(p
, wr
.r1
, wr
.r2
); /* get even pte */
2052 if (!m4kc_tlbp_war()) {
2053 build_tlb_probe_entry(p
);
2055 /* race condition happens, leaving */
2057 uasm_i_mfc0(p
, wr
.r3
, C0_INDEX
);
2058 uasm_il_bltz(p
, r
, wr
.r3
, label_leave
);
2066 build_r4000_tlbchange_handler_tail(u32
**p
, struct uasm_label
**l
,
2067 struct uasm_reloc
**r
, unsigned int tmp
,
2070 uasm_i_ori(p
, ptr
, ptr
, sizeof(pte_t
));
2071 uasm_i_xori(p
, ptr
, ptr
, sizeof(pte_t
));
2072 build_update_entries(p
, tmp
, ptr
);
2073 build_tlb_write_entry(p
, l
, r
, tlb_indexed
);
2074 uasm_l_leave(l
, *p
);
2075 build_restore_work_registers(p
);
2076 uasm_i_eret(p
); /* return from trap */
2079 build_get_pgd_vmalloc64(p
, l
, r
, tmp
, ptr
, not_refill
);
2083 static void build_r4000_tlb_load_handler(void)
2085 u32
*p
= (u32
*)msk_isa16_mode((ulong
)handle_tlbl
);
2086 const int handle_tlbl_size
= handle_tlbl_end
- handle_tlbl
;
2087 struct uasm_label
*l
= labels
;
2088 struct uasm_reloc
*r
= relocs
;
2089 struct work_registers wr
;
2091 memset(handle_tlbl
, 0, handle_tlbl_size
* sizeof(handle_tlbl
[0]));
2092 memset(labels
, 0, sizeof(labels
));
2093 memset(relocs
, 0, sizeof(relocs
));
2095 if (bcm1250_m3_war()) {
2096 unsigned int segbits
= 44;
2098 uasm_i_dmfc0(&p
, K0
, C0_BADVADDR
);
2099 uasm_i_dmfc0(&p
, K1
, C0_ENTRYHI
);
2100 uasm_i_xor(&p
, K0
, K0
, K1
);
2101 uasm_i_dsrl_safe(&p
, K1
, K0
, 62);
2102 uasm_i_dsrl_safe(&p
, K0
, K0
, 12 + 1);
2103 uasm_i_dsll_safe(&p
, K0
, K0
, 64 + 12 + 1 - segbits
);
2104 uasm_i_or(&p
, K0
, K0
, K1
);
2105 uasm_il_bnez(&p
, &r
, K0
, label_leave
);
2106 /* No need for uasm_i_nop */
2109 wr
= build_r4000_tlbchange_handler_head(&p
, &l
, &r
);
2110 build_pte_present(&p
, &r
, wr
.r1
, wr
.r2
, wr
.r3
, label_nopage_tlbl
);
2111 if (m4kc_tlbp_war())
2112 build_tlb_probe_entry(&p
);
2114 if (cpu_has_rixi
&& !cpu_has_rixiex
) {
2116 * If the page is not _PAGE_VALID, RI or XI could not
2117 * have triggered it. Skip the expensive test..
2119 if (use_bbit_insns()) {
2120 uasm_il_bbit0(&p
, &r
, wr
.r1
, ilog2(_PAGE_VALID
),
2121 label_tlbl_goaround1
);
2123 uasm_i_andi(&p
, wr
.r3
, wr
.r1
, _PAGE_VALID
);
2124 uasm_il_beqz(&p
, &r
, wr
.r3
, label_tlbl_goaround1
);
2130 switch (current_cpu_type()) {
2132 if (cpu_has_mips_r2_exec_hazard
) {
2135 case CPU_CAVIUM_OCTEON
:
2136 case CPU_CAVIUM_OCTEON_PLUS
:
2137 case CPU_CAVIUM_OCTEON2
:
2142 /* Examine entrylo 0 or 1 based on ptr. */
2143 if (use_bbit_insns()) {
2144 uasm_i_bbit0(&p
, wr
.r2
, ilog2(sizeof(pte_t
)), 8);
2146 uasm_i_andi(&p
, wr
.r3
, wr
.r2
, sizeof(pte_t
));
2147 uasm_i_beqz(&p
, wr
.r3
, 8);
2149 /* load it in the delay slot*/
2150 UASM_i_MFC0(&p
, wr
.r3
, C0_ENTRYLO0
);
2151 /* load it if ptr is odd */
2152 UASM_i_MFC0(&p
, wr
.r3
, C0_ENTRYLO1
);
2154 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
2155 * XI must have triggered it.
2157 if (use_bbit_insns()) {
2158 uasm_il_bbit1(&p
, &r
, wr
.r3
, 1, label_nopage_tlbl
);
2160 uasm_l_tlbl_goaround1(&l
, p
);
2162 uasm_i_andi(&p
, wr
.r3
, wr
.r3
, 2);
2163 uasm_il_bnez(&p
, &r
, wr
.r3
, label_nopage_tlbl
);
2166 uasm_l_tlbl_goaround1(&l
, p
);
2168 build_make_valid(&p
, &r
, wr
.r1
, wr
.r2
, wr
.r3
);
2169 build_r4000_tlbchange_handler_tail(&p
, &l
, &r
, wr
.r1
, wr
.r2
);
2171 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2173 * This is the entry point when build_r4000_tlbchange_handler_head
2174 * spots a huge page.
2176 uasm_l_tlb_huge_update(&l
, p
);
2177 iPTE_LW(&p
, wr
.r1
, wr
.r2
);
2178 build_pte_present(&p
, &r
, wr
.r1
, wr
.r2
, wr
.r3
, label_nopage_tlbl
);
2179 build_tlb_probe_entry(&p
);
2181 if (cpu_has_rixi
&& !cpu_has_rixiex
) {
2183 * If the page is not _PAGE_VALID, RI or XI could not
2184 * have triggered it. Skip the expensive test..
2186 if (use_bbit_insns()) {
2187 uasm_il_bbit0(&p
, &r
, wr
.r1
, ilog2(_PAGE_VALID
),
2188 label_tlbl_goaround2
);
2190 uasm_i_andi(&p
, wr
.r3
, wr
.r1
, _PAGE_VALID
);
2191 uasm_il_beqz(&p
, &r
, wr
.r3
, label_tlbl_goaround2
);
2197 switch (current_cpu_type()) {
2199 if (cpu_has_mips_r2_exec_hazard
) {
2202 case CPU_CAVIUM_OCTEON
:
2203 case CPU_CAVIUM_OCTEON_PLUS
:
2204 case CPU_CAVIUM_OCTEON2
:
2209 /* Examine entrylo 0 or 1 based on ptr. */
2210 if (use_bbit_insns()) {
2211 uasm_i_bbit0(&p
, wr
.r2
, ilog2(sizeof(pte_t
)), 8);
2213 uasm_i_andi(&p
, wr
.r3
, wr
.r2
, sizeof(pte_t
));
2214 uasm_i_beqz(&p
, wr
.r3
, 8);
2216 /* load it in the delay slot*/
2217 UASM_i_MFC0(&p
, wr
.r3
, C0_ENTRYLO0
);
2218 /* load it if ptr is odd */
2219 UASM_i_MFC0(&p
, wr
.r3
, C0_ENTRYLO1
);
2221 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
2222 * XI must have triggered it.
2224 if (use_bbit_insns()) {
2225 uasm_il_bbit0(&p
, &r
, wr
.r3
, 1, label_tlbl_goaround2
);
2227 uasm_i_andi(&p
, wr
.r3
, wr
.r3
, 2);
2228 uasm_il_beqz(&p
, &r
, wr
.r3
, label_tlbl_goaround2
);
2230 if (PM_DEFAULT_MASK
== 0)
2233 * We clobbered C0_PAGEMASK, restore it. On the other branch
2234 * it is restored in build_huge_tlb_write_entry.
2236 build_restore_pagemask(&p
, &r
, wr
.r3
, label_nopage_tlbl
, 0);
2238 uasm_l_tlbl_goaround2(&l
, p
);
2240 uasm_i_ori(&p
, wr
.r1
, wr
.r1
, (_PAGE_ACCESSED
| _PAGE_VALID
));
2241 build_huge_handler_tail(&p
, &r
, &l
, wr
.r1
, wr
.r2
, 1);
2244 uasm_l_nopage_tlbl(&l
, p
);
2245 build_restore_work_registers(&p
);
2246 #ifdef CONFIG_CPU_MICROMIPS
2247 if ((unsigned long)tlb_do_page_fault_0
& 1) {
2248 uasm_i_lui(&p
, K0
, uasm_rel_hi((long)tlb_do_page_fault_0
));
2249 uasm_i_addiu(&p
, K0
, K0
, uasm_rel_lo((long)tlb_do_page_fault_0
));
2253 uasm_i_j(&p
, (unsigned long)tlb_do_page_fault_0
& 0x0fffffff);
2256 if (p
>= handle_tlbl_end
)
2257 panic("TLB load handler fastpath space exceeded");
2259 uasm_resolve_relocs(relocs
, labels
);
2260 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
2261 (unsigned int)(p
- handle_tlbl
));
2263 dump_handler("r4000_tlb_load", handle_tlbl
, handle_tlbl_size
);
2266 static void build_r4000_tlb_store_handler(void)
2268 u32
*p
= (u32
*)msk_isa16_mode((ulong
)handle_tlbs
);
2269 const int handle_tlbs_size
= handle_tlbs_end
- handle_tlbs
;
2270 struct uasm_label
*l
= labels
;
2271 struct uasm_reloc
*r
= relocs
;
2272 struct work_registers wr
;
2274 memset(handle_tlbs
, 0, handle_tlbs_size
* sizeof(handle_tlbs
[0]));
2275 memset(labels
, 0, sizeof(labels
));
2276 memset(relocs
, 0, sizeof(relocs
));
2278 wr
= build_r4000_tlbchange_handler_head(&p
, &l
, &r
);
2279 build_pte_writable(&p
, &r
, wr
.r1
, wr
.r2
, wr
.r3
, label_nopage_tlbs
);
2280 if (m4kc_tlbp_war())
2281 build_tlb_probe_entry(&p
);
2282 build_make_write(&p
, &r
, wr
.r1
, wr
.r2
, wr
.r3
);
2283 build_r4000_tlbchange_handler_tail(&p
, &l
, &r
, wr
.r1
, wr
.r2
);
2285 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2287 * This is the entry point when
2288 * build_r4000_tlbchange_handler_head spots a huge page.
2290 uasm_l_tlb_huge_update(&l
, p
);
2291 iPTE_LW(&p
, wr
.r1
, wr
.r2
);
2292 build_pte_writable(&p
, &r
, wr
.r1
, wr
.r2
, wr
.r3
, label_nopage_tlbs
);
2293 build_tlb_probe_entry(&p
);
2294 uasm_i_ori(&p
, wr
.r1
, wr
.r1
,
2295 _PAGE_ACCESSED
| _PAGE_MODIFIED
| _PAGE_VALID
| _PAGE_DIRTY
);
2296 build_huge_handler_tail(&p
, &r
, &l
, wr
.r1
, wr
.r2
, 1);
2299 uasm_l_nopage_tlbs(&l
, p
);
2300 build_restore_work_registers(&p
);
2301 #ifdef CONFIG_CPU_MICROMIPS
2302 if ((unsigned long)tlb_do_page_fault_1
& 1) {
2303 uasm_i_lui(&p
, K0
, uasm_rel_hi((long)tlb_do_page_fault_1
));
2304 uasm_i_addiu(&p
, K0
, K0
, uasm_rel_lo((long)tlb_do_page_fault_1
));
2308 uasm_i_j(&p
, (unsigned long)tlb_do_page_fault_1
& 0x0fffffff);
2311 if (p
>= handle_tlbs_end
)
2312 panic("TLB store handler fastpath space exceeded");
2314 uasm_resolve_relocs(relocs
, labels
);
2315 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
2316 (unsigned int)(p
- handle_tlbs
));
2318 dump_handler("r4000_tlb_store", handle_tlbs
, handle_tlbs_size
);
2321 static void build_r4000_tlb_modify_handler(void)
2323 u32
*p
= (u32
*)msk_isa16_mode((ulong
)handle_tlbm
);
2324 const int handle_tlbm_size
= handle_tlbm_end
- handle_tlbm
;
2325 struct uasm_label
*l
= labels
;
2326 struct uasm_reloc
*r
= relocs
;
2327 struct work_registers wr
;
2329 memset(handle_tlbm
, 0, handle_tlbm_size
* sizeof(handle_tlbm
[0]));
2330 memset(labels
, 0, sizeof(labels
));
2331 memset(relocs
, 0, sizeof(relocs
));
2333 wr
= build_r4000_tlbchange_handler_head(&p
, &l
, &r
);
2334 build_pte_modifiable(&p
, &r
, wr
.r1
, wr
.r2
, wr
.r3
, label_nopage_tlbm
);
2335 if (m4kc_tlbp_war())
2336 build_tlb_probe_entry(&p
);
2337 /* Present and writable bits set, set accessed and dirty bits. */
2338 build_make_write(&p
, &r
, wr
.r1
, wr
.r2
, wr
.r3
);
2339 build_r4000_tlbchange_handler_tail(&p
, &l
, &r
, wr
.r1
, wr
.r2
);
2341 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2343 * This is the entry point when
2344 * build_r4000_tlbchange_handler_head spots a huge page.
2346 uasm_l_tlb_huge_update(&l
, p
);
2347 iPTE_LW(&p
, wr
.r1
, wr
.r2
);
2348 build_pte_modifiable(&p
, &r
, wr
.r1
, wr
.r2
, wr
.r3
, label_nopage_tlbm
);
2349 build_tlb_probe_entry(&p
);
2350 uasm_i_ori(&p
, wr
.r1
, wr
.r1
,
2351 _PAGE_ACCESSED
| _PAGE_MODIFIED
| _PAGE_VALID
| _PAGE_DIRTY
);
2352 build_huge_handler_tail(&p
, &r
, &l
, wr
.r1
, wr
.r2
, 0);
2355 uasm_l_nopage_tlbm(&l
, p
);
2356 build_restore_work_registers(&p
);
2357 #ifdef CONFIG_CPU_MICROMIPS
2358 if ((unsigned long)tlb_do_page_fault_1
& 1) {
2359 uasm_i_lui(&p
, K0
, uasm_rel_hi((long)tlb_do_page_fault_1
));
2360 uasm_i_addiu(&p
, K0
, K0
, uasm_rel_lo((long)tlb_do_page_fault_1
));
2364 uasm_i_j(&p
, (unsigned long)tlb_do_page_fault_1
& 0x0fffffff);
2367 if (p
>= handle_tlbm_end
)
2368 panic("TLB modify handler fastpath space exceeded");
2370 uasm_resolve_relocs(relocs
, labels
);
2371 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
2372 (unsigned int)(p
- handle_tlbm
));
2374 dump_handler("r4000_tlb_modify", handle_tlbm
, handle_tlbm_size
);
2377 static void flush_tlb_handlers(void)
2379 local_flush_icache_range((unsigned long)handle_tlbl
,
2380 (unsigned long)handle_tlbl_end
);
2381 local_flush_icache_range((unsigned long)handle_tlbs
,
2382 (unsigned long)handle_tlbs_end
);
2383 local_flush_icache_range((unsigned long)handle_tlbm
,
2384 (unsigned long)handle_tlbm_end
);
2385 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd
,
2386 (unsigned long)tlbmiss_handler_setup_pgd_end
);
2389 static void print_htw_config(void)
2391 unsigned long config
;
2393 const int field
= 2 * sizeof(unsigned long);
2395 config
= read_c0_pwfield();
2396 pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n",
2398 (config
& MIPS_PWFIELD_GDI_MASK
) >> MIPS_PWFIELD_GDI_SHIFT
,
2399 (config
& MIPS_PWFIELD_UDI_MASK
) >> MIPS_PWFIELD_UDI_SHIFT
,
2400 (config
& MIPS_PWFIELD_MDI_MASK
) >> MIPS_PWFIELD_MDI_SHIFT
,
2401 (config
& MIPS_PWFIELD_PTI_MASK
) >> MIPS_PWFIELD_PTI_SHIFT
,
2402 (config
& MIPS_PWFIELD_PTEI_MASK
) >> MIPS_PWFIELD_PTEI_SHIFT
);
2404 config
= read_c0_pwsize();
2405 pr_debug("PWSize (0x%0*lx): PS: 0x%lx GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n",
2407 (config
& MIPS_PWSIZE_PS_MASK
) >> MIPS_PWSIZE_PS_SHIFT
,
2408 (config
& MIPS_PWSIZE_GDW_MASK
) >> MIPS_PWSIZE_GDW_SHIFT
,
2409 (config
& MIPS_PWSIZE_UDW_MASK
) >> MIPS_PWSIZE_UDW_SHIFT
,
2410 (config
& MIPS_PWSIZE_MDW_MASK
) >> MIPS_PWSIZE_MDW_SHIFT
,
2411 (config
& MIPS_PWSIZE_PTW_MASK
) >> MIPS_PWSIZE_PTW_SHIFT
,
2412 (config
& MIPS_PWSIZE_PTEW_MASK
) >> MIPS_PWSIZE_PTEW_SHIFT
);
2414 pwctl
= read_c0_pwctl();
2415 pr_debug("PWCtl (0x%x): PWEn: 0x%x XK: 0x%x XS: 0x%x XU: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n",
2417 (pwctl
& MIPS_PWCTL_PWEN_MASK
) >> MIPS_PWCTL_PWEN_SHIFT
,
2418 (pwctl
& MIPS_PWCTL_XK_MASK
) >> MIPS_PWCTL_XK_SHIFT
,
2419 (pwctl
& MIPS_PWCTL_XS_MASK
) >> MIPS_PWCTL_XS_SHIFT
,
2420 (pwctl
& MIPS_PWCTL_XU_MASK
) >> MIPS_PWCTL_XU_SHIFT
,
2421 (pwctl
& MIPS_PWCTL_DPH_MASK
) >> MIPS_PWCTL_DPH_SHIFT
,
2422 (pwctl
& MIPS_PWCTL_HUGEPG_MASK
) >> MIPS_PWCTL_HUGEPG_SHIFT
,
2423 (pwctl
& MIPS_PWCTL_PSN_MASK
) >> MIPS_PWCTL_PSN_SHIFT
);
2426 static void config_htw_params(void)
2428 unsigned long pwfield
, pwsize
, ptei
;
2429 unsigned int config
;
2432 * We are using 2-level page tables, so we only need to
2433 * setup GDW and PTW appropriately. UDW and MDW will remain 0.
2434 * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to
2435 * write values less than 0xc in these fields because the entire
2436 * write will be dropped. As a result of which, we must preserve
2437 * the original reset values and overwrite only what we really want.
2440 pwfield
= read_c0_pwfield();
2441 /* re-initialize the GDI field */
2442 pwfield
&= ~MIPS_PWFIELD_GDI_MASK
;
2443 pwfield
|= PGDIR_SHIFT
<< MIPS_PWFIELD_GDI_SHIFT
;
2444 /* re-initialize the PTI field including the even/odd bit */
2445 pwfield
&= ~MIPS_PWFIELD_PTI_MASK
;
2446 pwfield
|= PAGE_SHIFT
<< MIPS_PWFIELD_PTI_SHIFT
;
2447 if (CONFIG_PGTABLE_LEVELS
>= 3) {
2448 pwfield
&= ~MIPS_PWFIELD_MDI_MASK
;
2449 pwfield
|= PMD_SHIFT
<< MIPS_PWFIELD_MDI_SHIFT
;
2451 /* Set the PTEI right shift */
2452 ptei
= _PAGE_GLOBAL_SHIFT
<< MIPS_PWFIELD_PTEI_SHIFT
;
2454 write_c0_pwfield(pwfield
);
2455 /* Check whether the PTEI value is supported */
2456 back_to_back_c0_hazard();
2457 pwfield
= read_c0_pwfield();
2458 if (((pwfield
& MIPS_PWFIELD_PTEI_MASK
) << MIPS_PWFIELD_PTEI_SHIFT
)
2460 pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled",
2463 * Drop option to avoid HTW being enabled via another path
2466 current_cpu_data
.options
&= ~MIPS_CPU_HTW
;
2470 pwsize
= ilog2(PTRS_PER_PGD
) << MIPS_PWSIZE_GDW_SHIFT
;
2471 pwsize
|= ilog2(PTRS_PER_PTE
) << MIPS_PWSIZE_PTW_SHIFT
;
2472 if (CONFIG_PGTABLE_LEVELS
>= 3)
2473 pwsize
|= ilog2(PTRS_PER_PMD
) << MIPS_PWSIZE_MDW_SHIFT
;
2475 /* Set pointer size to size of directory pointers */
2476 if (IS_ENABLED(CONFIG_64BIT
))
2477 pwsize
|= MIPS_PWSIZE_PS_MASK
;
2478 /* PTEs may be multiple pointers long (e.g. with XPA) */
2479 pwsize
|= ((PTE_T_LOG2
- PGD_T_LOG2
) << MIPS_PWSIZE_PTEW_SHIFT
)
2480 & MIPS_PWSIZE_PTEW_MASK
;
2482 write_c0_pwsize(pwsize
);
2484 /* Make sure everything is set before we enable the HTW */
2485 back_to_back_c0_hazard();
2488 * Enable HTW (and only for XUSeg on 64-bit), and disable the rest of
2491 config
= 1 << MIPS_PWCTL_PWEN_SHIFT
;
2492 if (IS_ENABLED(CONFIG_64BIT
))
2493 config
|= MIPS_PWCTL_XU_MASK
;
2494 write_c0_pwctl(config
);
2495 pr_info("Hardware Page Table Walker enabled\n");
2500 static void config_xpa_params(void)
2503 unsigned int pagegrain
;
2505 if (mips_xpa_disabled
) {
2506 pr_info("Extended Physical Addressing (XPA) disabled\n");
2510 pagegrain
= read_c0_pagegrain();
2511 write_c0_pagegrain(pagegrain
| PG_ELPA
);
2512 back_to_back_c0_hazard();
2513 pagegrain
= read_c0_pagegrain();
2515 if (pagegrain
& PG_ELPA
)
2516 pr_info("Extended Physical Addressing (XPA) enabled\n");
2518 panic("Extended Physical Addressing (XPA) disabled");
2522 static void check_pabits(void)
2524 unsigned long entry
;
2525 unsigned pabits
, fillbits
;
2527 if (!cpu_has_rixi
|| !_PAGE_NO_EXEC
) {
2529 * We'll only be making use of the fact that we can rotate bits
2530 * into the fill if the CPU supports RIXI, so don't bother
2531 * probing this for CPUs which don't.
2536 write_c0_entrylo0(~0ul);
2537 back_to_back_c0_hazard();
2538 entry
= read_c0_entrylo0();
2540 /* clear all non-PFN bits */
2541 entry
&= ~((1 << MIPS_ENTRYLO_PFN_SHIFT
) - 1);
2542 entry
&= ~(MIPS_ENTRYLO_RI
| MIPS_ENTRYLO_XI
);
2544 /* find a lower bound on PABITS, and upper bound on fill bits */
2545 pabits
= fls_long(entry
) + 6;
2546 fillbits
= max_t(int, (int)BITS_PER_LONG
- pabits
, 0);
2548 /* minus the RI & XI bits */
2549 fillbits
-= min_t(unsigned, fillbits
, 2);
2551 if (fillbits
>= ilog2(_PAGE_NO_EXEC
))
2552 fill_includes_sw_bits
= true;
2554 pr_debug("Entry* registers contain %u fill bits\n", fillbits
);
2557 void build_tlb_refill_handler(void)
2560 * The refill handler is generated per-CPU, multi-node systems
2561 * may have local storage for it. The other handlers are only
2564 static int run_once
= 0;
2566 if (IS_ENABLED(CONFIG_XPA
) && !cpu_has_rixi
)
2567 panic("Kernels supporting XPA currently require CPUs with RIXI");
2569 output_pgtable_bits_defines();
2573 check_for_high_segbits
= current_cpu_data
.vmbits
> (PGDIR_SHIFT
+ PGD_ORDER
+ PAGE_SHIFT
- 3);
2576 switch (current_cpu_type()) {
2584 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
2585 if (cpu_has_local_ebase
)
2586 build_r3000_tlb_refill_handler();
2588 if (!cpu_has_local_ebase
)
2589 build_r3000_tlb_refill_handler();
2591 build_r3000_tlb_load_handler();
2592 build_r3000_tlb_store_handler();
2593 build_r3000_tlb_modify_handler();
2594 flush_tlb_handlers();
2598 panic("No R3000 TLB refill handler");
2604 panic("No R6000 TLB refill handler yet");
2608 panic("No R8000 TLB refill handler yet");
2616 scratch_reg
= allocate_kscratch();
2618 build_r4000_tlb_load_handler();
2619 build_r4000_tlb_store_handler();
2620 build_r4000_tlb_modify_handler();
2622 build_loongson3_tlb_refill_handler();
2623 else if (!cpu_has_local_ebase
)
2624 build_r4000_tlb_refill_handler();
2625 flush_tlb_handlers();
2628 if (cpu_has_local_ebase
)
2629 build_r4000_tlb_refill_handler();
2631 config_xpa_params();
2633 config_htw_params();