arch/mips/momentum/jaguar_atx/setup.c

   1 /*
   2  * BRIEF MODULE DESCRIPTION
   3  * Momentum Computer Jaguar-ATX board dependent boot routines
   4  *
   5  * Copyright (C) 1996, 1997, 2001, 04, 06  Ralf Baechle (ralf@linux-mips.org)
   6  * Copyright (C) 2000 RidgeRun, Inc.
   7  * Copyright (C) 2001 Red Hat, Inc.
   8  * Copyright (C) 2002 Momentum Computer
   9  *
  10  * Author: Matthew Dharm, Momentum Computer
  11  *   mdharm@momenco.com
  12  *
  13  * Louis Hamilton, Red Hat, Inc.
  14  *   hamilton@redhat.com  [MIPS64 modifications]
  15  *
  16  * Author: RidgeRun, Inc.
  17  *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
  18  *
  19  * Copyright 2001 MontaVista Software Inc.
  20  * Author: jsun@mvista.com or jsun@junsun.net
  21  *
  22  *  This program is free software; you can redistribute  it and/or modify it
  23  *  under  the terms of  the GNU General  Public License as published by the
  24  *  Free Software Foundation;  either version 2 of the  License, or (at your
  25  *  option) any later version.
  26  *
  27  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  28  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  29  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  30  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  31  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  32  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  33  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  34  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  35  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  36  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  *
  38  *  You should have received a copy of the  GNU General Public License along
  39  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  40  *  675 Mass Ave, Cambridge, MA 02139, USA.
  41  */
  42 #include <linux/config.h>
  43 #include <linux/bcd.h>
  44 #include <linux/init.h>
  45 #include <linux/kernel.h>
  46 #include <linux/types.h>
  47 #include <linux/mm.h>
  48 #include <linux/bootmem.h>
  49 #include <linux/module.h>
  50 #include <linux/pci.h>
  51 #include <linux/swap.h>
  52 #include <linux/ioport.h>
  53 #include <linux/pm.h>
  54 #include <linux/sched.h>
  55 #include <linux/interrupt.h>
  56 #include <linux/timex.h>
  57 #include <linux/vmalloc.h>
  58 #include <linux/mv643xx.h>
  59
  60 #include <asm/time.h>
  61 #include <asm/bootinfo.h>
  62 #include <asm/page.h>
  63 #include <asm/io.h>
  64 #include <asm/irq.h>
  65 #include <asm/processor.h>
  66 #include <asm/ptrace.h>
  67 #include <asm/reboot.h>
  68 #include <asm/tlbflush.h>
  69
  70 #include "jaguar_atx_fpga.h"
  71
  72 extern unsigned long mv64340_sram_base;
  73 unsigned long cpu_clock;
  74
  75 /* These functions are used for rebooting or halting the machine*/
  76 extern void momenco_jaguar_restart(char *command);
  77 extern void momenco_jaguar_halt(void);
  78 extern void momenco_jaguar_power_off(void);
  79
  80 void momenco_time_init(void);
  81
  82 static char reset_reason;
  83
  84 static inline unsigned long ENTRYLO(unsigned long paddr)
  85 {
  86         return ((paddr & PAGE_MASK) |
  87                (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
  88                 _CACHE_UNCACHED)) >> 6;
  89 }
  90
  91 void __init bus_error_init(void) { /* nothing */ }
  92
  93 /*
  94  * Load a few TLB entries for the MV64340 and perhiperals. The MV64340 is going
  95  * to be hit on every IRQ anyway - there's absolutely no point in letting it be
  96  * a random TLB entry, as it'll just cause needless churning of the TLB. And we
  97  * use the other half for the serial port, which is just a PITA otherwise :)
  98  *
  99  *      Device                  Physical        Virtual
 100  *      MV64340 Internal Regs   0xf4000000      0xf4000000
 101  *      Ocelot-C[S] PLD (CS0)   0xfc000000      0xfc000000
 102  *      NVRAM (CS1)             0xfc800000      0xfc800000
 103  *      UARTs (CS2)             0xfd000000      0xfd000000
 104  *      Internal SRAM           0xfe000000      0xfe000000
 105  *      M-Systems DOC (CS3)     0xff000000      0xff000000
 106  */
 107
 108 static __init void wire_stupidity_into_tlb(void)
 109 {
 110 #ifdef CONFIG_32BIT
 111         write_c0_wired(0);
 112         local_flush_tlb_all();
 113
 114         /* marvell and extra space */
 115         add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000),
 116                         0xf4000000UL, PM_64K);
 117         /* fpga, rtc, and uart */
 118         add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000),
 119                         0xfc000000UL, PM_16M);
 120 //      /* m-sys and internal SRAM */
 121 //      add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000),
 122 //                      0xfe000000UL, PM_16M);
 123
 124         marvell_base = 0xf4000000;
 125         //mv64340_sram_base = 0xfe000000;       /* Currently unused */
 126 #endif
 127 }
 128
 129 unsigned long marvell_base      = 0xf4000000L;
 130 unsigned long ja_fpga_base      = JAGUAR_ATX_CS0_ADDR;
 131 unsigned long uart_base         = 0xfd000000L;
 132 static unsigned char *rtc_base  = (unsigned char*) 0xfc800000L;
 133
 134 EXPORT_SYMBOL(marvell_base);
 135
 136 static __init int per_cpu_mappings(void)
 137 {
 138         marvell_base    = (unsigned long) ioremap(0xf4000000, 0x10000);
 139         ja_fpga_base    = (unsigned long) ioremap(JAGUAR_ATX_CS0_ADDR,  0x1000);
 140         uart_base       = (unsigned long) ioremap(0xfd000000UL, 0x1000);
 141         rtc_base        = ioremap(0xfc000000UL, 0x8000);
 142         // ioremap(0xfe000000,  32 << 20);
 143         write_c0_wired(0);
 144         local_flush_tlb_all();
 145         ja_setup_console();
 146
 147         return 0;
 148 }
 149 arch_initcall(per_cpu_mappings);
 150
 151 unsigned long m48t37y_get_time(void)
 152 {
 153         unsigned int year, month, day, hour, min, sec;
 154         unsigned long flags;
 155
 156         spin_lock_irqsave(&rtc_lock, flags);
 157         /* stop the update */
 158         rtc_base[0x7ff8] = 0x40;
 159
 160         year = BCD2BIN(rtc_base[0x7fff]);
 161         year += BCD2BIN(rtc_base[0x7ff1]) * 100;
 162
 163         month = BCD2BIN(rtc_base[0x7ffe]);
 164
 165         day = BCD2BIN(rtc_base[0x7ffd]);
 166
 167         hour = BCD2BIN(rtc_base[0x7ffb]);
 168         min = BCD2BIN(rtc_base[0x7ffa]);
 169         sec = BCD2BIN(rtc_base[0x7ff9]);
 170
 171         /* start the update */
 172         rtc_base[0x7ff8] = 0x00;
 173         spin_unlock_irqrestore(&rtc_lock, flags);
 174
 175         return mktime(year, month, day, hour, min, sec);
 176 }
 177
 178 int m48t37y_set_time(unsigned long sec)
 179 {
 180         struct rtc_time tm;
 181         unsigned long flags;
 182
 183         /* convert to a more useful format -- note months count from 0 */
 184         to_tm(sec, &tm);
 185         tm.tm_mon += 1;
 186
 187         spin_lock_irqsave(&rtc_lock, flags);
 188         /* enable writing */
 189         rtc_base[0x7ff8] = 0x80;
 190
 191         /* year */
 192         rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
 193         rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
 194
 195         /* month */
 196         rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
 197
 198         /* day */
 199         rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
 200
 201         /* hour/min/sec */
 202         rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
 203         rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
 204         rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
 205
 206         /* day of week -- not really used, but let's keep it up-to-date */
 207         rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
 208
 209         /* disable writing */
 210         rtc_base[0x7ff8] = 0x00;
 211         spin_unlock_irqrestore(&rtc_lock, flags);
 212
 213         return 0;
 214 }
 215
 216 void momenco_timer_setup(struct irqaction *irq)
 217 {
 218         setup_irq(8, irq);
 219 }
 220
 221 /*
 222  * Ugly but the least of all evils.  TLB initialization did flush the TLB so
 223  * We need to setup mappings again before we can touch the RTC.
 224  */
 225 void momenco_time_init(void)
 226 {
 227         wire_stupidity_into_tlb();
 228
 229         mips_hpt_frequency = cpu_clock / 2;
 230         board_timer_setup = momenco_timer_setup;
 231
 232         rtc_mips_get_time = m48t37y_get_time;
 233         rtc_mips_set_time = m48t37y_set_time;
 234 }
 235
 236 static struct resource mv_pci_io_mem0_resource = {
 237         .name   = "MV64340 PCI0 IO MEM",
 238         .flags  = IORESOURCE_IO
 239 };
 240
 241 static struct resource mv_pci_mem0_resource = {
 242         .name   = "MV64340 PCI0 MEM",
 243         .flags  = IORESOURCE_MEM
 244 };
 245
 246 static struct mv_pci_controller mv_bus0_controller = {
 247         .pcic = {
 248                 .pci_ops        = &mv_pci_ops,
 249                 .mem_resource   = &mv_pci_mem0_resource,
 250                 .io_resource    = &mv_pci_io_mem0_resource,
 251         },
 252         .config_addr    = MV64340_PCI_0_CONFIG_ADDR,
 253         .config_vreg    = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG,
 254 };
 255
 256 static uint32_t mv_io_base, mv_io_size;
 257
 258 static void ja_pci0_init(void)
 259 {
 260         uint32_t mem0_base, mem0_size;
 261         uint32_t io_base, io_size;
 262
 263         io_base = MV_READ(MV64340_PCI_0_IO_BASE_ADDR) << 16;
 264         io_size = (MV_READ(MV64340_PCI_0_IO_SIZE) + 1) << 16;
 265         mem0_base = MV_READ(MV64340_PCI_0_MEMORY0_BASE_ADDR) << 16;
 266         mem0_size = (MV_READ(MV64340_PCI_0_MEMORY0_SIZE) + 1) << 16;
 267
 268         mv_pci_io_mem0_resource.start           = 0;
 269         mv_pci_io_mem0_resource.end             = io_size - 1;
 270         mv_pci_mem0_resource.start              = mem0_base;
 271         mv_pci_mem0_resource.end                = mem0_base + mem0_size - 1;
 272         mv_bus0_controller.pcic.mem_offset      = mem0_base;
 273         mv_bus0_controller.pcic.io_offset       = 0;
 274
 275         ioport_resource.end             = io_size - 1;
 276
 277         register_pci_controller(&mv_bus0_controller.pcic);
 278
 279         mv_io_base = io_base;
 280         mv_io_size = io_size;
 281 }
 282
 283 static struct resource mv_pci_io_mem1_resource = {
 284         .name   = "MV64340 PCI1 IO MEM",
 285         .flags  = IORESOURCE_IO
 286 };
 287
 288 static struct resource mv_pci_mem1_resource = {
 289         .name   = "MV64340 PCI1 MEM",
 290         .flags  = IORESOURCE_MEM
 291 };
 292
 293 static struct mv_pci_controller mv_bus1_controller = {
 294         .pcic = {
 295                 .pci_ops        = &mv_pci_ops,
 296                 .mem_resource   = &mv_pci_mem1_resource,
 297                 .io_resource    = &mv_pci_io_mem1_resource,
 298         },
 299         .config_addr    = MV64340_PCI_1_CONFIG_ADDR,
 300         .config_vreg    = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG,
 301 };
 302
 303 static __init void ja_pci1_init(void)
 304 {
 305         uint32_t mem0_base, mem0_size;
 306         uint32_t io_base, io_size;
 307
 308         io_base = MV_READ(MV64340_PCI_1_IO_BASE_ADDR) << 16;
 309         io_size = (MV_READ(MV64340_PCI_1_IO_SIZE) + 1) << 16;
 310         mem0_base = MV_READ(MV64340_PCI_1_MEMORY0_BASE_ADDR) << 16;
 311         mem0_size = (MV_READ(MV64340_PCI_1_MEMORY0_SIZE) + 1) << 16;
 312
 313         /*
 314          * Here we assume the I/O window of second bus to be contiguous with
 315          * the first.  A gap is no problem but would waste address space for
 316          * remapping the port space.
 317          */
 318         mv_pci_io_mem1_resource.start           = mv_io_size;
 319         mv_pci_io_mem1_resource.end             = mv_io_size + io_size - 1;
 320         mv_pci_mem1_resource.start              = mem0_base;
 321         mv_pci_mem1_resource.end                = mem0_base + mem0_size - 1;
 322         mv_bus1_controller.pcic.mem_offset      = mem0_base;
 323         mv_bus1_controller.pcic.io_offset       = 0;
 324
 325         ioport_resource.end             = io_base + io_size -mv_io_base - 1;
 326
 327         register_pci_controller(&mv_bus1_controller.pcic);
 328
 329         mv_io_size = io_base + io_size - mv_io_base;
 330 }
 331
 332 static __init int __init ja_pci_init(void)
 333 {
 334         unsigned long io_v_base;
 335         uint32_t enable;
 336
 337         enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE);
 338
 339         /*
 340          * We require at least one enabled I/O or PCI memory window or we
 341          * will ignore this PCI bus.  We ignore PCI windows 1, 2 and 3.
 342          */
 343         if (enable & (0x01 <<  9) || enable & (0x01 << 10))
 344                 ja_pci0_init();
 345
 346         if (enable & (0x01 << 14) || enable & (0x01 << 15))
 347                 ja_pci1_init();
 348
 349         if (mv_io_size) {
 350                 io_v_base = (unsigned long) ioremap(mv_io_base, mv_io_size);
 351                 if (!io_v_base)
 352                         panic("Could not ioremap I/O port range");
 353
 354                 set_io_port_base(io_v_base);
 355         }
 356
 357         return 0;
 358 }
 359
 360 arch_initcall(ja_pci_init);
 361
 362 void __init plat_mem_setup(void)
 363 {
 364         unsigned int tmpword;
 365
 366         board_time_init = momenco_time_init;
 367
 368         _machine_restart = momenco_jaguar_restart;
 369         _machine_halt = momenco_jaguar_halt;
 370         pm_power_off = momenco_jaguar_power_off;
 371
 372         /*
 373          * initrd_start = (ulong)jaguar_initrd_start;
 374          * initrd_end = (ulong)jaguar_initrd_start + (ulong)jaguar_initrd_size;
 375          * initrd_below_start_ok = 1;
 376          */
 377
 378         wire_stupidity_into_tlb();
 379
 380         /*
 381          * shut down ethernet ports, just to be sure our memory doesn't get
 382          * corrupted by random ethernet traffic.
 383          */
 384         MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
 385         MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
 386         MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(2), 0xff << 8);
 387         MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
 388         MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
 389         MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0xff << 8);
 390         while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
 391         while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
 392         while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(2)) & 0xff);
 393         while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
 394         while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
 395         while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(2)) & 0xff);
 396         MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),
 397                  MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
 398         MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),
 399                  MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
 400         MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(2),
 401                  MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(2)) & ~1);
 402
 403         /* Turn off the Bit-Error LED */
 404         JAGUAR_FPGA_WRITE(0x80, CLR);
 405
 406         tmpword = JAGUAR_FPGA_READ(BOARDREV);
 407         if (tmpword < 26)
 408                 printk("Momentum Jaguar-ATX: Board Assembly Rev. %c\n",
 409                         'A'+tmpword);
 410         else
 411                 printk("Momentum Jaguar-ATX: Board Assembly Revision #0x%x\n",
 412                         tmpword);
 413
 414         tmpword = JAGUAR_FPGA_READ(FPGA_REV);
 415         printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
 416         tmpword = JAGUAR_FPGA_READ(RESET_STATUS);
 417         printk("Reset reason: 0x%x\n", tmpword);
 418         switch (tmpword) {
 419         case 0x1:
 420                 printk("  - Power-up reset\n");
 421                 break;
 422         case 0x2:
 423                 printk("  - Push-button reset\n");
 424                 break;
 425         case 0x8:
 426                 printk("  - Watchdog reset\n");
 427                 break;
 428         case 0x10:
 429                 printk("  - JTAG reset\n");
 430                 break;
 431         default:
 432                 printk("  - Unknown reset cause\n");
 433         }
 434         reset_reason = tmpword;
 435         JAGUAR_FPGA_WRITE(0xff, RESET_STATUS);
 436
 437         tmpword = JAGUAR_FPGA_READ(BOARD_STATUS);
 438         printk("Board Status register: 0x%02x\n", tmpword);
 439         printk("  - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
 440         printk("  - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
 441
 442         /* 256MiB of RM9000x2 DDR */
 443 //      add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
 444
 445         /* 128MiB of MV-64340 DDR */
 446 //      add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
 447
 448         /* XXX Memory configuration should be picked up from PMON2k */
 449 #ifdef CONFIG_JAGUAR_DMALOW
 450         printk("Jaguar ATX DMA-low mode set\n");
 451         add_memory_region(0x00000000, 0x08000000, BOOT_MEM_RAM);
 452         add_memory_region(0x08000000, 0x10000000, BOOT_MEM_RAM);
 453 #else
 454         /* 128MiB of MV-64340 DDR RAM */
 455         printk("Jaguar ATX DMA-low mode is not set\n");
 456         add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
 457 #endif
 458
 459 #ifdef GEMDEBUG_TRACEBUFFER
 460         {
 461           unsigned int tbControl;
 462           tbControl =
 463             0 << 26 |  /* post trigger delay 0 */
 464                     0x2 << 16 |         /* sequential trace mode */
 465             //      0x0 << 16 |         /* non-sequential trace mode */
 466             //      0xf << 4 |          /* watchpoints disabled */
 467             2 << 2 |            /* armed */
 468             2 ;                 /* interrupt disabled  */
 469           printk ("setting     tbControl = %08lx\n", tbControl);
 470           write_32bit_cp0_set1_register($22, tbControl);
 471           __asm__ __volatile__(".set noreorder\n\t" \
 472                                "nop; nop; nop; nop; nop; nop;\n\t" \
 473                                "nop; nop; nop; nop; nop; nop;\n\t" \
 474                                ".set reorder\n\t");
 475
 476         }
 477 #endif
 478 }