2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <linux/kernel.h>
36 #include <linux/init.h>
37 #include <linux/linkage.h>
38 #include <linux/interrupt.h>
40 #include <linux/slab.h>
41 #include <linux/irq.h>
43 #include <asm/errno.h>
44 #include <asm/signal.h>
45 #include <asm/ptrace.h>
46 #include <asm/mipsregs.h>
47 #include <asm/thread_info.h>
49 #include <asm/netlogic/mips-extns.h>
50 #include <asm/netlogic/interrupt.h>
51 #include <asm/netlogic/haldefs.h>
52 #include <asm/netlogic/common.h>
54 #if defined(CONFIG_CPU_XLP)
55 #include <asm/netlogic/xlp-hal/iomap.h>
56 #include <asm/netlogic/xlp-hal/xlp.h>
57 #include <asm/netlogic/xlp-hal/pic.h>
58 #elif defined(CONFIG_CPU_XLR)
59 #include <asm/netlogic/xlr/iomap.h>
60 #include <asm/netlogic/xlr/pic.h>
61 #include <asm/netlogic/xlr/fmn.h>
67 #define SMP_IRQ_MASK ((1ULL << IRQ_IPI_SMP_FUNCTION) | \
68 (1ULL << IRQ_IPI_SMP_RESCHEDULE))
70 #define SMP_IRQ_MASK 0
72 #define PERCPU_IRQ_MASK (SMP_IRQ_MASK | (1ull << IRQ_TIMER) | \
76 void (*extra_ack
)(struct irq_data
*);
77 struct nlm_soc_info
*node
;
83 static void xlp_pic_enable(struct irq_data
*d
)
86 struct nlm_pic_irq
*pd
= irq_data_get_irq_handler_data(d
);
89 spin_lock_irqsave(&pd
->node
->piclock
, flags
);
90 nlm_pic_enable_irt(pd
->node
->picbase
, pd
->irt
);
91 spin_unlock_irqrestore(&pd
->node
->piclock
, flags
);
94 static void xlp_pic_disable(struct irq_data
*d
)
96 struct nlm_pic_irq
*pd
= irq_data_get_irq_handler_data(d
);
100 spin_lock_irqsave(&pd
->node
->piclock
, flags
);
101 nlm_pic_disable_irt(pd
->node
->picbase
, pd
->irt
);
102 spin_unlock_irqrestore(&pd
->node
->piclock
, flags
);
105 static void xlp_pic_mask_ack(struct irq_data
*d
)
107 struct nlm_pic_irq
*pd
= irq_data_get_irq_handler_data(d
);
108 uint64_t mask
= 1ull << pd
->picirq
;
110 write_c0_eirr(mask
); /* ack by writing EIRR */
113 static void xlp_pic_unmask(struct irq_data
*d
)
115 struct nlm_pic_irq
*pd
= irq_data_get_irq_handler_data(d
);
123 /* Ack is a single write, no need to lock */
124 nlm_pic_ack(pd
->node
->picbase
, pd
->irt
);
127 static struct irq_chip xlp_pic
= {
129 .irq_enable
= xlp_pic_enable
,
130 .irq_disable
= xlp_pic_disable
,
131 .irq_mask_ack
= xlp_pic_mask_ack
,
132 .irq_unmask
= xlp_pic_unmask
,
135 static void cpuintr_disable(struct irq_data
*d
)
138 uint64_t mask
= 1ull << d
->irq
;
140 eimr
= read_c0_eimr();
141 write_c0_eimr(eimr
& ~mask
);
144 static void cpuintr_enable(struct irq_data
*d
)
147 uint64_t mask
= 1ull << d
->irq
;
149 eimr
= read_c0_eimr();
150 write_c0_eimr(eimr
| mask
);
153 static void cpuintr_ack(struct irq_data
*d
)
155 uint64_t mask
= 1ull << d
->irq
;
160 static void cpuintr_nop(struct irq_data
*d
)
162 WARN(d
->irq
>= PIC_IRQ_BASE
, "Bad irq %d", d
->irq
);
166 * Chip definition for CPU originated interrupts(timer, msg) and
169 struct irq_chip nlm_cpu_intr
= {
170 .name
= "XLP-CPU-INTR",
171 .irq_enable
= cpuintr_enable
,
172 .irq_disable
= cpuintr_disable
,
173 .irq_mask
= cpuintr_nop
,
174 .irq_ack
= cpuintr_nop
,
175 .irq_eoi
= cpuintr_ack
,
178 static void __init
nlm_init_percpu_irqs(void)
182 for (i
= 0; i
< PIC_IRT_FIRST_IRQ
; i
++)
183 irq_set_chip_and_handler(i
, &nlm_cpu_intr
, handle_percpu_irq
);
185 irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION
, &nlm_cpu_intr
,
186 nlm_smp_function_ipi_handler
);
187 irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE
, &nlm_cpu_intr
,
188 nlm_smp_resched_ipi_handler
);
192 void nlm_setup_pic_irq(int node
, int picirq
, int irq
, int irt
)
194 struct nlm_pic_irq
*pic_data
;
197 xirq
= nlm_irq_to_xirq(node
, irq
);
198 pic_data
= kzalloc(sizeof(*pic_data
), GFP_KERNEL
);
199 BUG_ON(pic_data
== NULL
);
201 pic_data
->picirq
= picirq
;
202 pic_data
->node
= nlm_get_node(node
);
203 irq_set_chip_and_handler(xirq
, &xlp_pic
, handle_level_irq
);
204 irq_set_handler_data(xirq
, pic_data
);
207 void nlm_set_pic_extra_ack(int node
, int irq
, void (*xack
)(struct irq_data
*))
209 struct nlm_pic_irq
*pic_data
;
212 xirq
= nlm_irq_to_xirq(node
, irq
);
213 pic_data
= irq_get_handler_data(xirq
);
214 pic_data
->extra_ack
= xack
;
217 static void nlm_init_node_irqs(int node
)
221 struct nlm_soc_info
*nodep
;
223 pr_info("Init IRQ for node %d\n", node
);
224 nodep
= nlm_get_node(node
);
225 irqmask
= PERCPU_IRQ_MASK
;
226 for (i
= PIC_IRT_FIRST_IRQ
; i
<= PIC_IRT_LAST_IRQ
; i
++) {
227 irt
= nlm_irq_to_irt(i
);
230 nlm_setup_pic_irq(node
, i
, i
, irt
);
231 /* set interrupts to first cpu in node */
232 nlm_pic_init_irt(nodep
->picbase
, irt
, i
,
233 node
* NLM_CPUS_PER_NODE
);
234 irqmask
|= (1ull << i
);
236 nodep
->irqmask
= irqmask
;
239 void __init
arch_init_irq(void)
241 /* Initialize the irq descriptors */
242 nlm_init_percpu_irqs();
243 nlm_init_node_irqs(0);
244 write_c0_eimr(nlm_current_node()->irqmask
);
245 #if defined(CONFIG_CPU_XLR)
250 void nlm_smp_irq_init(int hwcpuid
)
254 node
= hwcpuid
/ NLM_CPUS_PER_NODE
;
255 cpu
= hwcpuid
% NLM_CPUS_PER_NODE
;
257 if (cpu
== 0 && node
!= 0)
258 nlm_init_node_irqs(node
);
259 write_c0_eimr(nlm_current_node()->irqmask
);
262 asmlinkage
void plat_irq_dispatch(void)
268 eirr
= read_c0_eirr() & read_c0_eimr();
270 i
= __ilog2_u64(eirr
);
274 /* per-CPU IRQs don't need translation */
275 if (eirr
& PERCPU_IRQ_MASK
) {
280 /* top level irq handling */
281 do_IRQ(nlm_irq_to_xirq(node
, i
));