arch/mips/netlogic/common/reset.S

   1 /*
   2  * Copyright 2003-2013 Broadcom Corporation.
   3  * All Rights Reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the Broadcom
   9  * license below:
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  *
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in
  19  *    the documentation and/or other materials provided with the
  20  *    distribution.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
  23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <linux/init.h>
  36
  37 #include <asm/asm.h>
  38 #include <asm/asm-offsets.h>
  39 #include <asm/regdef.h>
  40 #include <asm/mipsregs.h>
  41 #include <asm/stackframe.h>
  42 #include <asm/asmmacro.h>
  43 #include <asm/addrspace.h>
  44
  45 #include <asm/netlogic/common.h>
  46
  47 #include <asm/netlogic/xlp-hal/iomap.h>
  48 #include <asm/netlogic/xlp-hal/xlp.h>
  49 #include <asm/netlogic/xlp-hal/sys.h>
  50 #include <asm/netlogic/xlp-hal/cpucontrol.h>
  51
  52 #define CP0_EBASE       $15
  53 #define SYS_CPU_COHERENT_BASE(node)     CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
  54                         XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \
  55                         SYS_CPU_NONCOHERENT_MODE * 4
  56
  57 /* Enable XLP features and workarounds in the LSU */
  58 .macro xlp_config_lsu
  59         li      t0, LSU_DEFEATURE
  60         mfcr    t1, t0
  61
  62         lui     t2, 0xc080      /* SUE, Enable Unaligned Access, L2HPE */
  63         or      t1, t1, t2
  64         mtcr    t1, t0
  65
  66         li      t0, ICU_DEFEATURE
  67         mfcr    t1, t0
  68         ori     t1, 0x1000      /* Enable Icache partitioning */
  69         mtcr    t1, t0
  70
  71         li      t0, SCHED_DEFEATURE
  72         lui     t1, 0x0100      /* Disable BRU accepting ALU ops */
  73         mtcr    t1, t0
  74 .endm
  75
  76 /*
  77  * Low level flush for L1D cache on XLP, the normal cache ops does
  78  * not do the complete and correct cache flush.
  79  */
  80 .macro  xlp_flush_l1_dcache
  81         li      t0, LSU_DEBUG_DATA0
  82         li      t1, LSU_DEBUG_ADDR
  83         li      t2, 0           /* index */
  84         li      t3, 0x1000      /* loop count */
  85 1:
  86         sll     v0, t2, 5
  87         mtcr    zero, t0
  88         ori     v1, v0, 0x3     /* way0 | write_enable | write_active */
  89         mtcr    v1, t1
  90 2:
  91         mfcr    v1, t1
  92         andi    v1, 0x1         /* wait for write_active == 0 */
  93         bnez    v1, 2b
  94         nop
  95         mtcr    zero, t0
  96         ori     v1, v0, 0x7     /* way1 | write_enable | write_active */
  97         mtcr    v1, t1
  98 3:
  99         mfcr    v1, t1
 100         andi    v1, 0x1         /* wait for write_active == 0 */
 101         bnez    v1, 3b
 102         nop
 103         addi    t2, 1
 104         bne     t3, t2, 1b
 105         nop
 106 .endm
 107
 108 /*
 109  * nlm_reset_entry will be copied to the reset entry point for
 110  * XLR and XLP. The XLP cores start here when they are woken up. This
 111  * is also the NMI entry point.
 112  *
 113  * We use scratch reg 6/7 to save k0/k1 and check for NMI first.
 114  *
 115  * The data corresponding to reset/NMI is stored at RESET_DATA_PHYS
 116  * location, this will have the thread mask (used when core is woken up)
 117  * and the current NMI handler in case we reached here for an NMI.
 118  *
 119  * When a core or thread is newly woken up, it marks itself ready and
 120  * loops in a 'wait'. When the CPU really needs waking up, we send an NMI
 121  * IPI to it, with the NMI handler set to prom_boot_secondary_cpus
 122  */
 123         .set    noreorder
 124         .set    noat
 125         .set    arch=xlr        /* for mfcr/mtcr, XLR is sufficient */
 126
 127 FEXPORT(nlm_reset_entry)
 128         dmtc0   k0, $22, 6
 129         dmtc0   k1, $22, 7
 130         mfc0    k0, CP0_STATUS
 131         li      k1, 0x80000
 132         and     k1, k0, k1
 133         beqz    k1, 1f          /* go to real reset entry */
 134         nop
 135         li      k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */
 136         ld      k0, BOOT_NMI_HANDLER(k1)
 137         jr      k0
 138         nop
 139
 140 1:      /* Entry point on core wakeup */
 141         mfc0    t0, CP0_EBASE, 1
 142         mfc0    t1, CP0_EBASE, 1
 143         srl     t1, 5
 144         andi    t1, 0x3                 /* t1 <- node */
 145         li      t2, 0x40000
 146         mul     t3, t2, t1              /* t3 = node * 0x40000 */
 147         srl     t0, t0, 2
 148         and     t0, t0, 0x7             /* t0 <- core */
 149         li      t1, 0x1
 150         sll     t0, t1, t0
 151         nor     t0, t0, zero            /* t0 <- ~(1 << core) */
 152         li      t2, SYS_CPU_COHERENT_BASE(0)
 153         add     t2, t2, t3              /* t2 <- SYS offset for node */
 154         lw      t1, 0(t2)
 155         and     t1, t1, t0
 156         sw      t1, 0(t2)
 157
 158         /* read back to ensure complete */
 159         lw      t1, 0(t2)
 160         sync
 161
 162         /* Configure LSU on Non-0 Cores. */
 163         xlp_config_lsu
 164         /* FALL THROUGH */
 165
 166 /*
 167  * Wake up sibling threads from the initial thread in
 168  * a core.
 169  */
 170 EXPORT(nlm_boot_siblings)
 171         /* core L1D flush before enable threads */
 172         xlp_flush_l1_dcache
 173         /* Enable hw threads by writing to MAP_THREADMODE of the core */
 174         li      t0, CKSEG1ADDR(RESET_DATA_PHYS)
 175         lw      t1, BOOT_THREAD_MODE(t0)        /* t1 <- thread mode */
 176         li      t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
 177         mfcr    t2, t0
 178         or      t2, t2, t1
 179         mtcr    t2, t0
 180
 181         /*
 182          * The new hardware thread starts at the next instruction
 183          * For all the cases other than core 0 thread 0, we will
 184         * jump to the secondary wait function.
 185         */
 186         mfc0    v0, CP0_EBASE, 1
 187         andi    v0, 0x3ff               /* v0 <- node/core */
 188
 189         beqz    v0, 4f          /* boot cpu (cpuid == 0)? */
 190         nop
 191
 192         /* setup status reg */
 193         move    t1, zero
 194 #ifdef CONFIG_64BIT
 195         ori     t1, ST0_KX
 196 #endif
 197         mtc0    t1, CP0_STATUS
 198
 199         /* mark CPU ready, careful here, previous mtcr trashed registers */
 200         li      t3, CKSEG1ADDR(RESET_DATA_PHYS)
 201         ADDIU   t1, t3, BOOT_CPU_READY
 202         sll     v1, v0, 2
 203         PTR_ADDU t1, v1
 204         li      t2, 1
 205         sw      t2, 0(t1)
 206         /* Wait until NMI hits */
 207 3:      wait
 208         b       3b
 209         nop
 210
 211         /*
 212          * For the boot CPU, we have to restore registers and
 213          * return
 214          */
 215 4:      dmfc0   t0, $4, 2       /* restore SP from UserLocal */
 216         li      t1, 0xfadebeef
 217         dmtc0   t1, $4, 2       /* restore SP from UserLocal */
 218         PTR_SUBU sp, t0, PT_SIZE
 219         RESTORE_ALL
 220         jr      ra
 221         nop
 222 EXPORT(nlm_reset_entry_end)
 223
 224 LEAF(nlm_init_boot_cpu)
 225 #ifdef CONFIG_CPU_XLP
 226         xlp_config_lsu
 227 #endif
 228         jr      ra
 229         nop
 230 END(nlm_init_boot_cpu)