arch/mips/netlogic/common/smp.c

   1 /*
   2  * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
   3  * reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the NetLogic
   9  * license below:
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  *
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in
  19  *    the documentation and/or other materials provided with the
  20  *    distribution.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
  23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <linux/kernel.h>
  36 #include <linux/delay.h>
  37 #include <linux/init.h>
  38 #include <linux/sched/task_stack.h>
  39 #include <linux/smp.h>
  40 #include <linux/irq.h>
  41
  42 #include <asm/mmu_context.h>
  43
  44 #include <asm/netlogic/interrupt.h>
  45 #include <asm/netlogic/mips-extns.h>
  46 #include <asm/netlogic/haldefs.h>
  47 #include <asm/netlogic/common.h>
  48
  49 #if defined(CONFIG_CPU_XLP)
  50 #include <asm/netlogic/xlp-hal/iomap.h>
  51 #include <asm/netlogic/xlp-hal/xlp.h>
  52 #include <asm/netlogic/xlp-hal/pic.h>
  53 #elif defined(CONFIG_CPU_XLR)
  54 #include <asm/netlogic/xlr/iomap.h>
  55 #include <asm/netlogic/xlr/pic.h>
  56 #include <asm/netlogic/xlr/xlr.h>
  57 #else
  58 #error "Unknown CPU"
  59 #endif
  60
  61 void nlm_send_ipi_single(int logical_cpu, unsigned int action)
  62 {
  63         unsigned int hwtid;
  64         uint64_t picbase;
  65
  66         /* node id is part of hwtid, and needed for send_ipi */
  67         hwtid = cpu_logical_map(logical_cpu);
  68         picbase = nlm_get_node(nlm_hwtid_to_node(hwtid))->picbase;
  69
  70         if (action & SMP_CALL_FUNCTION)
  71                 nlm_pic_send_ipi(picbase, hwtid, IRQ_IPI_SMP_FUNCTION, 0);
  72         if (action & SMP_RESCHEDULE_YOURSELF)
  73                 nlm_pic_send_ipi(picbase, hwtid, IRQ_IPI_SMP_RESCHEDULE, 0);
  74 }
  75
  76 void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
  77 {
  78         int cpu;
  79
  80         for_each_cpu(cpu, mask) {
  81                 nlm_send_ipi_single(cpu, action);
  82         }
  83 }
  84
  85 /* IRQ_IPI_SMP_FUNCTION Handler */
  86 void nlm_smp_function_ipi_handler(struct irq_desc *desc)
  87 {
  88         unsigned int irq = irq_desc_get_irq(desc);
  89         clear_c0_eimr(irq);
  90         ack_c0_eirr(irq);
  91         generic_smp_call_function_interrupt();
  92         set_c0_eimr(irq);
  93 }
  94
  95 /* IRQ_IPI_SMP_RESCHEDULE  handler */
  96 void nlm_smp_resched_ipi_handler(struct irq_desc *desc)
  97 {
  98         unsigned int irq = irq_desc_get_irq(desc);
  99         clear_c0_eimr(irq);
 100         ack_c0_eirr(irq);
 101         scheduler_ipi();
 102         set_c0_eimr(irq);
 103 }
 104
 105 /*
 106  * Called before going into mips code, early cpu init
 107  */
 108 void nlm_early_init_secondary(int cpu)
 109 {
 110         change_c0_config(CONF_CM_CMASK, 0x3);
 111 #ifdef CONFIG_CPU_XLP
 112         xlp_mmu_init();
 113 #endif
 114         write_c0_ebase(nlm_current_node()->ebase);
 115 }
 116
 117 /*
 118  * Code to run on secondary just after probing the CPU
 119  */
 120 static void nlm_init_secondary(void)
 121 {
 122         int hwtid;
 123
 124         hwtid = hard_smp_processor_id();
 125         current_cpu_data.core = hwtid / NLM_THREADS_PER_CORE;
 126         current_cpu_data.package = nlm_nodeid();
 127         nlm_percpu_init(hwtid);
 128         nlm_smp_irq_init(hwtid);
 129 }
 130
 131 void nlm_prepare_cpus(unsigned int max_cpus)
 132 {
 133         /* declare we are SMT capable */
 134         smp_num_siblings = nlm_threads_per_core;
 135 }
 136
 137 void nlm_smp_finish(void)
 138 {
 139         local_irq_enable();
 140 }
 141
 142 /*
 143  * Boot all other cpus in the system, initialize them, and bring them into
 144  * the boot function
 145  */
 146 unsigned long nlm_next_gp;
 147 unsigned long nlm_next_sp;
 148 static cpumask_t phys_cpu_present_mask;
 149
 150 void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
 151 {
 152         uint64_t picbase;
 153         int hwtid;
 154
 155         hwtid = cpu_logical_map(logical_cpu);
 156         picbase = nlm_get_node(nlm_hwtid_to_node(hwtid))->picbase;
 157
 158         nlm_next_sp = (unsigned long)__KSTK_TOS(idle);
 159         nlm_next_gp = (unsigned long)task_thread_info(idle);
 160
 161         /* barrier for sp/gp store above */
 162         __sync();
 163         nlm_pic_send_ipi(picbase, hwtid, 1, 1);  /* NMI */
 164 }
 165
 166 void __init nlm_smp_setup(void)
 167 {
 168         unsigned int boot_cpu;
 169         int num_cpus, i, ncore, node;
 170         volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY);
 171
 172         boot_cpu = hard_smp_processor_id();
 173         cpumask_clear(&phys_cpu_present_mask);
 174
 175         cpumask_set_cpu(boot_cpu, &phys_cpu_present_mask);
 176         __cpu_number_map[boot_cpu] = 0;
 177         __cpu_logical_map[0] = boot_cpu;
 178         set_cpu_possible(0, true);
 179
 180         num_cpus = 1;
 181         for (i = 0; i < NR_CPUS; i++) {
 182                 /*
 183                  * cpu_ready array is not set for the boot_cpu,
 184                  * it is only set for ASPs (see smpboot.S)
 185                  */
 186                 if (cpu_ready[i]) {
 187                         cpumask_set_cpu(i, &phys_cpu_present_mask);
 188                         __cpu_number_map[i] = num_cpus;
 189                         __cpu_logical_map[num_cpus] = i;
 190                         set_cpu_possible(num_cpus, true);
 191                         node = nlm_hwtid_to_node(i);
 192                         cpumask_set_cpu(num_cpus, &nlm_get_node(node)->cpumask);
 193                         ++num_cpus;
 194                 }
 195         }
 196
 197         pr_info("Physical CPU mask: %*pb\n",
 198                 cpumask_pr_args(&phys_cpu_present_mask));
 199         pr_info("Possible CPU mask: %*pb\n",
 200                 cpumask_pr_args(cpu_possible_mask));
 201
 202         /* check with the cores we have woken up */
 203         for (ncore = 0, i = 0; i < NLM_NR_NODES; i++)
 204                 ncore += hweight32(nlm_get_node(i)->coremask);
 205
 206         pr_info("Detected (%dc%dt) %d Slave CPU(s)\n", ncore,
 207                 nlm_threads_per_core, num_cpus);
 208
 209         /* switch NMI handler to boot CPUs */
 210         nlm_set_nmi_handler(nlm_boot_secondary_cpus);
 211 }
 212
 213 static int nlm_parse_cpumask(cpumask_t *wakeup_mask)
 214 {
 215         uint32_t core0_thr_mask, core_thr_mask;
 216         int threadmode, i, j;
 217
 218         core0_thr_mask = 0;
 219         for (i = 0; i < NLM_THREADS_PER_CORE; i++)
 220                 if (cpumask_test_cpu(i, wakeup_mask))
 221                         core0_thr_mask |= (1 << i);
 222         switch (core0_thr_mask) {
 223         case 1:
 224                 nlm_threads_per_core = 1;
 225                 threadmode = 0;
 226                 break;
 227         case 3:
 228                 nlm_threads_per_core = 2;
 229                 threadmode = 2;
 230                 break;
 231         case 0xf:
 232                 nlm_threads_per_core = 4;
 233                 threadmode = 3;
 234                 break;
 235         default:
 236                 goto unsupp;
 237         }
 238
 239         /* Verify other cores CPU masks */
 240         for (i = 0; i < NR_CPUS; i += NLM_THREADS_PER_CORE) {
 241                 core_thr_mask = 0;
 242                 for (j = 0; j < NLM_THREADS_PER_CORE; j++)
 243                         if (cpumask_test_cpu(i + j, wakeup_mask))
 244                                 core_thr_mask |= (1 << j);
 245                 if (core_thr_mask != 0 && core_thr_mask != core0_thr_mask)
 246                                 goto unsupp;
 247         }
 248         return threadmode;
 249
 250 unsupp:
 251         panic("Unsupported CPU mask %*pb", cpumask_pr_args(wakeup_mask));
 252         return 0;
 253 }
 254
 255 int nlm_wakeup_secondary_cpus(void)
 256 {
 257         u32 *reset_data;
 258         int threadmode;
 259
 260         /* verify the mask and setup core config variables */
 261         threadmode = nlm_parse_cpumask(&nlm_cpumask);
 262
 263         /* Setup CPU init parameters */
 264         reset_data = nlm_get_boot_data(BOOT_THREAD_MODE);
 265         *reset_data = threadmode;
 266
 267 #ifdef CONFIG_CPU_XLP
 268         xlp_wakeup_secondary_cpus();
 269 #else
 270         xlr_wakeup_secondary_cpus();
 271 #endif
 272         return 0;
 273 }
 274
 275 struct plat_smp_ops nlm_smp_ops = {
 276         .send_ipi_single        = nlm_send_ipi_single,
 277         .send_ipi_mask          = nlm_send_ipi_mask,
 278         .init_secondary         = nlm_init_secondary,
 279         .smp_finish             = nlm_smp_finish,
 280         .boot_secondary         = nlm_boot_secondary,
 281         .smp_setup              = nlm_smp_setup,
 282         .prepare_cpus           = nlm_prepare_cpus,
 283 };