arch/mips/netlogic/common/smpboot.S

   1 /*
   2  * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
   3  * reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the NetLogic
   9  * license below:
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  *
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in
  19  *    the documentation and/or other materials provided with the
  20  *    distribution.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
  23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <linux/init.h>
  36
  37 #include <asm/asm.h>
  38 #include <asm/asm-offsets.h>
  39 #include <asm/regdef.h>
  40 #include <asm/mipsregs.h>
  41 #include <asm/stackframe.h>
  42 #include <asm/asmmacro.h>
  43 #include <asm/addrspace.h>
  44
  45 #include <asm/netlogic/common.h>
  46
  47 #include <asm/netlogic/xlp-hal/iomap.h>
  48 #include <asm/netlogic/xlp-hal/xlp.h>
  49 #include <asm/netlogic/xlp-hal/sys.h>
  50 #include <asm/netlogic/xlp-hal/cpucontrol.h>
  51
  52 #define CP0_EBASE       $15
  53 #define SYS_CPU_COHERENT_BASE(node)     CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
  54                         XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \
  55                         SYS_CPU_NONCOHERENT_MODE * 4
  56
  57 #define XLP_AX_WORKAROUND       /* enable Ax silicon workarounds */
  58
  59 /* Enable XLP features and workarounds in the LSU */
  60 .macro xlp_config_lsu
  61         li      t0, LSU_DEFEATURE
  62         mfcr    t1, t0
  63
  64         lui     t2, 0xc080      /* SUE, Enable Unaligned Access, L2HPE */
  65         or      t1, t1, t2
  66 #ifdef XLP_AX_WORKAROUND
  67         li      t2, ~0xe        /* S1RCM */
  68         and     t1, t1, t2
  69 #endif
  70         mtcr    t1, t0
  71
  72 #ifdef XLP_AX_WORKAROUND
  73         li      t0, SCHED_DEFEATURE
  74         lui     t1, 0x0100      /* Disable BRU accepting ALU ops */
  75         mtcr    t1, t0
  76 #endif
  77 .endm
  78
  79 /*
  80  * This is the code that will be copied to the reset entry point for
  81  * XLR and XLP. The XLP cores start here when they are woken up. This
  82  * is also the NMI entry point.
  83  */
  84 .macro  xlp_flush_l1_dcache
  85         li      t0, LSU_DEBUG_DATA0
  86         li      t1, LSU_DEBUG_ADDR
  87         li      t2, 0           /* index */
  88         li      t3, 0x1000      /* loop count */
  89 1:
  90         sll     v0, t2, 5
  91         mtcr    zero, t0
  92         ori     v1, v0, 0x3     /* way0 | write_enable | write_active */
  93         mtcr    v1, t1
  94 2:
  95         mfcr    v1, t1
  96         andi    v1, 0x1         /* wait for write_active == 0 */
  97         bnez    v1, 2b
  98         nop
  99         mtcr    zero, t0
 100         ori     v1, v0, 0x7     /* way1 | write_enable | write_active */
 101         mtcr    v1, t1
 102 3:
 103         mfcr    v1, t1
 104         andi    v1, 0x1         /* wait for write_active == 0 */
 105         bnez    v1, 3b
 106         nop
 107         addi    t2, 1
 108         bne     t3, t2, 1b
 109         nop
 110 .endm
 111
 112 /*
 113  * The cores can come start when they are woken up. This is also the NMI
 114  * entry, so check that first.
 115  *
 116  * The data corresponding to reset/NMI is stored at RESET_DATA_PHYS
 117  * location, this will have the thread mask (used when core is woken up)
 118  * and the current NMI handler in case we reached here for an NMI.
 119  *
 120  * When a core or thread is newly woken up, it loops in a 'wait'. When
 121  * the CPU really needs waking up, we send an NMI to it, with the NMI
 122  * handler set to prom_boot_secondary_cpus
 123  */
 124
 125         .set    noreorder
 126         .set    noat
 127         .set    arch=xlr        /* for mfcr/mtcr, XLR is sufficient */
 128
 129 FEXPORT(nlm_reset_entry)
 130         dmtc0   k0, $22, 6
 131         dmtc0   k1, $22, 7
 132         mfc0    k0, CP0_STATUS
 133         li      k1, 0x80000
 134         and     k1, k0, k1
 135         beqz    k1, 1f          /* go to real reset entry */
 136         nop
 137         li      k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */
 138         ld      k0, BOOT_NMI_HANDLER(k1)
 139         jr      k0
 140         nop
 141
 142 1:      /* Entry point on core wakeup */
 143         mfc0    t0, CP0_EBASE, 1
 144         mfc0    t1, CP0_EBASE, 1
 145         srl     t1, 5
 146         andi    t1, 0x3                 /* t1 <- node */
 147         li      t2, 0x40000
 148         mul     t3, t2, t1              /* t3 = node * 0x40000 */
 149         srl     t0, t0, 2
 150         and     t0, t0, 0x7             /* t0 <- core */
 151         li      t1, 0x1
 152         sll     t0, t1, t0
 153         nor     t0, t0, zero            /* t0 <- ~(1 << core) */
 154         li      t2, SYS_CPU_COHERENT_BASE(0)
 155         add     t2, t2, t3              /* t2 <- SYS offset for node */
 156         lw      t1, 0(t2)
 157         and     t1, t1, t0
 158         sw      t1, 0(t2)
 159
 160         /* read back to ensure complete */
 161         lw      t1, 0(t2)
 162         sync
 163
 164         /* Configure LSU on Non-0 Cores. */
 165         xlp_config_lsu
 166         /* FALL THROUGH */
 167
 168 /*
 169  * Wake up sibling threads from the initial thread in
 170  * a core.
 171  */
 172 EXPORT(nlm_boot_siblings)
 173         /* core L1D flush before enable threads */
 174         xlp_flush_l1_dcache
 175         /* Enable hw threads by writing to MAP_THREADMODE of the core */
 176         li      t0, CKSEG1ADDR(RESET_DATA_PHYS)
 177         lw      t1, BOOT_THREAD_MODE(t0)        /* t1 <- thread mode */
 178         li      t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
 179         mfcr    t2, t0
 180         or      t2, t2, t1
 181         mtcr    t2, t0
 182
 183         /*
 184          * The new hardware thread starts at the next instruction
 185          * For all the cases other than core 0 thread 0, we will
 186         * jump to the secondary wait function.
 187         */
 188         mfc0    v0, CP0_EBASE, 1
 189         andi    v0, 0x3ff               /* v0 <- node/core */
 190
 191         /* Init MMU in the first thread after changing THREAD_MODE
 192          * register (Ax Errata?)
 193          */
 194         andi    v1, v0, 0x3             /* v1 <- thread id */
 195         bnez    v1, 2f
 196         nop
 197
 198         li      t0, MMU_SETUP
 199         li      t1, 0
 200         mtcr    t1, t0
 201         _ehb
 202
 203 2:      beqz    v0, 4f          /* boot cpu (cpuid == 0)? */
 204         nop
 205
 206         /* setup status reg */
 207         move    t1, zero
 208 #ifdef CONFIG_64BIT
 209         ori     t1, ST0_KX
 210 #endif
 211         mtc0    t1, CP0_STATUS
 212         /* mark CPU ready */
 213         PTR_LA  t1, nlm_cpu_ready
 214         sll     v1, v0, 2
 215         PTR_ADDU t1, v1
 216         li      t2, 1
 217         sw      t2, 0(t1)
 218         /* Wait until NMI hits */
 219 3:      wait
 220         j       3b
 221         nop
 222
 223         /*
 224          * For the boot CPU, we have to restore registers and
 225          * return
 226          */
 227 4:      dmfc0   t0, $4, 2       /* restore SP from UserLocal */
 228         li      t1, 0xfadebeef
 229         dmtc0   t1, $4, 2       /* restore SP from UserLocal */
 230         PTR_SUBU sp, t0, PT_SIZE
 231         RESTORE_ALL
 232         jr   ra
 233         nop
 234 EXPORT(nlm_reset_entry_end)
 235
 236 FEXPORT(xlp_boot_core0_siblings)        /* "Master" cpu starts from here */
 237         xlp_config_lsu
 238         dmtc0   sp, $4, 2               /* SP saved in UserLocal */
 239         SAVE_ALL
 240         sync
 241         /* find the location to which nlm_boot_siblings was relocated */
 242         li      t0, CKSEG1ADDR(RESET_VEC_PHYS)
 243         dla     t1, nlm_reset_entry
 244         dla     t2, nlm_boot_siblings
 245         dsubu   t2, t1
 246         daddu   t2, t0
 247         /* call it */
 248         jr      t2
 249         nop
 250         /* not reached */
 251
 252         __CPUINIT
 253 NESTED(nlm_boot_secondary_cpus, 16, sp)
 254         /* Initialize CP0 Status */
 255         move    t1, zero
 256 #ifdef CONFIG_64BIT
 257         ori     t1, ST0_KX
 258 #endif
 259         mtc0    t1, CP0_STATUS
 260         PTR_LA  t1, nlm_next_sp
 261         PTR_L   sp, 0(t1)
 262         PTR_LA  t1, nlm_next_gp
 263         PTR_L   gp, 0(t1)
 264
 265         /* a0 has the processor id */
 266         mfc0    a0, CP0_EBASE, 1
 267         andi    a0, 0x3ff               /* a0 <- node/core */
 268         PTR_LA  t0, nlm_early_init_secondary
 269         jalr    t0
 270         nop
 271
 272         PTR_LA  t0, smp_bootstrap
 273         jr      t0
 274         nop
 275 END(nlm_boot_secondary_cpus)
 276         __FINIT
 277
 278 /*
 279  * In case of RMIboot bootloader which is used on XLR boards, the CPUs
 280  * be already woken up and waiting in bootloader code.
 281  * This will get them out of the bootloader code and into linux. Needed
 282  *  because the bootloader area will be taken and initialized by linux.
 283  */
 284         __CPUINIT
 285 NESTED(nlm_rmiboot_preboot, 16, sp)
 286         mfc0    t0, $15, 1      /* read ebase */
 287         andi    t0, 0x1f        /* t0 has the processor_id() */
 288         andi    t2, t0, 0x3     /* thread num */
 289         sll     t0, 2           /* offset in cpu array */
 290
 291         PTR_LA  t1, nlm_cpu_ready /* mark CPU ready */
 292         PTR_ADDU t1, t0
 293         li      t3, 1
 294         sw      t3, 0(t1)
 295
 296         bnez    t2, 1f          /* skip thread programming */
 297         nop                     /* for thread id != 0 */
 298
 299         /*
 300          * XLR MMU setup only for first thread in core
 301          */
 302         li      t0, 0x400
 303         mfcr    t1, t0
 304         li      t2, 6           /* XLR thread mode mask */
 305         nor     t3, t2, zero
 306         and     t2, t1, t2      /* t2 - current thread mode */
 307         li      v0, CKSEG1ADDR(RESET_DATA_PHYS)
 308         lw      v1, BOOT_THREAD_MODE(v0) /* v1 - new thread mode */
 309         sll     v1, 1
 310         beq     v1, t2, 1f      /* same as request value */
 311         nop                     /* nothing to do */
 312
 313         and     t2, t1, t3      /* mask out old thread mode */
 314         or      t1, t2, v1      /* put in new value */
 315         mtcr    t1, t0          /* update core control */
 316
 317 1:      wait
 318         j       1b
 319         nop
 320 END(nlm_rmiboot_preboot)
 321         __FINIT