arch/mips/netlogic/xlp/nlm_hal.c

   1 /*
   2  * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
   3  * reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the NetLogic
   9  * license below:
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  *
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in
  19  *    the documentation and/or other materials provided with the
  20  *    distribution.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
  23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <linux/types.h>
  36 #include <linux/kernel.h>
  37 #include <linux/mm.h>
  38 #include <linux/delay.h>
  39
  40 #include <asm/mipsregs.h>
  41 #include <asm/time.h>
  42
  43 #include <asm/netlogic/common.h>
  44 #include <asm/netlogic/haldefs.h>
  45 #include <asm/netlogic/xlp-hal/iomap.h>
  46 #include <asm/netlogic/xlp-hal/xlp.h>
  47 #include <asm/netlogic/xlp-hal/bridge.h>
  48 #include <asm/netlogic/xlp-hal/pic.h>
  49 #include <asm/netlogic/xlp-hal/sys.h>
  50
  51 /* Main initialization */
  52 void nlm_node_init(int node)
  53 {
  54         struct nlm_soc_info *nodep;
  55
  56         nodep = nlm_get_node(node);
  57         nodep->sysbase = nlm_get_sys_regbase(node);
  58         nodep->picbase = nlm_get_pic_regbase(node);
  59         nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1));
  60         if (cpu_is_xlp9xx())
  61                 nodep->socbus = xlp9xx_get_socbus(node);
  62         else
  63                 nodep->socbus = 0;
  64         spin_lock_init(&nodep->piclock);
  65 }
  66
  67 int nlm_irq_to_irt(int irq)
  68 {
  69         uint64_t pcibase;
  70         int devoff, irt;
  71
  72         /* bypass for 9xx */
  73         if (cpu_is_xlp9xx()) {
  74                 switch (irq) {
  75                 case PIC_UART_0_IRQ:
  76                         return 133;
  77                 case PIC_UART_1_IRQ:
  78                         return 134;
  79                 }
  80                 return -1;
  81         }
  82
  83         devoff = 0;
  84         switch (irq) {
  85         case PIC_UART_0_IRQ:
  86                 devoff = XLP_IO_UART0_OFFSET(0);
  87                 break;
  88         case PIC_UART_1_IRQ:
  89                 devoff = XLP_IO_UART1_OFFSET(0);
  90                 break;
  91         case PIC_MMC_IRQ:
  92                 devoff = XLP_IO_SD_OFFSET(0);
  93                 break;
  94         case PIC_I2C_0_IRQ:     /* I2C will be fixed up */
  95         case PIC_I2C_1_IRQ:
  96         case PIC_I2C_2_IRQ:
  97         case PIC_I2C_3_IRQ:
  98                 if (cpu_is_xlpii())
  99                         devoff = XLP2XX_IO_I2C_OFFSET(0);
 100                 else
 101                         devoff = XLP_IO_I2C0_OFFSET(0);
 102                 break;
 103         default:
 104                 if (cpu_is_xlpii()) {
 105                         switch (irq) {
 106                                 /* XLP2XX has three XHCI USB controller */
 107                         case PIC_2XX_XHCI_0_IRQ:
 108                                 devoff = XLP2XX_IO_USB_XHCI0_OFFSET(0);
 109                                 break;
 110                         case PIC_2XX_XHCI_1_IRQ:
 111                                 devoff = XLP2XX_IO_USB_XHCI1_OFFSET(0);
 112                                 break;
 113                         case PIC_2XX_XHCI_2_IRQ:
 114                                 devoff = XLP2XX_IO_USB_XHCI2_OFFSET(0);
 115                                 break;
 116                         }
 117                 } else {
 118                         switch (irq) {
 119                         case PIC_EHCI_0_IRQ:
 120                                 devoff = XLP_IO_USB_EHCI0_OFFSET(0);
 121                                 break;
 122                         case PIC_EHCI_1_IRQ:
 123                                 devoff = XLP_IO_USB_EHCI1_OFFSET(0);
 124                                 break;
 125                         case PIC_OHCI_0_IRQ:
 126                                 devoff = XLP_IO_USB_OHCI0_OFFSET(0);
 127                                 break;
 128                         case PIC_OHCI_1_IRQ:
 129                                 devoff = XLP_IO_USB_OHCI1_OFFSET(0);
 130                                 break;
 131                         case PIC_OHCI_2_IRQ:
 132                                 devoff = XLP_IO_USB_OHCI2_OFFSET(0);
 133                                 break;
 134                         case PIC_OHCI_3_IRQ:
 135                                 devoff = XLP_IO_USB_OHCI3_OFFSET(0);
 136                                 break;
 137                         }
 138                 }
 139         }
 140
 141         if (devoff != 0) {
 142                 pcibase = nlm_pcicfg_base(devoff);
 143                 irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff;
 144                 /* HW weirdness, I2C IRT entry has to be fixed up */
 145                 switch (irq) {
 146                 case PIC_I2C_1_IRQ:
 147                         irt = irt + 1; break;
 148                 case PIC_I2C_2_IRQ:
 149                         irt = irt + 2; break;
 150                 case PIC_I2C_3_IRQ:
 151                         irt = irt + 3; break;
 152                 }
 153         } else if (irq >= PIC_PCIE_LINK_LEGACY_IRQ(0) &&
 154                         irq <= PIC_PCIE_LINK_LEGACY_IRQ(3)) {
 155                 /* HW bug, PCI IRT entries are bad on early silicon, fix */
 156                 irt = PIC_IRT_PCIE_LINK_INDEX(irq -
 157                                         PIC_PCIE_LINK_LEGACY_IRQ_BASE);
 158         } else if (irq >= PIC_PCIE_LINK_MSI_IRQ(0) &&
 159                         irq <= PIC_PCIE_LINK_MSI_IRQ(3)) {
 160                 irt = -2;
 161         } else if (irq >= PIC_PCIE_MSIX_IRQ(0) &&
 162                         irq <= PIC_PCIE_MSIX_IRQ(3)) {
 163                 irt = -2;
 164         } else {
 165                 irt = -1;
 166         }
 167         return irt;
 168 }
 169
 170 unsigned int nlm_get_core_frequency(int node, int core)
 171 {
 172         unsigned int pll_divf, pll_divr, dfs_div, ext_div;
 173         unsigned int rstval, dfsval, denom;
 174         uint64_t num, sysbase;
 175
 176         sysbase = nlm_get_node(node)->sysbase;
 177         rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG);
 178         if (cpu_is_xlpii()) {
 179                 num = 1000000ULL * (400 * 3 + 100 * (rstval >> 26));
 180                 denom = 3;
 181         } else {
 182                 dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
 183                 pll_divf = ((rstval >> 10) & 0x7f) + 1;
 184                 pll_divr = ((rstval >> 8)  & 0x3) + 1;
 185                 ext_div  = ((rstval >> 30) & 0x3) + 1;
 186                 dfs_div  = ((dfsval >> (core * 4)) & 0xf) + 1;
 187
 188                 num = 800000000ULL * pll_divf;
 189                 denom = 3 * pll_divr * ext_div * dfs_div;
 190         }
 191         do_div(num, denom);
 192         return (unsigned int)num;
 193 }
 194
 195 /* Calculate Frequency to the PIC from PLL.
 196  * freq_out = ( ref_freq/2 * (6 + ctrl2[7:0]) + ctrl2[20:8]/2^13 ) /
 197  * ((2^ctrl0[7:5]) * Table(ctrl0[26:24]))
 198  */
 199 static unsigned int nlm_2xx_get_pic_frequency(int node)
 200 {
 201         u32 ctrl_val0, ctrl_val2, vco_post_div, pll_post_div;
 202         u32 mdiv, fdiv, pll_out_freq_den, reg_select, ref_div, pic_div;
 203         u64 ref_clk, sysbase, pll_out_freq_num, ref_clk_select;
 204
 205         sysbase = nlm_get_node(node)->sysbase;
 206
 207         /* Find ref_clk_base */
 208         ref_clk_select =
 209                 (nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG) >> 18) & 0x3;
 210         switch (ref_clk_select) {
 211         case 0:
 212                 ref_clk = 200000000ULL;
 213                 ref_div = 3;
 214                 break;
 215         case 1:
 216                 ref_clk = 100000000ULL;
 217                 ref_div = 1;
 218                 break;
 219         case 2:
 220                 ref_clk = 125000000ULL;
 221                 ref_div = 1;
 222                 break;
 223         case 3:
 224                 ref_clk = 400000000ULL;
 225                 ref_div = 3;
 226                 break;
 227         }
 228
 229         /* Find the clock source PLL device for PIC */
 230         reg_select = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_SEL) >> 22) & 0x3;
 231         switch (reg_select) {
 232         case 0:
 233                 ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0);
 234                 ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2);
 235                 break;
 236         case 1:
 237                 ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(0));
 238                 ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(0));
 239                 break;
 240         case 2:
 241                 ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(1));
 242                 ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(1));
 243                 break;
 244         case 3:
 245                 ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(2));
 246                 ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(2));
 247                 break;
 248         }
 249
 250         vco_post_div = (ctrl_val0 >> 5) & 0x7;
 251         pll_post_div = (ctrl_val0 >> 24) & 0x7;
 252         mdiv = ctrl_val2 & 0xff;
 253         fdiv = (ctrl_val2 >> 8) & 0xfff;
 254
 255         /* Find PLL post divider value */
 256         switch (pll_post_div) {
 257         case 1:
 258                 pll_post_div = 2;
 259                 break;
 260         case 3:
 261                 pll_post_div = 4;
 262                 break;
 263         case 7:
 264                 pll_post_div = 8;
 265                 break;
 266         case 6:
 267                 pll_post_div = 16;
 268                 break;
 269         case 0:
 270         default:
 271                 pll_post_div = 1;
 272                 break;
 273         }
 274
 275         fdiv = fdiv/(1 << 13);
 276         pll_out_freq_num = ((ref_clk >> 1) * (6 + mdiv)) + fdiv;
 277         pll_out_freq_den = (1 << vco_post_div) * pll_post_div * 3;
 278
 279         if (pll_out_freq_den > 0)
 280                 do_div(pll_out_freq_num, pll_out_freq_den);
 281
 282         /* PIC post divider, which happens after PLL */
 283         pic_div = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_DIV) >> 22) & 0x3;
 284         do_div(pll_out_freq_num, 1 << pic_div);
 285
 286         return pll_out_freq_num;
 287 }
 288
 289 unsigned int nlm_get_pic_frequency(int node)
 290 {
 291         /* TODO Has to calculate freq as like 2xx */
 292         if (cpu_is_xlp9xx())
 293                 return 250000000;
 294
 295         if (cpu_is_xlpii())
 296                 return nlm_2xx_get_pic_frequency(node);
 297         else
 298                 return 133333333;
 299 }
 300
 301 unsigned int nlm_get_cpu_frequency(void)
 302 {
 303         return nlm_get_core_frequency(0, 0);
 304 }
 305
 306 /*
 307  * Fills upto 8 pairs of entries containing the DRAM map of a node
 308  * if n < 0, get dram map for all nodes
 309  */
 310 int xlp_get_dram_map(int n, uint64_t *dram_map)
 311 {
 312         uint64_t bridgebase, base, lim;
 313         uint32_t val;
 314         int i, node, rv;
 315
 316         /* Look only at mapping on Node 0, we don't handle crazy configs */
 317         bridgebase = nlm_get_bridge_regbase(0);
 318         rv = 0;
 319         for (i = 0; i < 8; i++) {
 320                 val = nlm_read_bridge_reg(bridgebase,
 321                                         BRIDGE_DRAM_NODE_TRANSLN(i));
 322                 node = (val >> 1) & 0x3;
 323                 if (n >= 0 && n != node)
 324                         continue;
 325                 val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_BAR(i));
 326                 val = (val >>  12) & 0xfffff;
 327                 base = (uint64_t) val << 20;
 328                 val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_LIMIT(i));
 329                 val = (val >>  12) & 0xfffff;
 330                 if (val == 0)   /* BAR not used */
 331                         continue;
 332                 lim = ((uint64_t)val + 1) << 20;
 333                 dram_map[rv] = base;
 334                 dram_map[rv + 1] = lim;
 335                 rv += 2;
 336         }
 337         return rv;
 338 }